[REACTX] Fix 64 bit issues
[reactos.git] / ntoskrnl / kd / arm / kdbg.c
1 /*
2 * PROJECT: ReactOS Kernel
3 * LICENSE: BSD - See COPYING.ARM in the top level directory
4 * FILE: ntoskrnl/kd/arm/kdbg.c
5 * PURPOSE: Serial Port Kernel Debugging Transport Library
6 * PROGRAMMERS: ReactOS Portable Systems Group
7 */
8
9 /* INCLUDES *******************************************************************/
10
11 #include <ntoskrnl.h>
12 #include <arm/peripherals/pl011.h>
13 #define NDEBUG
14 #include <debug.h>
15
16 /* GLOBALS ********************************************************************/
17
18 CPPORT DefaultPort = {0, 0, 0};
19
20 //
21 // We need to build this in the configuration root and use KeFindConfigurationEntry
22 // to recover it later.
23 //
24 #define HACK 24000000
25
26 /* REACTOS FUNCTIONS **********************************************************/
27
28 NTSTATUS
29 NTAPI
30 KdDebuggerInitialize1(IN PLOADER_PARAMETER_BLOCK LoaderBlock OPTIONAL)
31 {
32 return STATUS_NOT_IMPLEMENTED;
33 }
34
35 BOOLEAN
36 NTAPI
37 KdPortInitializeEx(IN PCPPORT PortInformation,
38 IN ULONG ComPortNumber)
39 {
40 ULONG Divider, Remainder, Fraction;
41 ULONG Baudrate = PortInformation->BaudRate;
42
43 //
44 // Calculate baudrate clock divider and remainder
45 //
46 Divider = HACK / (16 * Baudrate);
47 Remainder = HACK % (16 * Baudrate);
48
49 //
50 // Calculate the fractional part
51 //
52 Fraction = (8 * Remainder / Baudrate) >> 1;
53 Fraction += (8 * Remainder / Baudrate) & 1;
54
55 //
56 // Disable interrupts
57 //
58 WRITE_REGISTER_ULONG((PULONG)UART_PL011_CR, 0);
59
60 //
61 // Set the baud rate
62 //
63 WRITE_REGISTER_ULONG((PULONG)UART_PL011_IBRD, Divider);
64 WRITE_REGISTER_ULONG((PULONG)UART_PL011_FBRD, Fraction);
65
66 //
67 // Set 8 bits for data, 1 stop bit, no parity, FIFO enabled
68 //
69 WRITE_REGISTER_ULONG((PULONG)UART_PL011_LCRH,
70 UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN);
71
72 //
73 // Clear and enable FIFO
74 //
75 WRITE_REGISTER_ULONG((PULONG)UART_PL011_CR,
76 UART_PL011_CR_UARTEN |
77 UART_PL011_CR_TXE |
78 UART_PL011_CR_RXE);
79
80 //
81 // Done
82 //
83 return TRUE;
84 }
85
86 BOOLEAN
87 NTAPI
88 KdPortGetByteEx(IN PCPPORT PortInformation,
89 OUT PUCHAR ByteReceived)
90 {
91 UNIMPLEMENTED;
92 while (TRUE);
93 return FALSE;
94 }
95
96 VOID
97 NTAPI
98 KdPortPutByteEx(IN PCPPORT PortInformation,
99 IN UCHAR ByteToSend)
100 {
101 //
102 // Wait for ready
103 //
104 while ((READ_REGISTER_ULONG((PULONG)UART_PL01x_FR) & UART_PL01x_FR_TXFF) != 0);
105
106 //
107 // Send the character
108 //
109 WRITE_REGISTER_ULONG((PULONG)UART_PL01x_DR, ByteToSend);
110 }
111
112 /* EOF */