2 * PROJECT: ReactOS Kernel
3 * LICENSE: GPL - See COPYING in the top level directory
4 * FILE: ntoskrnl/ke/i386/cpu.c
5 * PURPOSE: Routines for CPU-level support
6 * PROGRAMMERS: Alex Ionescu (alex.ionescu@reactos.org)
9 /* INCLUDES *****************************************************************/
15 /* GLOBALS *******************************************************************/
17 /* The TSS to use for Double Fault Traps (INT 0x9) */
18 UCHAR KiDoubleFaultTSS
[KTSS_IO_MAPS
];
20 /* The TSS to use for NMI Fault Traps (INT 0x2) */
21 UCHAR KiNMITSS
[KTSS_IO_MAPS
];
23 /* CPU Features and Flags */
26 ULONG KeProcessorArchitecture
;
27 ULONG KeProcessorLevel
;
28 ULONG KeProcessorRevision
;
30 ULONG KiFastSystemCallDisable
;
31 ULONG KeI386NpxPresent
= 0;
32 ULONG KiMXCsrMask
= 0;
33 ULONG MxcsrFeatureMask
= 0;
34 ULONG KeI386XMMIPresent
= 0;
35 ULONG KeI386FxsrPresent
= 0;
36 ULONG KeI386MachineType
;
37 ULONG Ke386Pae
= FALSE
;
38 ULONG Ke386NoExecute
= FALSE
;
39 ULONG KeLargestCacheLine
= 0x40;
40 ULONG KeDcacheFlushCount
= 0;
41 ULONG KeIcacheFlushCount
= 0;
42 ULONG KiDmaIoCoherency
= 0;
43 ULONG KePrefetchNTAGranularity
= 32;
44 CHAR KeNumberProcessors
;
45 KAFFINITY KeActiveProcessors
= 1;
46 BOOLEAN KiI386PentiumLockErrataPresent
;
47 BOOLEAN KiSMTProcessorsPresent
;
49 /* The distance between SYSEXIT and IRETD return modes */
50 UCHAR KiSystemCallExitAdjust
;
52 /* The offset that was applied -- either 0 or the value above */
53 UCHAR KiSystemCallExitAdjusted
;
55 /* Whether the adjustment was already done once */
56 BOOLEAN KiFastCallCopyDoneOnce
;
59 volatile LONG KiTbFlushTimeStamp
;
62 static const CHAR CmpIntelID
[] = "GenuineIntel";
63 static const CHAR CmpAmdID
[] = "AuthenticAMD";
64 static const CHAR CmpCyrixID
[] = "CyrixInstead";
65 static const CHAR CmpTransmetaID
[] = "GenuineTMx86";
66 static const CHAR CmpCentaurID
[] = "CentaurHauls";
67 static const CHAR CmpRiseID
[] = "RiseRiseRise";
69 /* SUPPORT ROUTINES FOR MSVC COMPATIBILITY ***********************************/
73 CPUID(IN ULONG InfoType
,
74 OUT PULONG CpuInfoEax
,
75 OUT PULONG CpuInfoEbx
,
76 OUT PULONG CpuInfoEcx
,
77 OUT PULONG CpuInfoEdx
)
81 /* Perform the CPUID Operation */
82 __cpuid((int*)CpuInfo
, InfoType
);
84 /* Return the results */
85 *CpuInfoEax
= CpuInfo
[0];
86 *CpuInfoEbx
= CpuInfo
[1];
87 *CpuInfoEcx
= CpuInfo
[2];
88 *CpuInfoEdx
= CpuInfo
[3];
93 WRMSR(IN ULONG Register
,
96 /* Write to the MSR */
97 __writemsr(Register
, Value
);
102 RDMSR(IN ULONG Register
)
104 /* Read from the MSR */
105 return __readmsr(Register
);
108 /* NSC/Cyrix CPU configuration register index */
109 #define CX86_CCR1 0xc1
111 /* NSC/Cyrix CPU indexed register access macros */
116 WRITE_PORT_UCHAR((PUCHAR
)(ULONG_PTR
)0x22, reg
);
117 return READ_PORT_UCHAR((PUCHAR
)(ULONG_PTR
)0x23);
120 #define setCx86(reg, data) do { \
121 WRITE_PORT_UCHAR((PUCHAR)(ULONG_PTR)0x22,(reg)); \
122 WRITE_PORT_UCHAR((PUCHAR)(ULONG_PTR)0x23,(data)); \
125 /* FUNCTIONS *****************************************************************/
130 KiSetProcessorType(VOID
)
132 ULONG EFlags
, NewEFlags
;
134 ULONG Stepping
, Type
;
136 /* Start by assuming no CPUID data */
137 KeGetCurrentPrcb()->CpuID
= 0;
140 EFlags
= __readeflags();
142 /* XOR out the ID bit and update EFlags */
143 NewEFlags
= EFlags
^ EFLAGS_ID
;
144 __writeeflags(NewEFlags
);
146 /* Get them back and see if they were modified */
147 NewEFlags
= __readeflags();
148 if (NewEFlags
!= EFlags
)
150 /* The modification worked, so CPUID exists. Set the ID Bit again. */
152 __writeeflags(EFlags
);
154 /* Peform CPUID 0 to see if CPUID 1 is supported */
155 CPUID(0, &Reg
, &Dummy
, &Dummy
, &Dummy
);
159 CPUID(1, &Reg
, &Dummy
, &Dummy
, &Dummy
);
162 * Get the Stepping and Type. The stepping contains both the
163 * Model and the Step, while the Type contains the returned Type.
164 * We ignore the family.
166 * For the stepping, we convert this: zzzzzzxy into this: x0y
168 Stepping
= Reg
& 0xF0;
170 Stepping
+= (Reg
& 0xFF);
175 /* Save them in the PRCB */
176 KeGetCurrentPrcb()->CpuID
= TRUE
;
177 KeGetCurrentPrcb()->CpuType
= (UCHAR
)Type
;
178 KeGetCurrentPrcb()->CpuStep
= (USHORT
)Stepping
;
182 DPRINT1("CPUID Support lacking\n");
187 DPRINT1("CPUID Support lacking\n");
191 __writeeflags(EFlags
);
199 PKPRCB Prcb
= KeGetCurrentPrcb();
203 /* Assume no Vendor ID and fail if no CPUID Support. */
204 Prcb
->VendorString
[0] = 0;
205 if (!Prcb
->CpuID
) return 0;
207 /* Get the Vendor ID and null-terminate it */
208 CPUID(0, &Vendor
[0], &Vendor
[1], &Vendor
[2], &Vendor
[3]);
211 /* Re-arrange vendor string */
213 Vendor
[2] = Vendor
[3];
216 /* Copy it to the PRCB and null-terminate it again */
217 RtlCopyMemory(Prcb
->VendorString
,
219 sizeof(Prcb
->VendorString
) - sizeof(CHAR
));
220 Prcb
->VendorString
[sizeof(Prcb
->VendorString
) - sizeof(CHAR
)] = ANSI_NULL
;
222 /* Now check the CPU Type */
223 if (!strcmp(Prcb
->VendorString
, CmpIntelID
))
227 else if (!strcmp(Prcb
->VendorString
, CmpAmdID
))
231 else if (!strcmp(Prcb
->VendorString
, CmpCyrixID
))
233 DPRINT1("Cyrix CPU support not fully tested!\n");
236 else if (!strcmp(Prcb
->VendorString
, CmpTransmetaID
))
238 DPRINT1("Transmeta CPU support not fully tested!\n");
239 return CPU_TRANSMETA
;
241 else if (!strcmp(Prcb
->VendorString
, CmpCentaurID
))
243 DPRINT1("Centaur CPU support not fully tested!\n");
246 else if (!strcmp(Prcb
->VendorString
, CmpRiseID
))
248 DPRINT1("Rise CPU support not fully tested!\n");
259 KiGetFeatureBits(VOID
)
261 PKPRCB Prcb
= KeGetCurrentPrcb();
263 ULONG FeatureBits
= KF_WORKING_PTE
;
264 ULONG Reg
[4], Dummy
, Ccr1
;
265 BOOLEAN ExtendedCPUID
= TRUE
;
266 ULONG CpuFeatures
= 0;
268 /* Get the Vendor ID */
269 Vendor
= KiGetCpuVendor();
271 /* Make sure we got a valid vendor ID at least. */
272 if (!Vendor
) return FeatureBits
;
274 /* Get the CPUID Info. Features are in Reg[3]. */
275 CPUID(1, &Reg
[0], &Reg
[1], &Dummy
, &Reg
[3]);
277 /* Set the initial APIC ID */
278 Prcb
->InitialApicId
= (UCHAR
)(Reg
[1] >> 24);
285 /* Check if it's a P6 */
286 if (Prcb
->CpuType
== 6)
288 /* Perform the special sequence to get the MicroCode Signature */
290 CPUID(1, &Dummy
, &Dummy
, &Dummy
, &Dummy
);
291 Prcb
->UpdateSignature
.QuadPart
= RDMSR(0x8B);
293 else if (Prcb
->CpuType
== 5)
295 /* On P5, enable workaround for the LOCK errata. */
296 KiI386PentiumLockErrataPresent
= TRUE
;
299 /* Check for broken P6 with bad SMP PTE implementation */
300 if (((Reg
[0] & 0x0FF0) == 0x0610 && (Reg
[0] & 0x000F) <= 0x9) ||
301 ((Reg
[0] & 0x0FF0) == 0x0630 && (Reg
[0] & 0x000F) <= 0x4))
303 /* Remove support for correct PTE support. */
304 FeatureBits
&= ~KF_WORKING_PTE
;
307 /* Check if the CPU is too old to support SYSENTER */
308 if ((Prcb
->CpuType
< 6) ||
309 ((Prcb
->CpuType
== 6) && (Prcb
->CpuStep
< 0x0303)))
315 /* Set the current features */
316 CpuFeatures
= Reg
[3];
323 /* Check if this is a K5 or K6. (family 5) */
324 if ((Reg
[0] & 0x0F00) == 0x0500)
326 /* Get the Model Number */
327 switch (Reg
[0] & 0x00F0)
329 /* Model 1: K5 - 5k86 (initial models) */
332 /* Check if this is Step 0 or 1. They don't support PGE */
333 if ((Reg
[0] & 0x000F) > 0x03) break;
335 /* Model 0: K5 - SSA5 */
338 /* Model 0 doesn't support PGE at all. */
345 /* K6-2, Step 8 and over have support for MTRR. */
346 if ((Reg
[0] & 0x000F) >= 0x8) FeatureBits
|= KF_AMDK6MTRR
;
350 Model D: K6-2+, K6-III+ */
354 FeatureBits
|= KF_AMDK6MTRR
;
358 else if((Reg
[0] & 0x0F00) < 0x0500)
360 /* Families below 5 don't support PGE, PSE or CMOV at all */
361 Reg
[3] &= ~(0x08 | 0x2000 | 0x8000);
363 /* They also don't support advanced CPUID functions. */
364 ExtendedCPUID
= FALSE
;
367 /* Set the current features */
368 CpuFeatures
= Reg
[3];
375 /* Workaround the "COMA" bug on 6x family of Cyrix CPUs */
376 if (Prcb
->CpuType
== 6 &&
380 Ccr1
= getCx86(CX86_CCR1
);
382 /* Enable the NO_LOCK bit */
385 /* Set the new CCR1 value */
386 setCx86(CX86_CCR1
, Ccr1
);
389 /* Set the current features */
390 CpuFeatures
= Reg
[3];
397 /* Enable CMPXCHG8B if the family (>= 5), model and stepping (>= 4.2) support it */
398 if ((Reg
[0] & 0x0FFF) >= 0x0542)
400 WRMSR(0x80860004, RDMSR(0x80860004) | 0x0100);
401 FeatureBits
|= KF_CMPXCHG8B
;
406 /* Centaur, IDT, Rise and VIA CPUs */
410 /* These CPUs don't report the presence of CMPXCHG8B through CPUID.
411 However, this feature exists and operates properly without any additional steps. */
412 FeatureBits
|= KF_CMPXCHG8B
;
417 /* Convert all CPUID Feature bits into our format */
418 if (CpuFeatures
& 0x00000002) FeatureBits
|= KF_V86_VIS
| KF_CR4
;
419 if (CpuFeatures
& 0x00000008) FeatureBits
|= KF_LARGE_PAGE
| KF_CR4
;
420 if (CpuFeatures
& 0x00000010) FeatureBits
|= KF_RDTSC
;
421 if (CpuFeatures
& 0x00000100) FeatureBits
|= KF_CMPXCHG8B
;
422 if (CpuFeatures
& 0x00000800) FeatureBits
|= KF_FAST_SYSCALL
;
423 if (CpuFeatures
& 0x00001000) FeatureBits
|= KF_MTRR
;
424 if (CpuFeatures
& 0x00002000) FeatureBits
|= KF_GLOBAL_PAGE
| KF_CR4
;
425 if (CpuFeatures
& 0x00008000) FeatureBits
|= KF_CMOV
;
426 if (CpuFeatures
& 0x00010000) FeatureBits
|= KF_PAT
;
427 if (CpuFeatures
& 0x00200000) FeatureBits
|= KF_DTS
;
428 if (CpuFeatures
& 0x00800000) FeatureBits
|= KF_MMX
;
429 if (CpuFeatures
& 0x01000000) FeatureBits
|= KF_FXSR
;
430 if (CpuFeatures
& 0x02000000) FeatureBits
|= KF_XMMI
;
431 if (CpuFeatures
& 0x04000000) FeatureBits
|= KF_XMMI64
;
433 /* Check if the CPU has hyper-threading */
434 if (CpuFeatures
& 0x10000000)
436 /* Set the number of logical CPUs */
437 Prcb
->LogicalProcessorsPerPhysicalProcessor
= (UCHAR
)(Reg
[1] >> 16);
438 if (Prcb
->LogicalProcessorsPerPhysicalProcessor
> 1)
440 /* We're on dual-core */
441 KiSMTProcessorsPresent
= TRUE
;
446 /* We only have a single CPU */
447 Prcb
->LogicalProcessorsPerPhysicalProcessor
= 1;
450 /* Check if CPUID 0x80000000 is supported */
454 CPUID(0x80000000, &Reg
[0], &Dummy
, &Dummy
, &Dummy
);
455 if ((Reg
[0] & 0xffffff00) == 0x80000000)
457 /* Check if CPUID 0x80000001 is supported */
458 if (Reg
[0] >= 0x80000001)
460 /* Check which extended features are available. */
461 CPUID(0x80000001, &Dummy
, &Dummy
, &Dummy
, &Reg
[3]);
463 /* Check if NX-bit is supported */
464 if (Reg
[3] & 0x00100000) FeatureBits
|= KF_NX_BIT
;
466 /* Now handle each features for each CPU Vendor */
471 if (Reg
[3] & 0x80000000) FeatureBits
|= KF_3DNOW
;
478 #define print_supported(kf_value) ((FeatureBits & kf_value) ? #kf_value : "")
479 DPRINT1("Supported CPU features : %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s\n",
480 print_supported(KF_V86_VIS
),
481 print_supported(KF_RDTSC
),
482 print_supported(KF_CR4
),
483 print_supported(KF_CMOV
),
484 print_supported(KF_GLOBAL_PAGE
),
485 print_supported(KF_LARGE_PAGE
),
486 print_supported(KF_MTRR
),
487 print_supported(KF_CMPXCHG8B
),
488 print_supported(KF_MMX
),
489 print_supported(KF_WORKING_PTE
),
490 print_supported(KF_PAT
),
491 print_supported(KF_FXSR
),
492 print_supported(KF_FAST_SYSCALL
),
493 print_supported(KF_XMMI
),
494 print_supported(KF_3DNOW
),
495 print_supported(KF_AMDK6MTRR
),
496 print_supported(KF_XMMI64
),
497 print_supported(KF_DTS
),
498 print_supported(KF_NX_BIT
),
499 print_supported(KF_NX_DISABLED
),
500 print_supported(KF_NX_ENABLED
));
501 #undef print_supported
503 /* Return the Feature Bits */
510 KiGetCacheInformation(VOID
)
512 PKIPCR Pcr
= (PKIPCR
)KeGetPcr();
514 ULONG Data
[4], Dummy
;
515 ULONG CacheRequests
= 0, i
;
516 ULONG CurrentRegister
;
518 ULONG Size
, Associativity
= 0, CacheLine
= 64, CurrentSize
= 0;
519 BOOLEAN FirstPass
= TRUE
;
521 /* Set default L2 size */
522 Pcr
->SecondLevelCacheSize
= 0;
524 /* Get the Vendor ID and make sure we support CPUID */
525 Vendor
= KiGetCpuVendor();
528 /* Check the Vendor ID */
531 /* Handle Intel case */
534 /*Check if we support CPUID 2 */
535 CPUID(0, &Data
[0], &Dummy
, &Dummy
, &Dummy
);
538 /* We need to loop for the number of times CPUID will tell us to */
541 /* Do the CPUID call */
542 CPUID(2, &Data
[0], &Data
[1], &Data
[2], &Data
[3]);
544 /* Check if it was the first call */
548 * The number of times to loop is the first byte. Read
549 * it and then destroy it so we don't get confused.
551 CacheRequests
= Data
[0] & 0xFF;
552 Data
[0] &= 0xFFFFFF00;
554 /* Don't go over this again */
558 /* Loop all 4 registers */
559 for (i
= 0; i
< 4; i
++)
561 /* Get the current register */
562 CurrentRegister
= Data
[i
];
565 * If the upper bit is set, then this register should
568 if (CurrentRegister
& 0x80000000) continue;
570 /* Keep looping for every byte inside this register */
571 while (CurrentRegister
)
573 /* Read a byte, skip a byte. */
574 RegisterByte
= (UCHAR
)(CurrentRegister
& 0xFF);
575 CurrentRegister
>>= 8;
576 if (!RegisterByte
) continue;
579 * Valid values are from 0x40 (0 bytes) to 0x49
580 * (32MB), or from 0x80 to 0x89 (same size but
583 if (((RegisterByte
> 0x40) && (RegisterByte
<= 0x47)) ||
584 ((RegisterByte
> 0x78) && (RegisterByte
<= 0x7C)) ||
585 ((RegisterByte
> 0x80) && (RegisterByte
<= 0x85)))
587 /* Compute associativity */
589 if (RegisterByte
>= 0x79) Associativity
= 8;
591 /* Mask out only the first nibble */
592 RegisterByte
&= 0x07;
594 /* Check if this cache is bigger than the last */
595 Size
= 0x10000 << RegisterByte
;
596 if ((Size
/ Associativity
) > CurrentSize
)
598 /* Set the L2 Cache Size and Associativity */
599 CurrentSize
= Size
/ Associativity
;
600 Pcr
->SecondLevelCacheSize
= Size
;
601 Pcr
->SecondLevelCacheAssociativity
= Associativity
;
604 else if ((RegisterByte
> 0x21) && (RegisterByte
<= 0x29))
606 /* Set minimum cache line size */
607 if (CacheLine
< 128) CacheLine
= 128;
609 /* Hard-code size/associativity */
611 switch (RegisterByte
)
635 /* Check if this cache is bigger than the last */
636 if ((Size
/ Associativity
) > CurrentSize
)
638 /* Set the L2 Cache Size and Associativity */
639 CurrentSize
= Size
/ Associativity
;
640 Pcr
->SecondLevelCacheSize
= Size
;
641 Pcr
->SecondLevelCacheAssociativity
= Associativity
;
644 else if (((RegisterByte
> 0x65) && (RegisterByte
< 0x69)) ||
645 (RegisterByte
== 0x2C) || (RegisterByte
== 0xF0))
647 /* Indicates L1 cache line of 64 bytes */
648 KePrefetchNTAGranularity
= 64;
650 else if (RegisterByte
== 0xF1)
652 /* Indicates L1 cache line of 128 bytes */
653 KePrefetchNTAGranularity
= 128;
655 else if (((RegisterByte
>= 0x4A) && (RegisterByte
<= 0x4C)) ||
656 (RegisterByte
== 0x78) ||
657 (RegisterByte
== 0x7D) ||
658 (RegisterByte
== 0x7F) ||
659 (RegisterByte
== 0x86) ||
660 (RegisterByte
== 0x87))
662 /* Set minimum cache line size */
663 if (CacheLine
< 64) CacheLine
= 64;
665 /* Hard-code size/associativity */
666 switch (RegisterByte
)
669 Size
= 4 * 1024 * 1024;
674 Size
= 6 * 1024 * 1024;
679 Size
= 8 * 1024 * 1024;
684 Size
= 1 * 1024 * 1024;
689 Size
= 2 * 1024 * 1024;
704 Size
= 1 * 1024 * 1024;
713 /* Check if this cache is bigger than the last */
714 if ((Size
/ Associativity
) > CurrentSize
)
716 /* Set the L2 Cache Size and Associativity */
717 CurrentSize
= Size
/ Associativity
;
718 Pcr
->SecondLevelCacheSize
= Size
;
719 Pcr
->SecondLevelCacheAssociativity
= Associativity
;
724 } while (--CacheRequests
);
730 /* Check if we support CPUID 0x80000005 */
731 CPUID(0x80000000, &Data
[0], &Data
[1], &Data
[2], &Data
[3]);
732 if (Data
[0] >= 0x80000006)
734 /* Get L1 size first */
735 CPUID(0x80000005, &Data
[0], &Data
[1], &Data
[2], &Data
[3]);
736 KePrefetchNTAGranularity
= Data
[2] & 0xFF;
738 /* Check if we support CPUID 0x80000006 */
739 CPUID(0x80000000, &Data
[0], &Data
[1], &Data
[2], &Data
[3]);
740 if (Data
[0] >= 0x80000006)
742 /* Get 2nd level cache and tlb size */
743 CPUID(0x80000006, &Data
[0], &Data
[1], &Data
[2], &Data
[3]);
745 /* Cache line size */
746 CacheLine
= Data
[2] & 0xFF;
748 /* Hardcode associativity */
749 RegisterByte
= Data
[2] >> 12;
750 switch (RegisterByte
)
775 Size
= (Data
[2] >> 16) << 10;
777 /* Hack for Model 6, Steping 300 */
778 if ((KeGetCurrentPrcb()->CpuType
== 6) &&
779 (KeGetCurrentPrcb()->CpuStep
== 0x300))
781 /* Stick 64K in there */
785 /* Set the L2 Cache Size and associativity */
786 Pcr
->SecondLevelCacheSize
= Size
;
787 Pcr
->SecondLevelCacheAssociativity
= Associativity
;
801 /* Set the cache line */
802 if (CacheLine
> KeLargestCacheLine
) KeLargestCacheLine
= CacheLine
;
803 DPRINT1("Prefetch Cache: %d bytes\tL2 Cache: %d bytes\tL2 Cache Line: %d bytes\tL2 Cache Associativity: %d\n",
804 KePrefetchNTAGranularity
,
805 Pcr
->SecondLevelCacheSize
,
807 Pcr
->SecondLevelCacheAssociativity
);
817 /* Save current CR0 */
820 /* If this is a 486, enable Write-Protection */
821 if (KeGetCurrentPrcb()->CpuType
> 3) Cr0
|= CR0_WP
;
830 KiInitializeTSS2(IN PKTSS Tss
,
831 IN PKGDTENTRY TssEntry OPTIONAL
)
835 /* Make sure the GDT Entry is valid */
839 TssEntry
->LimitLow
= sizeof(KTSS
) - 1;
840 TssEntry
->HighWord
.Bits
.LimitHi
= 0;
843 /* Now clear the I/O Map */
844 ASSERT(IOPM_COUNT
== 1);
845 RtlFillMemory(Tss
->IoMaps
[0].IoMap
, IOPM_FULL_SIZE
, 0xFF);
847 /* Initialize Interrupt Direction Maps */
848 p
= (PUCHAR
)(Tss
->IoMaps
[0].DirectionMap
);
849 RtlZeroMemory(p
, IOPM_DIRECTION_MAP_SIZE
);
851 /* Add DPMI support for interrupts */
856 /* Initialize the default Interrupt Direction Map */
857 p
= Tss
->IntDirectionMap
;
858 RtlZeroMemory(Tss
->IntDirectionMap
, IOPM_DIRECTION_MAP_SIZE
);
860 /* Add DPMI support */
868 KiInitializeTSS(IN PKTSS Tss
)
870 /* Set an invalid map base */
871 Tss
->IoMapBase
= KiComputeIopmOffset(IO_ACCESS_MAP_NONE
);
873 /* Disable traps during Task Switches */
876 /* Set LDT and Ring 0 SS */
878 Tss
->Ss0
= KGDT_R0_DATA
;
884 Ki386InitializeTss(IN PKTSS Tss
,
888 PKGDTENTRY TssEntry
, TaskGateEntry
;
890 /* Initialize the boot TSS. */
891 TssEntry
= &Gdt
[KGDT_TSS
/ sizeof(KGDTENTRY
)];
892 TssEntry
->HighWord
.Bits
.Type
= I386_TSS
;
893 TssEntry
->HighWord
.Bits
.Pres
= 1;
894 TssEntry
->HighWord
.Bits
.Dpl
= 0;
895 KiInitializeTSS2(Tss
, TssEntry
);
896 KiInitializeTSS(Tss
);
898 /* Load the task register */
899 Ke386SetTr(KGDT_TSS
);
901 /* Setup the Task Gate for Double Fault Traps */
902 TaskGateEntry
= (PKGDTENTRY
)&Idt
[8];
903 TaskGateEntry
->HighWord
.Bits
.Type
= I386_TASK_GATE
;
904 TaskGateEntry
->HighWord
.Bits
.Pres
= 1;
905 TaskGateEntry
->HighWord
.Bits
.Dpl
= 0;
906 ((PKIDTENTRY
)TaskGateEntry
)->Selector
= KGDT_DF_TSS
;
908 /* Initialize the TSS used for handling double faults. */
909 Tss
= (PKTSS
)KiDoubleFaultTSS
;
910 KiInitializeTSS(Tss
);
911 Tss
->CR3
= __readcr3();
912 Tss
->Esp0
= KiDoubleFaultStack
;
913 Tss
->Esp
= KiDoubleFaultStack
;
914 Tss
->Eip
= PtrToUlong(KiTrap08
);
915 Tss
->Cs
= KGDT_R0_CODE
;
916 Tss
->Fs
= KGDT_R0_PCR
;
917 Tss
->Ss
= Ke386GetSs();
918 Tss
->Es
= KGDT_R3_DATA
| RPL_MASK
;
919 Tss
->Ds
= KGDT_R3_DATA
| RPL_MASK
;
921 /* Setup the Double Trap TSS entry in the GDT */
922 TssEntry
= &Gdt
[KGDT_DF_TSS
/ sizeof(KGDTENTRY
)];
923 TssEntry
->HighWord
.Bits
.Type
= I386_TSS
;
924 TssEntry
->HighWord
.Bits
.Pres
= 1;
925 TssEntry
->HighWord
.Bits
.Dpl
= 0;
926 TssEntry
->BaseLow
= (USHORT
)((ULONG_PTR
)Tss
& 0xFFFF);
927 TssEntry
->HighWord
.Bytes
.BaseMid
= (UCHAR
)((ULONG_PTR
)Tss
>> 16);
928 TssEntry
->HighWord
.Bytes
.BaseHi
= (UCHAR
)((ULONG_PTR
)Tss
>> 24);
929 TssEntry
->LimitLow
= KTSS_IO_MAPS
;
931 /* Now setup the NMI Task Gate */
932 TaskGateEntry
= (PKGDTENTRY
)&Idt
[2];
933 TaskGateEntry
->HighWord
.Bits
.Type
= I386_TASK_GATE
;
934 TaskGateEntry
->HighWord
.Bits
.Pres
= 1;
935 TaskGateEntry
->HighWord
.Bits
.Dpl
= 0;
936 ((PKIDTENTRY
)TaskGateEntry
)->Selector
= KGDT_NMI_TSS
;
938 /* Initialize the actual TSS */
939 Tss
= (PKTSS
)KiNMITSS
;
940 KiInitializeTSS(Tss
);
941 Tss
->CR3
= __readcr3();
942 Tss
->Esp0
= KiDoubleFaultStack
;
943 Tss
->Esp
= KiDoubleFaultStack
;
944 Tss
->Eip
= PtrToUlong(KiTrap02
);
945 Tss
->Cs
= KGDT_R0_CODE
;
946 Tss
->Fs
= KGDT_R0_PCR
;
947 Tss
->Ss
= Ke386GetSs();
948 Tss
->Es
= KGDT_R3_DATA
| RPL_MASK
;
949 Tss
->Ds
= KGDT_R3_DATA
| RPL_MASK
;
951 /* And its associated TSS Entry */
952 TssEntry
= &Gdt
[KGDT_NMI_TSS
/ sizeof(KGDTENTRY
)];
953 TssEntry
->HighWord
.Bits
.Type
= I386_TSS
;
954 TssEntry
->HighWord
.Bits
.Pres
= 1;
955 TssEntry
->HighWord
.Bits
.Dpl
= 0;
956 TssEntry
->BaseLow
= (USHORT
)((ULONG_PTR
)Tss
& 0xFFFF);
957 TssEntry
->HighWord
.Bytes
.BaseMid
= (UCHAR
)((ULONG_PTR
)Tss
>> 16);
958 TssEntry
->HighWord
.Bytes
.BaseHi
= (UCHAR
)((ULONG_PTR
)Tss
>> 24);
959 TssEntry
->LimitLow
= KTSS_IO_MAPS
;
964 KeFlushCurrentTb(VOID
)
966 /* Flush the TLB by resetting CR3 */
967 __writecr3(__readcr3());
972 KiRestoreProcessorControlState(PKPROCESSOR_STATE ProcessorState
)
977 // Restore the CR registers
979 __writecr0(ProcessorState
->SpecialRegisters
.Cr0
);
980 Ke386SetCr2(ProcessorState
->SpecialRegisters
.Cr2
);
981 __writecr3(ProcessorState
->SpecialRegisters
.Cr3
);
982 if (KeFeatureBits
& KF_CR4
) __writecr4(ProcessorState
->SpecialRegisters
.Cr4
);
985 // Restore the DR registers
987 __writedr(0, ProcessorState
->SpecialRegisters
.KernelDr0
);
988 __writedr(1, ProcessorState
->SpecialRegisters
.KernelDr1
);
989 __writedr(2, ProcessorState
->SpecialRegisters
.KernelDr2
);
990 __writedr(3, ProcessorState
->SpecialRegisters
.KernelDr3
);
991 __writedr(6, ProcessorState
->SpecialRegisters
.KernelDr6
);
992 __writedr(7, ProcessorState
->SpecialRegisters
.KernelDr7
);
995 // Restore GDT and IDT
997 Ke386SetGlobalDescriptorTable(&ProcessorState
->SpecialRegisters
.Gdtr
.Limit
);
998 __lidt(&ProcessorState
->SpecialRegisters
.Idtr
.Limit
);
1001 // Clear the busy flag so we don't crash if we reload the same selector
1003 TssEntry
= (PKGDTENTRY
)(ProcessorState
->SpecialRegisters
.Gdtr
.Base
+
1004 ProcessorState
->SpecialRegisters
.Tr
);
1005 TssEntry
->HighWord
.Bytes
.Flags1
&= ~0x2;
1008 // Restore TSS and LDT
1010 Ke386SetTr(ProcessorState
->SpecialRegisters
.Tr
);
1011 Ke386SetLocalDescriptorTable(ProcessorState
->SpecialRegisters
.Ldtr
);
1016 KiSaveProcessorControlState(OUT PKPROCESSOR_STATE ProcessorState
)
1018 /* Save the CR registers */
1019 ProcessorState
->SpecialRegisters
.Cr0
= __readcr0();
1020 ProcessorState
->SpecialRegisters
.Cr2
= __readcr2();
1021 ProcessorState
->SpecialRegisters
.Cr3
= __readcr3();
1022 ProcessorState
->SpecialRegisters
.Cr4
= (KeFeatureBits
& KF_CR4
) ?
1025 /* Save the DR registers */
1026 ProcessorState
->SpecialRegisters
.KernelDr0
= __readdr(0);
1027 ProcessorState
->SpecialRegisters
.KernelDr1
= __readdr(1);
1028 ProcessorState
->SpecialRegisters
.KernelDr2
= __readdr(2);
1029 ProcessorState
->SpecialRegisters
.KernelDr3
= __readdr(3);
1030 ProcessorState
->SpecialRegisters
.KernelDr6
= __readdr(6);
1031 ProcessorState
->SpecialRegisters
.KernelDr7
= __readdr(7);
1034 /* Save GDT, IDT, LDT and TSS */
1035 Ke386GetGlobalDescriptorTable(&ProcessorState
->SpecialRegisters
.Gdtr
.Limit
);
1036 __sidt(&ProcessorState
->SpecialRegisters
.Idtr
.Limit
);
1037 ProcessorState
->SpecialRegisters
.Tr
= Ke386GetTr();
1038 ProcessorState
->SpecialRegisters
.Ldtr
= Ke386GetLocalDescriptorTable();
1044 KiInitializeMachineType(VOID
)
1046 /* Set the Machine Type we got from NTLDR */
1047 KeI386MachineType
= KeLoaderBlock
->u
.I386
.MachineType
& 0x000FF;
1053 KiLoadFastSyscallMachineSpecificRegisters(IN ULONG_PTR Context
)
1055 /* Set CS and ESP */
1056 WRMSR(0x174, KGDT_R0_CODE
);
1057 WRMSR(0x175, (ULONG_PTR
)KeGetCurrentPrcb()->DpcStack
);
1060 WRMSR(0x176, (ULONG_PTR
)KiFastCallEntry
);
1067 KiRestoreFastSyscallReturnState(VOID
)
1069 /* Check if the CPU Supports fast system call */
1070 if (KeFeatureBits
& KF_FAST_SYSCALL
)
1072 /* Check if it has been disabled */
1073 if (!KiFastSystemCallDisable
)
1075 /* Do an IPI to enable it */
1076 KeIpiGenericCall(KiLoadFastSyscallMachineSpecificRegisters
, 0);
1078 /* It's enabled, so use the proper exit stub */
1079 KiFastCallExitHandler
= KiSystemCallSysExitReturn
;
1080 DPRINT1("Support for SYSENTER detected.\n");
1084 /* Disable fast system call */
1085 KeFeatureBits
&= ~KF_FAST_SYSCALL
;
1086 KiFastCallExitHandler
= KiSystemCallTrapReturn
;
1087 DPRINT1("Support for SYSENTER disabled.\n");
1092 /* Use the IRET handler */
1093 KiFastCallExitHandler
= KiSystemCallTrapReturn
;
1094 DPRINT1("No support for SYSENTER detected.\n");
1101 Ki386EnableDE(IN ULONG_PTR Context
)
1104 __writecr4(__readcr4() | CR4_DE
);
1111 Ki386EnableFxsr(IN ULONG_PTR Context
)
1114 __writecr4(__readcr4() | CR4_FXSR
);
1121 Ki386EnableXMMIExceptions(IN ULONG_PTR Context
)
1123 PKIDTENTRY IdtEntry
;
1125 /* Get the IDT Entry for Interrupt 0x13 */
1126 IdtEntry
= &((PKIPCR
)KeGetPcr())->IDT
[0x13];
1129 IdtEntry
->Selector
= KGDT_R0_CODE
;
1130 IdtEntry
->Offset
= ((ULONG_PTR
)KiTrap13
& 0xFFFF);
1131 IdtEntry
->ExtendedOffset
= ((ULONG_PTR
)KiTrap13
>> 16) & 0xFFFF;
1132 ((PKIDT_ACCESS
)&IdtEntry
->Access
)->Dpl
= 0;
1133 ((PKIDT_ACCESS
)&IdtEntry
->Access
)->Present
= 1;
1134 ((PKIDT_ACCESS
)&IdtEntry
->Access
)->SegmentType
= I386_INTERRUPT_GATE
;
1136 /* Enable XMMI exceptions */
1137 __writecr4(__readcr4() | CR4_XMMEXCPT
);
1144 KiI386PentiumLockErrataFixup(VOID
)
1146 KDESCRIPTOR IdtDescriptor
;
1147 PKIDTENTRY NewIdt
, NewIdt2
;
1149 /* Allocate memory for a new IDT */
1150 NewIdt
= ExAllocatePool(NonPagedPool
, 2 * PAGE_SIZE
);
1152 /* Put everything after the first 7 entries on a new page */
1153 NewIdt2
= (PVOID
)((ULONG_PTR
)NewIdt
+ PAGE_SIZE
- (7 * sizeof(KIDTENTRY
)));
1155 /* Disable interrupts */
1158 /* Get the current IDT and copy it */
1159 __sidt(&IdtDescriptor
.Limit
);
1160 RtlCopyMemory(NewIdt2
,
1161 (PVOID
)IdtDescriptor
.Base
,
1162 IdtDescriptor
.Limit
+ 1);
1163 IdtDescriptor
.Base
= (ULONG
)NewIdt2
;
1165 /* Set the new IDT */
1166 __lidt(&IdtDescriptor
.Limit
);
1167 ((PKIPCR
)KeGetPcr())->IDT
= NewIdt2
;
1169 /* Restore interrupts */
1172 /* Set the first 7 entries as read-only to produce a fault */
1173 MmSetPageProtect(NULL
, NewIdt
, PAGE_READONLY
);
1178 KeDisableInterrupts(VOID
)
1183 /* Get EFLAGS and check if the interrupt bit is set */
1184 Flags
= __readeflags();
1185 Return
= (Flags
& EFLAGS_INTERRUPT_MASK
) ? TRUE
: FALSE
;
1187 /* Disable interrupts */
1194 KeInvalidateAllCaches(VOID
)
1196 /* Only supported on Pentium Pro and higher */
1197 if (KeI386CpuType
< 6) return FALSE
;
1199 /* Invalidate all caches */
1206 KeZeroPages(IN PVOID Address
,
1209 /* Not using XMMI in this routine */
1210 RtlZeroMemory(Address
, Size
);
1215 KiSaveProcessorState(IN PKTRAP_FRAME TrapFrame
,
1216 IN PKEXCEPTION_FRAME ExceptionFrame
)
1218 PKPRCB Prcb
= KeGetCurrentPrcb();
1221 // Save full context
1223 Prcb
->ProcessorState
.ContextFrame
.ContextFlags
= CONTEXT_FULL
|
1224 CONTEXT_DEBUG_REGISTERS
;
1225 KeTrapFrameToContext(TrapFrame
, NULL
, &Prcb
->ProcessorState
.ContextFrame
);
1228 // Save control registers
1230 KiSaveProcessorControlState(&Prcb
->ProcessorState
);
1236 KiIsNpxPresent(VOID
)
1244 /* Read CR0 and mask out FPU flags */
1245 Cr0
= __readcr0() & ~(CR0_MP
| CR0_TS
| CR0_EM
| CR0_ET
);
1247 /* Store on FPU stack */
1252 asm volatile ("fninit;" "fnstsw %0" : "+m"(Magic
));
1255 /* Magic should now be cleared */
1258 /* You don't have an FPU -- enable emulation for now */
1259 __writecr0(Cr0
| CR0_EM
| CR0_TS
);
1263 /* You have an FPU, enable it */
1266 /* Enable INT 16 on 486 and higher */
1267 if (KeGetCurrentPrcb()->CpuType
>= 3) Cr0
|= CR0_NE
;
1270 __writecr0(Cr0
| CR0_EM
| CR0_TS
);
1277 KiIsNpxErrataPresent(VOID
)
1279 BOOLEAN ErrataPresent
;
1281 volatile double Value1
, Value2
;
1283 /* Disable interrupts */
1286 /* Read CR0 and remove FPU flags */
1288 __writecr0(Cr0
& ~(CR0_MP
| CR0_TS
| CR0_EM
));
1290 /* Initialize FPU state */
1293 /* Multiply the magic values and divide, we should get the result back */
1296 ErrataPresent
= (Value1
* Value2
/ 3145727.0) != 4195835.0;
1301 /* Enable interrupts */
1304 /* Return if there's an errata */
1305 return ErrataPresent
;
1310 KiFlushNPXState(IN PFLOATING_SAVE_AREA SaveArea
)
1313 PKTHREAD Thread
, NpxThread
;
1314 PFX_SAVE_AREA FxSaveArea
;
1316 /* Save volatiles and disable interrupts */
1317 EFlags
= __readeflags();
1320 /* Save the PCR and get the current thread */
1321 Thread
= KeGetCurrentThread();
1323 /* Check if we're already loaded */
1324 if (Thread
->NpxState
!= NPX_STATE_LOADED
)
1326 /* If there's nothing to load, quit */
1327 if (!SaveArea
) return;
1329 /* Need FXSR support for this */
1330 ASSERT(KeI386FxsrPresent
== TRUE
);
1332 /* Check for sane CR0 */
1334 if (Cr0
& (CR0_MP
| CR0_TS
| CR0_EM
))
1336 /* Mask out FPU flags */
1337 __writecr0(Cr0
& ~(CR0_MP
| CR0_TS
| CR0_EM
));
1340 /* Get the NPX thread and check its FPU state */
1341 NpxThread
= KeGetCurrentPrcb()->NpxThread
;
1342 if ((NpxThread
) && (NpxThread
->NpxState
== NPX_STATE_LOADED
))
1344 /* Get the FX frame and store the state there */
1345 FxSaveArea
= KiGetThreadNpxArea(NpxThread
);
1346 Ke386FxSave(FxSaveArea
);
1348 /* NPX thread has lost its state */
1349 NpxThread
->NpxState
= NPX_STATE_NOT_LOADED
;
1352 /* Now load NPX state from the NPX area */
1353 FxSaveArea
= KiGetThreadNpxArea(Thread
);
1354 Ke386FxStore(FxSaveArea
);
1358 /* Check for sane CR0 */
1360 if (Cr0
& (CR0_MP
| CR0_TS
| CR0_EM
))
1362 /* Mask out FPU flags */
1363 __writecr0(Cr0
& ~(CR0_MP
| CR0_TS
| CR0_EM
));
1367 FxSaveArea
= KiGetThreadNpxArea(Thread
);
1368 Thread
->NpxState
= NPX_STATE_NOT_LOADED
;
1370 /* Save state if supported by CPU */
1371 if (KeI386FxsrPresent
) Ke386FxSave(FxSaveArea
);
1374 /* Now save the FN state wherever it was requested */
1375 if (SaveArea
) Ke386FnSave(SaveArea
);
1377 /* Clear NPX thread */
1378 KeGetCurrentPrcb()->NpxThread
= NULL
;
1380 /* Add the CR0 from the NPX frame */
1381 Cr0
|= NPX_STATE_NOT_LOADED
;
1382 Cr0
|= FxSaveArea
->Cr0NpxState
;
1385 /* Restore interrupt state */
1386 __writeeflags(EFlags
);
1389 /* PUBLIC FUNCTIONS **********************************************************/
1396 KiCoprocessorError(VOID
)
1398 PFX_SAVE_AREA NpxArea
;
1400 /* Get the FPU area */
1401 NpxArea
= KiGetThreadNpxArea(KeGetCurrentThread());
1404 NpxArea
->Cr0NpxState
= CR0_TS
;
1405 __writecr0(__readcr0() | CR0_TS
);
1413 KeSaveFloatingPointState(OUT PKFLOATING_SAVE Save
)
1415 PFNSAVE_FORMAT FpState
;
1416 ASSERT(KeGetCurrentIrql() <= DISPATCH_LEVEL
);
1417 DPRINT1("%s is not really implemented\n", __FUNCTION__
);
1419 /* check if we are doing software emulation */
1420 if (!KeI386NpxPresent
) return STATUS_ILLEGAL_FLOAT_CONTEXT
;
1422 FpState
= ExAllocatePool(NonPagedPool
, sizeof (FNSAVE_FORMAT
));
1423 if (!FpState
) return STATUS_INSUFFICIENT_RESOURCES
;
1425 *((PVOID
*) Save
) = FpState
;
1427 asm volatile("fnsave %0\n\t" : "=m" (*FpState
));
1435 KeGetCurrentThread()->DispatcherHeader
.NpxIrql
= KeGetCurrentIrql();
1436 return STATUS_SUCCESS
;
1444 KeRestoreFloatingPointState(IN PKFLOATING_SAVE Save
)
1446 PFNSAVE_FORMAT FpState
= *((PVOID
*) Save
);
1447 ASSERT(KeGetCurrentThread()->DispatcherHeader
.NpxIrql
== KeGetCurrentIrql());
1448 DPRINT1("%s is not really implemented\n", __FUNCTION__
);
1451 asm volatile("fnclex\n\t");
1452 asm volatile("frstor %0\n\t" : "=m" (*FpState
));
1461 ExFreePool(FpState
);
1462 return STATUS_SUCCESS
;
1470 KeGetRecommendedSharedDataAlignment(VOID
)
1472 /* Return the global variable */
1473 return KeLargestCacheLine
;
1478 KiFlushTargetEntireTb(IN PKIPI_CONTEXT PacketContext
,
1483 /* Signal this packet as done */
1484 KiIpiSignalPacketDone(PacketContext
);
1486 /* Flush the TB for the Current CPU */
1495 KeFlushEntireTb(IN BOOLEAN Invalid
,
1496 IN BOOLEAN AllProcessors
)
1500 KAFFINITY TargetAffinity
;
1501 PKPRCB Prcb
= KeGetCurrentPrcb();
1504 /* Raise the IRQL for the TB Flush */
1505 OldIrql
= KeRaiseIrqlToSynchLevel();
1508 /* FIXME: Use KiTbFlushTimeStamp to synchronize TB flush */
1510 /* Get the current processor affinity, and exclude ourselves */
1511 TargetAffinity
= KeActiveProcessors
;
1512 TargetAffinity
&= ~Prcb
->SetMember
;
1514 /* Make sure this is MP */
1517 /* Send an IPI TB flush to the other processors */
1518 KiIpiSendPacket(TargetAffinity
,
1519 KiFlushTargetEntireTb
,
1526 /* Flush the TB for the Current CPU, and update the flush stamp */
1530 /* If this is MP, wait for the other processors to finish */
1534 ASSERT(Prcb
== (volatile PKPRCB
)KeGetCurrentPrcb());
1537 ASSERTMSG("Not yet implemented\n", FALSE
);
1541 /* Update the flush stamp and return to original IRQL */
1542 InterlockedExchangeAdd(&KiTbFlushTimeStamp
, 1);
1543 KeLowerIrql(OldIrql
);
1551 KeSetDmaIoCoherency(IN ULONG Coherency
)
1553 /* Save the coherency globally */
1554 KiDmaIoCoherency
= Coherency
;
1562 KeQueryActiveProcessors(VOID
)
1566 /* Simply return the number of active processors */
1567 return KeActiveProcessors
;
1575 KeSaveStateForHibernate(IN PKPROCESSOR_STATE State
)
1577 /* Capture the context */
1578 RtlCaptureContext(&State
->ContextFrame
);
1580 /* Capture the control state */
1581 KiSaveProcessorControlState(State
);