ntoskrnl/mm/ARM3/miarm.h

   1 /*
   2  * PROJECT:         ReactOS Kernel
   3  * LICENSE:         BSD - See COPYING.ARM in the top level directory
   4  * FILE:            ntoskrnl/mm/ARM3/miarm.h
   5  * PURPOSE:         ARM Memory Manager Header
   6  * PROGRAMMERS:     ReactOS Portable Systems Group
   7  */
   8
   9 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT)
  10 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING         ((19*1024*1024) >> PAGE_SHIFT)
  11 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST          ((32*1024*1024) >> PAGE_SHIFT)
  12 #define MI_MAX_INIT_NONPAGED_POOL_SIZE         (128 * 1024 * 1024)
  13 #define MI_MAX_NONPAGED_POOL_SIZE              (128 * 1024 * 1024)
  14 #define MI_MAX_FREE_PAGE_LISTS                 4
  15
  16 #define MI_MIN_INIT_PAGED_POOLSIZE             (32 * 1024 * 1024)
  17
  18 #define MI_SESSION_VIEW_SIZE                   (20 * 1024 * 1024)
  19 #define MI_SESSION_POOL_SIZE                   (16 * 1024 * 1024)
  20 #define MI_SESSION_IMAGE_SIZE                  (8 * 1024 * 1024)
  21 #define MI_SESSION_WORKING_SET_SIZE            (4 * 1024 * 1024)
  22 #define MI_SESSION_SIZE                        (MI_SESSION_VIEW_SIZE + \
  23                                                 MI_SESSION_POOL_SIZE + \
  24                                                 MI_SESSION_IMAGE_SIZE + \
  25                                                 MI_SESSION_WORKING_SET_SIZE)
  26
  27 #define MI_SYSTEM_VIEW_SIZE                    (16 * 1024 * 1024)
  28
  29 #define MI_SYSTEM_CACHE_WS_START               (PVOID)0xC0C00000
  30 #define MI_PAGED_POOL_START                    (PVOID)0xE1000000
  31 #define MI_NONPAGED_POOL_END                   (PVOID)0xFFBE0000
  32 #define MI_DEBUG_MAPPING                       (PVOID)0xFFBFF000
  33
  34 #define MI_MIN_SECONDARY_COLORS                 8
  35 #define MI_SECONDARY_COLORS                     64
  36 #define MI_MAX_SECONDARY_COLORS                 1024
  37
  38 #define MM_HIGHEST_VAD_ADDRESS \
  39     (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
  40
  41 /* Make the code cleaner with some definitions for size multiples */
  42 #define _1KB (1024)
  43 #define _1MB (1024 * _1KB)
  44
  45 /* Area mapped by a PDE */
  46 #define PDE_MAPPED_VA  (PTE_COUNT * PAGE_SIZE)
  47
  48 /* Size of a page table */
  49 #define PT_SIZE  (PTE_COUNT * sizeof(MMPTE))
  50
  51 /* Architecture specific count of PDEs in a directory, and count of PTEs in a PT */
  52 #ifdef _M_IX86
  53 #define PD_COUNT  1
  54 #define PDE_COUNT 1024
  55 #define PTE_COUNT 1024
  56 #elif _M_ARM
  57 #define PD_COUNT  1
  58 #define PDE_COUNT 4096
  59 #define PTE_COUNT 256
  60 #else
  61 #error Define these please!
  62 #endif
  63
  64 #ifdef _M_IX86
  65 #define IMAGE_FILE_MACHINE_NATIVE   IMAGE_FILE_MACHINE_I386
  66 #elif _M_ARM
  67 #define IMAGE_FILE_MACHINE_NATIVE   IMAGE_FILE_MACHINE_ARM
  68 #elif _M_AMD64
  69 #define IMAGE_FILE_MACHINE_NATIVE   IMAGE_FILE_MACHINE_AMD64
  70 #else
  71 #error Define these please!
  72 #endif
  73
  74 //
  75 // Protection Bits part of the internal memory manager Protection Mask
  76 // Taken from http://www.reactos.org/wiki/Techwiki:Memory_management_in_the_Windows_XP_kernel
  77 // and public assertions.
  78 //
  79 #define MM_ZERO_ACCESS         0
  80 #define MM_READONLY            1
  81 #define MM_EXECUTE             2
  82 #define MM_EXECUTE_READ        3
  83 #define MM_READWRITE           4
  84 #define MM_WRITECOPY           5
  85 #define MM_EXECUTE_READWRITE   6
  86 #define MM_EXECUTE_WRITECOPY   7
  87 #define MM_NOCACHE             8
  88 #define MM_DECOMMIT            0x10
  89 #define MM_NOACCESS            (MM_DECOMMIT | MM_NOCACHE)
  90
  91 //
  92 // Specific PTE Definitions that map to the Memory Manager's Protection Mask Bits
  93 // The Memory Manager's definition define the attributes that must be preserved
  94 // and these PTE definitions describe the attributes in the hardware sense. This
  95 // helps deal with hardware differences between the actual boolean expression of
  96 // the argument.
  97 //
  98 // For example, in the logical attributes, we want to express read-only as a flag
  99 // but on x86, it is writability that must be set. On the other hand, on x86, just
 100 // like in the kernel, it is disabling the caches that requires a special flag,
 101 // while on certain architectures such as ARM, it is enabling the cache which
 102 // requires a flag.
 103 //
 104 #if defined(_M_IX86) || defined(_M_AMD64)
 105 //
 106 // Access Flags
 107 //
 108 #define PTE_READONLY            0
 109 #define PTE_EXECUTE             0 // Not worrying about NX yet
 110 #define PTE_EXECUTE_READ        0 // Not worrying about NX yet
 111 #define PTE_READWRITE           0x2
 112 #define PTE_WRITECOPY           0x200
 113 #define PTE_EXECUTE_READWRITE   0x0
 114 #define PTE_EXECUTE_WRITECOPY   0x200
 115 //
 116 // Cache flags
 117 //
 118 #define PTE_ENABLE_CACHE        0
 119 #define PTE_DISABLE_CACHE       0x10
 120 #define PTE_WRITECOMBINED_CACHE 0x10
 121 #elif defined(_M_ARM)
 122 #else
 123 #error Define these please!
 124 #endif
 125 static const
 126 ULONG
 127 MmProtectToPteMask[32] =
 128 {
 129     //
 130     // These are the base MM_ protection flags
 131     //
 132     0,
 133     PTE_READONLY            | PTE_ENABLE_CACHE,
 134     PTE_EXECUTE             | PTE_ENABLE_CACHE,
 135     PTE_EXECUTE_READ        | PTE_ENABLE_CACHE,
 136     PTE_READWRITE           | PTE_ENABLE_CACHE,
 137     PTE_WRITECOPY           | PTE_ENABLE_CACHE,
 138     PTE_EXECUTE_READWRITE   | PTE_ENABLE_CACHE,
 139     PTE_EXECUTE_WRITECOPY   | PTE_ENABLE_CACHE,
 140     //
 141     // These OR in the MM_NOCACHE flag
 142     //
 143     0,
 144     PTE_READONLY            | PTE_DISABLE_CACHE,
 145     PTE_EXECUTE             | PTE_DISABLE_CACHE,
 146     PTE_EXECUTE_READ        | PTE_DISABLE_CACHE,
 147     PTE_READWRITE           | PTE_DISABLE_CACHE,
 148     PTE_WRITECOPY           | PTE_DISABLE_CACHE,
 149     PTE_EXECUTE_READWRITE   | PTE_DISABLE_CACHE,
 150     PTE_EXECUTE_WRITECOPY   | PTE_DISABLE_CACHE,
 151     //
 152     // These OR in the MM_DECOMMIT flag, which doesn't seem supported on x86/64/ARM
 153     //
 154     0,
 155     PTE_READONLY            | PTE_ENABLE_CACHE,
 156     PTE_EXECUTE             | PTE_ENABLE_CACHE,
 157     PTE_EXECUTE_READ        | PTE_ENABLE_CACHE,
 158     PTE_READWRITE           | PTE_ENABLE_CACHE,
 159     PTE_WRITECOPY           | PTE_ENABLE_CACHE,
 160     PTE_EXECUTE_READWRITE   | PTE_ENABLE_CACHE,
 161     PTE_EXECUTE_WRITECOPY   | PTE_ENABLE_CACHE,
 162     //
 163     // These OR in the MM_NOACCESS flag, which seems to enable WriteCombining?
 164     //
 165     0,
 166     PTE_READONLY            | PTE_WRITECOMBINED_CACHE,
 167     PTE_EXECUTE             | PTE_WRITECOMBINED_CACHE,
 168     PTE_EXECUTE_READ        | PTE_WRITECOMBINED_CACHE,
 169     PTE_READWRITE           | PTE_WRITECOMBINED_CACHE,
 170     PTE_WRITECOPY           | PTE_WRITECOMBINED_CACHE,
 171     PTE_EXECUTE_READWRITE   | PTE_WRITECOMBINED_CACHE,
 172     PTE_EXECUTE_WRITECOPY   | PTE_WRITECOMBINED_CACHE,
 173 };
 174
 175 //
 176 // Assertions for session images, addresses, and PTEs
 177 //
 178 #define MI_IS_SESSION_IMAGE_ADDRESS(Address) \
 179     (((Address) >= MiSessionImageStart) && ((Address) < MiSessionImageEnd))
 180
 181 #define MI_IS_SESSION_ADDRESS(Address) \
 182     (((Address) >= MmSessionBase) && ((Address) < MiSessionSpaceEnd))
 183
 184 #define MI_IS_SESSION_PTE(Pte) \
 185     ((((PMMPTE)Pte) >= MiSessionBasePte) && (((PMMPTE)Pte) < MiSessionLastPte))
 186
 187 //
 188 // Corresponds to MMPTE_SOFTWARE.Protection
 189 //
 190 #ifdef _M_IX86
 191 #define MM_PTE_SOFTWARE_PROTECTION_BITS   5
 192 #elif _M_ARM
 193 #define MM_PTE_SOFTWARE_PROTECTION_BITS   5
 194 #elif _M_AMD64
 195 #define MM_PTE_SOFTWARE_PROTECTION_BITS   5
 196 #else
 197 #error Define these please!
 198 #endif
 199
 200 //
 201 // Creates a software PTE with the given protection
 202 //
 203 #define MI_MAKE_SOFTWARE_PTE(p, x)          ((p)->u.Long = (x << MM_PTE_SOFTWARE_PROTECTION_BITS))
 204
 205 //
 206 // Marks a PTE as deleted
 207 //
 208 #define MI_SET_PFN_DELETED(x)               ((x)->PteAddress = (PMMPTE)((ULONG_PTR)(x)->PteAddress | 1))
 209 #define MI_IS_PFN_DELETED(x)                ((ULONG_PTR)((x)->PteAddress) & 1)
 210
 211 //
 212 // Special values for LoadedImports
 213 //
 214 #define MM_SYSLDR_NO_IMPORTS   (PVOID)0xFFFFFFFE
 215 #define MM_SYSLDR_BOOT_LOADED  (PVOID)0xFFFFFFFF
 216 #define MM_SYSLDR_SINGLE_ENTRY 0x1
 217
 218 //
 219 // PFN List Sentinel
 220 //
 221 #define LIST_HEAD 0xFFFFFFFF
 222
 223 //
 224 // Special IRQL value (found in assertions)
 225 //
 226 #define MM_NOIRQL (KIRQL)0xFFFFFFFF
 227
 228 //
 229 // FIXFIX: These should go in ex.h after the pool merge
 230 //
 231 #ifdef _M_AMD64
 232 #define POOL_BLOCK_SIZE 16
 233 #else
 234 #define POOL_BLOCK_SIZE  8
 235 #endif
 236 #define POOL_LISTS_PER_PAGE (PAGE_SIZE / POOL_BLOCK_SIZE)
 237 #define BASE_POOL_TYPE_MASK 1
 238 #define POOL_MAX_ALLOC (PAGE_SIZE - (sizeof(POOL_HEADER) + POOL_BLOCK_SIZE))
 239
 240 typedef struct _POOL_DESCRIPTOR
 241 {
 242     POOL_TYPE PoolType;
 243     ULONG PoolIndex;
 244     ULONG RunningAllocs;
 245     ULONG RunningDeAllocs;
 246     ULONG TotalPages;
 247     ULONG TotalBigPages;
 248     ULONG Threshold;
 249     PVOID LockAddress;
 250     PVOID PendingFrees;
 251     LONG PendingFreeDepth;
 252     SIZE_T TotalBytes;
 253     SIZE_T Spare0;
 254     LIST_ENTRY ListHeads[POOL_LISTS_PER_PAGE];
 255 } POOL_DESCRIPTOR, *PPOOL_DESCRIPTOR;
 256
 257 typedef struct _POOL_HEADER
 258 {
 259     union
 260     {
 261         struct
 262         {
 263 #ifdef _M_AMD64
 264             ULONG PreviousSize:8;
 265             ULONG PoolIndex:8;
 266             ULONG BlockSize:8;
 267             ULONG PoolType:8;
 268 #else
 269             USHORT PreviousSize:9;
 270             USHORT PoolIndex:7;
 271             USHORT BlockSize:9;
 272             USHORT PoolType:7;
 273 #endif
 274         };
 275         ULONG Ulong1;
 276     };
 277 #ifdef _M_AMD64
 278     ULONG PoolTag;
 279 #endif
 280     union
 281     {
 282 #ifdef _M_AMD64
 283         PEPROCESS ProcessBilled;
 284 #else
 285         ULONG PoolTag;
 286 #endif
 287         struct
 288         {
 289             USHORT AllocatorBackTraceIndex;
 290             USHORT PoolTagHash;
 291         };
 292     };
 293 } POOL_HEADER, *PPOOL_HEADER;
 294
 295 C_ASSERT(sizeof(POOL_HEADER) == POOL_BLOCK_SIZE);
 296 C_ASSERT(POOL_BLOCK_SIZE == sizeof(LIST_ENTRY));
 297
 298 extern ULONG ExpNumberOfPagedPools;
 299 extern POOL_DESCRIPTOR NonPagedPoolDescriptor;
 300 extern PPOOL_DESCRIPTOR ExpPagedPoolDescriptor[16 + 1];
 301 extern PVOID PoolTrackTable;
 302
 303 //
 304 // END FIXFIX
 305 //
 306
 307 typedef struct _MI_LARGE_PAGE_DRIVER_ENTRY
 308 {
 309     LIST_ENTRY Links;
 310     UNICODE_STRING BaseName;
 311 } MI_LARGE_PAGE_DRIVER_ENTRY, *PMI_LARGE_PAGE_DRIVER_ENTRY;
 312
 313 typedef enum _MMSYSTEM_PTE_POOL_TYPE
 314 {
 315     SystemPteSpace,
 316     NonPagedPoolExpansion,
 317     MaximumPtePoolTypes
 318 } MMSYSTEM_PTE_POOL_TYPE;
 319
 320 typedef enum _MI_PFN_CACHE_ATTRIBUTE
 321 {
 322     MiNonCached,
 323     MiCached,
 324     MiWriteCombined,
 325     MiNotMapped
 326 } MI_PFN_CACHE_ATTRIBUTE, *PMI_PFN_CACHE_ATTRIBUTE;
 327
 328 typedef struct _PHYSICAL_MEMORY_RUN
 329 {
 330     ULONG BasePage;
 331     ULONG PageCount;
 332 } PHYSICAL_MEMORY_RUN, *PPHYSICAL_MEMORY_RUN;
 333
 334 typedef struct _PHYSICAL_MEMORY_DESCRIPTOR
 335 {
 336     ULONG NumberOfRuns;
 337     ULONG NumberOfPages;
 338     PHYSICAL_MEMORY_RUN Run[1];
 339 } PHYSICAL_MEMORY_DESCRIPTOR, *PPHYSICAL_MEMORY_DESCRIPTOR;
 340
 341 typedef struct _MMCOLOR_TABLES
 342 {
 343     PFN_NUMBER Flink;
 344     PVOID Blink;
 345     PFN_NUMBER Count;
 346 } MMCOLOR_TABLES, *PMMCOLOR_TABLES;
 347
 348 typedef struct _MI_LARGE_PAGE_RANGES
 349 {
 350     PFN_NUMBER StartFrame;
 351     PFN_NUMBER LastFrame;
 352 } MI_LARGE_PAGE_RANGES, *PMI_LARGE_PAGE_RANGES;
 353
 354 extern MMPTE HyperTemplatePte;
 355 extern MMPDE ValidKernelPde;
 356 extern MMPTE ValidKernelPte;
 357 extern BOOLEAN MmLargeSystemCache;
 358 extern BOOLEAN MmZeroPageFile;
 359 extern BOOLEAN MmProtectFreedNonPagedPool;
 360 extern BOOLEAN MmTrackLockedPages;
 361 extern BOOLEAN MmTrackPtes;
 362 extern BOOLEAN MmDynamicPfn;
 363 extern BOOLEAN MmMirroring;
 364 extern BOOLEAN MmMakeLowMemory;
 365 extern BOOLEAN MmEnforceWriteProtection;
 366 extern ULONG MmAllocationFragment;
 367 extern ULONG MmConsumedPoolPercentage;
 368 extern ULONG MmVerifyDriverBufferType;
 369 extern ULONG MmVerifyDriverLevel;
 370 extern WCHAR MmVerifyDriverBuffer[512];
 371 extern WCHAR MmLargePageDriverBuffer[512];
 372 extern LIST_ENTRY MiLargePageDriverList;
 373 extern BOOLEAN MiLargePageAllDrivers;
 374 extern ULONG MmVerifyDriverBufferLength;
 375 extern ULONG MmLargePageDriverBufferLength;
 376 extern ULONG MmSizeOfNonPagedPoolInBytes;
 377 extern ULONG MmMaximumNonPagedPoolInBytes;
 378 extern PFN_NUMBER MmMaximumNonPagedPoolInPages;
 379 extern PFN_NUMBER MmSizeOfPagedPoolInPages;
 380 extern PVOID MmNonPagedSystemStart;
 381 extern PVOID MmNonPagedPoolStart;
 382 extern PVOID MmNonPagedPoolExpansionStart;
 383 extern PVOID MmNonPagedPoolEnd;
 384 extern ULONG MmSizeOfPagedPoolInBytes;
 385 extern PVOID MmPagedPoolStart;
 386 extern PVOID MmPagedPoolEnd;
 387 extern PVOID MmSessionBase;
 388 extern ULONG MmSessionSize;
 389 extern PMMPTE MmFirstReservedMappingPte, MmLastReservedMappingPte;
 390 extern PMMPTE MiFirstReservedZeroingPte;
 391 extern MI_PFN_CACHE_ATTRIBUTE MiPlatformCacheAttributes[2][MmMaximumCacheType];
 392 extern PPHYSICAL_MEMORY_DESCRIPTOR MmPhysicalMemoryBlock;
 393 extern ULONG MmBootImageSize;
 394 extern PMMPTE MmSystemPtesStart[MaximumPtePoolTypes];
 395 extern PMMPTE MmSystemPtesEnd[MaximumPtePoolTypes];
 396 extern PMEMORY_ALLOCATION_DESCRIPTOR MxFreeDescriptor;
 397 extern MEMORY_ALLOCATION_DESCRIPTOR MxOldFreeDescriptor;
 398 extern ULONG MxPfnAllocation;
 399 extern MM_PAGED_POOL_INFO MmPagedPoolInfo;
 400 extern RTL_BITMAP MiPfnBitMap;
 401 extern KGUARDED_MUTEX MmPagedPoolMutex;
 402 extern PVOID MmPagedPoolStart;
 403 extern PVOID MmPagedPoolEnd;
 404 extern PVOID MmNonPagedSystemStart;
 405 extern PVOID MiSystemViewStart;
 406 extern ULONG MmSystemViewSize;
 407 extern PVOID MmSessionBase;
 408 extern PVOID MiSessionSpaceEnd;
 409 extern PMMPTE MiSessionImagePteStart;
 410 extern PMMPTE MiSessionImagePteEnd;
 411 extern PMMPTE MiSessionBasePte;
 412 extern PMMPTE MiSessionLastPte;
 413 extern ULONG MmSizeOfPagedPoolInBytes;
 414 extern PMMPTE MmSystemPagePtes;
 415 extern PVOID MmSystemCacheStart;
 416 extern PVOID MmSystemCacheEnd;
 417 extern MMSUPPORT MmSystemCacheWs;
 418 extern SIZE_T MmAllocatedNonPagedPool;
 419 extern ULONG_PTR MmSubsectionBase;
 420 extern ULONG MmSpecialPoolTag;
 421 extern PVOID MmHyperSpaceEnd;
 422 extern PMMWSL MmSystemCacheWorkingSetList;
 423 extern ULONG MmMinimumNonPagedPoolSize;
 424 extern ULONG MmMinAdditionNonPagedPoolPerMb;
 425 extern ULONG MmDefaultMaximumNonPagedPool;
 426 extern ULONG MmMaxAdditionNonPagedPoolPerMb;
 427 extern ULONG MmSecondaryColors;
 428 extern ULONG MmSecondaryColorMask;
 429 extern ULONG MmNumberOfSystemPtes;
 430 extern ULONG MmMaximumNonPagedPoolPercent;
 431 extern ULONG MmLargeStackSize;
 432 extern PMMCOLOR_TABLES MmFreePagesByColor[FreePageList + 1];
 433 extern ULONG MmProductType;
 434 extern MM_SYSTEMSIZE MmSystemSize;
 435 extern PKEVENT MiLowMemoryEvent;
 436 extern PKEVENT MiHighMemoryEvent;
 437 extern PKEVENT MiLowPagedPoolEvent;
 438 extern PKEVENT MiHighPagedPoolEvent;
 439 extern PKEVENT MiLowNonPagedPoolEvent;
 440 extern PKEVENT MiHighNonPagedPoolEvent;
 441 extern PFN_NUMBER MmLowMemoryThreshold;
 442 extern PFN_NUMBER MmHighMemoryThreshold;
 443 extern PFN_NUMBER MiLowPagedPoolThreshold;
 444 extern PFN_NUMBER MiHighPagedPoolThreshold;
 445 extern PFN_NUMBER MiLowNonPagedPoolThreshold;
 446 extern PFN_NUMBER MiHighNonPagedPoolThreshold;
 447 extern PFN_NUMBER MmMinimumFreePages;
 448 extern PFN_NUMBER MmPlentyFreePages;
 449 extern PFN_NUMBER MiExpansionPoolPagesInitialCharge;
 450 extern PFN_NUMBER MmResidentAvailablePages;
 451 extern PFN_NUMBER MmResidentAvailableAtInit;
 452 extern ULONG MmTotalFreeSystemPtes[MaximumPtePoolTypes];
 453 extern PFN_NUMBER MmTotalSystemDriverPages;
 454 extern PVOID MiSessionImageStart;
 455 extern PVOID MiSessionImageEnd;
 456 extern PMMPTE MiHighestUserPte;
 457 extern PMMPDE MiHighestUserPde;
 458 extern PFN_NUMBER MmSystemPageDirectory[PD_COUNT];
 459
 460 #define MI_PFN_TO_PFNENTRY(x)     (&MmPfnDatabase[1][x])
 461 #define MI_PFNENTRY_TO_PFN(x)     (x - MmPfnDatabase[1])
 462
 463 //
 464 // Creates a valid kernel PTE with the given protection
 465 //
 466 FORCEINLINE
 467 VOID
 468 MI_MAKE_HARDWARE_PTE(IN PMMPTE NewPte,
 469                      IN PMMPTE MappingPte,
 470                      IN ULONG ProtectionMask,
 471                      IN PFN_NUMBER PageFrameNumber)
 472 {
 473     /* Only valid for kernel, non-session PTEs */
 474     ASSERT(MappingPte > MiHighestUserPte);
 475     ASSERT(!MI_IS_SESSION_PTE(MappingPte));
 476     ASSERT((MappingPte < (PMMPTE)PDE_BASE) || (MappingPte > (PMMPTE)PDE_TOP));
 477
 478     /* Start fresh */
 479     *NewPte = ValidKernelPte;
 480
 481     /* Set the protection and page */
 482     NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
 483     NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
 484 }
 485
 486 //
 487 // Returns if the page is physically resident (ie: a large page)
 488 // FIXFIX: CISC/x86 only?
 489 //
 490 FORCEINLINE
 491 BOOLEAN
 492 MI_IS_PHYSICAL_ADDRESS(IN PVOID Address)
 493 {
 494     PMMPDE PointerPde;
 495
 496     /* Large pages are never paged out, always physically resident */
 497     PointerPde = MiAddressToPde(Address);
 498     return ((PointerPde->u.Hard.LargePage) && (PointerPde->u.Hard.Valid));
 499 }
 500
 501 //
 502 // Writes a valid PTE
 503 //
 504 VOID
 505 FORCEINLINE
 506 MI_WRITE_VALID_PTE(IN PMMPTE PointerPte,
 507                    IN MMPTE TempPte)
 508 {
 509     /* Write the valid PTE */
 510     ASSERT(PointerPte->u.Hard.Valid == 0);
 511     ASSERT(TempPte.u.Hard.Valid == 1);
 512     *PointerPte = TempPte;
 513 }
 514
 515 //
 516 // Writes an invalid PTE
 517 //
 518 VOID
 519 FORCEINLINE
 520 MI_WRITE_INVALID_PTE(IN PMMPTE PointerPte,
 521                      IN MMPTE InvalidPte)
 522 {
 523     /* Write the invalid PTE */
 524     ASSERT(InvalidPte.u.Hard.Valid == 0);
 525     *PointerPte = InvalidPte;
 526 }
 527
 528 NTSTATUS
 529 NTAPI
 530 MmArmInitSystem(
 531     IN ULONG Phase,
 532     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 533 );
 534
 535 NTSTATUS
 536 NTAPI
 537 MiInitMachineDependent(
 538     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 539 );
 540
 541 VOID
 542 NTAPI
 543 MiComputeColorInformation(
 544     VOID
 545 );
 546
 547 VOID
 548 NTAPI
 549 MiMapPfnDatabase(
 550     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 551 );
 552
 553 VOID
 554 NTAPI
 555 MiInitializeColorTables(
 556     VOID
 557 );
 558
 559 VOID
 560 NTAPI
 561 MiInitializePfnDatabase(
 562     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 563 );
 564
 565 BOOLEAN
 566 NTAPI
 567 MiInitializeMemoryEvents(
 568     VOID
 569 );
 570
 571 PFN_NUMBER
 572 NTAPI
 573 MxGetNextPage(
 574     IN PFN_NUMBER PageCount
 575 );
 576
 577 PPHYSICAL_MEMORY_DESCRIPTOR
 578 NTAPI
 579 MmInitializeMemoryLimits(
 580     IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 581     IN PBOOLEAN IncludeType
 582 );
 583
 584 PFN_NUMBER
 585 NTAPI
 586 MiPagesInLoaderBlock(
 587     IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 588     IN PBOOLEAN IncludeType
 589 );
 590
 591 VOID
 592 FASTCALL
 593 MiSyncARM3WithROS(
 594     IN PVOID AddressStart,
 595     IN PVOID AddressEnd
 596 );
 597
 598 NTSTATUS
 599 NTAPI
 600 MmArmAccessFault(
 601     IN BOOLEAN StoreInstruction,
 602     IN PVOID Address,
 603     IN KPROCESSOR_MODE Mode,
 604     IN PVOID TrapInformation
 605 );
 606
 607 NTSTATUS
 608 FASTCALL
 609 MiCheckPdeForPagedPool(
 610     IN PVOID Address
 611 );
 612
 613 VOID
 614 NTAPI
 615 MiInitializeNonPagedPool(
 616     VOID
 617 );
 618
 619 VOID
 620 NTAPI
 621 MiInitializeNonPagedPoolThresholds(
 622     VOID
 623 );
 624
 625 VOID
 626 NTAPI
 627 MiInitializePoolEvents(
 628     VOID
 629 );
 630
 631 VOID                      //
 632 NTAPI                     //
 633 InitializePool(           //
 634     IN POOL_TYPE PoolType,// FIXFIX: This should go in ex.h after the pool merge
 635     IN ULONG Threshold    //
 636 );                        //
 637
 638 VOID
 639 NTAPI
 640 MiInitializeSystemPtes(
 641     IN PMMPTE StartingPte,
 642     IN ULONG NumberOfPtes,
 643     IN MMSYSTEM_PTE_POOL_TYPE PoolType
 644 );
 645
 646 PMMPTE
 647 NTAPI
 648 MiReserveSystemPtes(
 649     IN ULONG NumberOfPtes,
 650     IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType
 651 );
 652
 653 VOID
 654 NTAPI
 655 MiReleaseSystemPtes(
 656     IN PMMPTE StartingPte,
 657     IN ULONG NumberOfPtes,
 658     IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType
 659 );
 660
 661
 662 PFN_NUMBER
 663 NTAPI
 664 MiFindContiguousPages(
 665     IN PFN_NUMBER LowestPfn,
 666     IN PFN_NUMBER HighestPfn,
 667     IN PFN_NUMBER BoundaryPfn,
 668     IN PFN_NUMBER SizeInPages,
 669     IN MEMORY_CACHING_TYPE CacheType
 670 );
 671
 672 PVOID
 673 NTAPI
 674 MiCheckForContiguousMemory(
 675     IN PVOID BaseAddress,
 676     IN PFN_NUMBER BaseAddressPages,
 677     IN PFN_NUMBER SizeInPages,
 678     IN PFN_NUMBER LowestPfn,
 679     IN PFN_NUMBER HighestPfn,
 680     IN PFN_NUMBER BoundaryPfn,
 681     IN MI_PFN_CACHE_ATTRIBUTE CacheAttribute
 682 );
 683
 684 PMDL
 685 NTAPI
 686 MiAllocatePagesForMdl(
 687     IN PHYSICAL_ADDRESS LowAddress,
 688     IN PHYSICAL_ADDRESS HighAddress,
 689     IN PHYSICAL_ADDRESS SkipBytes,
 690     IN SIZE_T TotalBytes,
 691     IN MI_PFN_CACHE_ATTRIBUTE CacheAttribute,
 692     IN ULONG Flags
 693 );
 694
 695 PVOID
 696 NTAPI
 697 MiMapLockedPagesInUserSpace(
 698     IN PMDL Mdl,
 699     IN PVOID BaseVa,
 700     IN MEMORY_CACHING_TYPE CacheType,
 701     IN PVOID BaseAddress
 702 );
 703
 704 VOID
 705 NTAPI
 706 MiUnmapLockedPagesInUserSpace(
 707     IN PVOID BaseAddress,
 708     IN PMDL Mdl
 709 );
 710
 711 VOID
 712 NTAPI
 713 MiInsertInListTail(
 714     IN PMMPFNLIST ListHead,
 715     IN PMMPFN Entry
 716 );
 717
 718 VOID
 719 NTAPI
 720 MiInsertZeroListAtBack(
 721     IN PFN_NUMBER PageIndex
 722 );
 723
 724 VOID
 725 NTAPI
 726 MiUnlinkFreeOrZeroedPage(
 727     IN PMMPFN Entry
 728 );
 729
 730 PMMPFN
 731 NTAPI
 732 MiRemoveHeadList(
 733     IN PMMPFNLIST ListHead
 734 );
 735
 736 PFN_NUMBER
 737 NTAPI
 738 MiAllocatePfn(
 739     IN PMMPTE PointerPte,
 740     IN ULONG Protection
 741 );
 742
 743 VOID
 744 NTAPI
 745 MiInitializePfn(
 746     IN PFN_NUMBER PageFrameIndex,
 747     IN PMMPTE PointerPte,
 748     IN BOOLEAN Modified
 749 );
 750
 751 VOID
 752 NTAPI
 753 MiInitializePfnForOtherProcess(
 754     IN PFN_NUMBER PageFrameIndex,
 755     IN PMMPTE PointerPte,
 756     IN PFN_NUMBER PteFrame
 757 );
 758
 759 VOID
 760 NTAPI
 761 MiDecrementShareCount(
 762     IN PMMPFN Pfn1,
 763     IN PFN_NUMBER PageFrameIndex
 764 );
 765
 766 PFN_NUMBER
 767 NTAPI
 768 MiRemoveAnyPage(
 769     IN ULONG Color
 770 );
 771
 772 PFN_NUMBER
 773 NTAPI
 774 MiRemoveZeroPage(
 775     IN ULONG Color
 776 );
 777
 778 VOID
 779 NTAPI
 780 MiInsertPageInFreeList(
 781     IN PFN_NUMBER PageFrameIndex
 782 );
 783
 784 PFN_NUMBER
 785 NTAPI
 786 MiDeleteSystemPageableVm(
 787     IN PMMPTE PointerPte,
 788     IN PFN_NUMBER PageCount,
 789     IN ULONG Flags,
 790     OUT PPFN_NUMBER ValidPages
 791 );
 792
 793 PLDR_DATA_TABLE_ENTRY
 794 NTAPI
 795 MiLookupDataTableEntry(
 796     IN PVOID Address
 797 );
 798
 799 VOID
 800 NTAPI
 801 MiInitializeDriverLargePageList(
 802     VOID
 803 );
 804
 805 VOID
 806 NTAPI
 807 MiInitializeLargePageSupport(
 808     VOID
 809 );
 810
 811 VOID
 812 NTAPI
 813 MiSyncCachedRanges(
 814     VOID
 815 );
 816
 817 BOOLEAN
 818 NTAPI
 819 MiIsPfnInUse(
 820     IN PMMPFN Pfn1
 821 );
 822
 823 /* EOF */