ntoskrnl/mm/ARM3/miarm.h

   1 /*
   2  * PROJECT:         ReactOS Kernel
   3  * LICENSE:         BSD - See COPYING.ARM in the top level directory
   4  * FILE:            ntoskrnl/mm/ARM3/miarm.h
   5  * PURPOSE:         ARM Memory Manager Header
   6  * PROGRAMMERS:     ReactOS Portable Systems Group
   7  */
   8
   9 #ifndef _M_AMD64
  10
  11 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING   ((255 * _1MB) >> PAGE_SHIFT)
  12 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING          ((19 * _1MB) >> PAGE_SHIFT)
  13 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST           ((32 * _1MB) >> PAGE_SHIFT)
  14 #define MI_MAX_INIT_NONPAGED_POOL_SIZE          (128 * _1MB)
  15 #define MI_MAX_NONPAGED_POOL_SIZE               (128 * _1MB)
  16 #define MI_MAX_FREE_PAGE_LISTS                  4
  17
  18 #define MI_MIN_INIT_PAGED_POOLSIZE              (32 * _1MB)
  19
  20 #define MI_SESSION_VIEW_SIZE                    (20 * _1MB)
  21 #define MI_SESSION_POOL_SIZE                    (16 * _1MB)
  22 #define MI_SESSION_IMAGE_SIZE                   (8 * _1MB)
  23 #define MI_SESSION_WORKING_SET_SIZE             (4 * _1MB)
  24 #define MI_SESSION_SIZE                         (MI_SESSION_VIEW_SIZE + \
  25                                                  MI_SESSION_POOL_SIZE + \
  26                                                  MI_SESSION_IMAGE_SIZE + \
  27                                                  MI_SESSION_WORKING_SET_SIZE)
  28
  29 #define MI_SYSTEM_VIEW_SIZE                     (16 * _1MB)
  30
  31 #define MI_HIGHEST_USER_ADDRESS                 (PVOID)0x7FFEFFFF
  32 #define MI_USER_PROBE_ADDRESS                   (PVOID)0x7FFF0000
  33 #define MI_DEFAULT_SYSTEM_RANGE_START           (PVOID)0x80000000
  34 #define MI_SYSTEM_CACHE_WS_START                (PVOID)0xC0C00000
  35 #define MI_PAGED_POOL_START                     (PVOID)0xE1000000
  36 #define MI_NONPAGED_POOL_END                    (PVOID)0xFFBE0000
  37 #define MI_DEBUG_MAPPING                        (PVOID)0xFFBFF000
  38
  39 #define MI_SYSTEM_PTE_BASE                      (PVOID)MiAddressToPte(NULL)
  40
  41 #define MI_MIN_SECONDARY_COLORS                 8
  42 #define MI_SECONDARY_COLORS                     64
  43 #define MI_MAX_SECONDARY_COLORS                 1024
  44
  45 #define MI_MIN_ALLOCATION_FRAGMENT              (4 * _1KB)
  46 #define MI_ALLOCATION_FRAGMENT                  (64 * _1KB)
  47 #define MI_MAX_ALLOCATION_FRAGMENT              (2  * _1MB)
  48
  49 #define MM_HIGHEST_VAD_ADDRESS \
  50     (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
  51 #define MI_LOWEST_VAD_ADDRESS                   (PVOID)MM_LOWEST_USER_ADDRESS
  52
  53 #endif /* !_M_AMD64 */
  54
  55 /* Make the code cleaner with some definitions for size multiples */
  56 #define _1KB (1024u)
  57 #define _1MB (1024 * _1KB)
  58 #define _1GB (1024 * _1MB)
  59
  60 /* Everyone loves 64K */
  61 #define _64K (64 * _1KB)
  62
  63 /* Area mapped by a PDE */
  64 #define PDE_MAPPED_VA  (PTE_COUNT * PAGE_SIZE)
  65
  66 /* Size of a page table */
  67 #define PT_SIZE  (PTE_COUNT * sizeof(MMPTE))
  68
  69 /* Size of a page directory */
  70 #define PD_SIZE  (PDE_COUNT * sizeof(MMPDE))
  71
  72 /* Size of all page directories for a process */
  73 #define SYSTEM_PD_SIZE (PD_COUNT * PD_SIZE)
  74
  75 /* Architecture specific count of PDEs in a directory, and count of PTEs in a PT */
  76 #ifdef _M_IX86
  77 #define PD_COUNT  1
  78 #define PDE_COUNT 1024
  79 #define PTE_COUNT 1024
  80 C_ASSERT(SYSTEM_PD_SIZE == PAGE_SIZE);
  81 #elif _M_ARM
  82 #define PD_COUNT  1
  83 #define PDE_COUNT 4096
  84 #define PTE_COUNT 256
  85 #else
  86 #define PD_COUNT  PPE_PER_PAGE
  87 #define PDE_COUNT PDE_PER_PAGE
  88 #define PTE_COUNT PTE_PER_PAGE
  89 #endif
  90
  91 //
  92 // Protection Bits part of the internal memory manager Protection Mask
  93 // Taken from http://www.reactos.org/wiki/Techwiki:Memory_management_in_the_Windows_XP_kernel
  94 // and public assertions.
  95 //
  96 #define MM_ZERO_ACCESS         0
  97 #define MM_READONLY            1
  98 #define MM_EXECUTE             2
  99 #define MM_EXECUTE_READ        3
 100 #define MM_READWRITE           4
 101 #define MM_WRITECOPY           5
 102 #define MM_EXECUTE_READWRITE   6
 103 #define MM_EXECUTE_WRITECOPY   7
 104 #define MM_NOCACHE             8
 105 #define MM_DECOMMIT            0x10
 106 #define MM_NOACCESS            (MM_DECOMMIT | MM_NOCACHE)
 107 #define MM_INVALID_PROTECTION  0xFFFFFFFF
 108
 109 //
 110 // Specific PTE Definitions that map to the Memory Manager's Protection Mask Bits
 111 // The Memory Manager's definition define the attributes that must be preserved
 112 // and these PTE definitions describe the attributes in the hardware sense. This
 113 // helps deal with hardware differences between the actual boolean expression of
 114 // the argument.
 115 //
 116 // For example, in the logical attributes, we want to express read-only as a flag
 117 // but on x86, it is writability that must be set. On the other hand, on x86, just
 118 // like in the kernel, it is disabling the caches that requires a special flag,
 119 // while on certain architectures such as ARM, it is enabling the cache which
 120 // requires a flag.
 121 //
 122 #if defined(_M_IX86) || defined(_M_AMD64)
 123 //
 124 // Access Flags
 125 //
 126 #define PTE_READONLY            0 // Doesn't exist on x86
 127 #define PTE_EXECUTE             0 // Not worrying about NX yet
 128 #define PTE_EXECUTE_READ        0 // Not worrying about NX yet
 129 #define PTE_READWRITE           0x2
 130 #define PTE_WRITECOPY           0x200
 131 #define PTE_EXECUTE_READWRITE   0x2 // Not worrying about NX yet
 132 #define PTE_EXECUTE_WRITECOPY   0x200
 133 #define PTE_PROTOTYPE           0x400
 134
 135 //
 136 // State Flags
 137 //
 138 #define PTE_VALID               0x1
 139 #define PTE_ACCESSED            0x20
 140 #define PTE_DIRTY               0x40
 141
 142 //
 143 // Cache flags
 144 //
 145 #define PTE_ENABLE_CACHE        0
 146 #define PTE_DISABLE_CACHE       0x10
 147 #define PTE_WRITECOMBINED_CACHE 0x10
 148 #elif defined(_M_ARM)
 149 #define PTE_READONLY            0x200
 150 #define PTE_EXECUTE             0 // Not worrying about NX yet
 151 #define PTE_EXECUTE_READ        0 // Not worrying about NX yet
 152 #define PTE_READWRITE           0 // Doesn't exist on ARM
 153 #define PTE_WRITECOPY           0 // Doesn't exist on ARM
 154 #define PTE_EXECUTE_READWRITE   0 // Not worrying about NX yet
 155 #define PTE_EXECUTE_WRITECOPY   0 // Not worrying about NX yet
 156 #define PTE_PROTOTYPE           0x400 // Using the Shared bit
 157 //
 158 // Cache flags
 159 //
 160 #define PTE_ENABLE_CACHE        0
 161 #define PTE_DISABLE_CACHE       0x10
 162 #define PTE_WRITECOMBINED_CACHE 0x10
 163 #else
 164 #error Define these please!
 165 #endif
 166
 167 extern const ULONG MmProtectToPteMask[32];
 168 extern const ULONG MmProtectToValue[32];
 169
 170 //
 171 // Assertions for session images, addresses, and PTEs
 172 //
 173 #define MI_IS_SESSION_IMAGE_ADDRESS(Address) \
 174     (((Address) >= MiSessionImageStart) && ((Address) < MiSessionImageEnd))
 175
 176 #define MI_IS_SESSION_ADDRESS(Address) \
 177     (((Address) >= MmSessionBase) && ((Address) < MiSessionSpaceEnd))
 178
 179 #define MI_IS_SESSION_PTE(Pte) \
 180     ((((PMMPTE)Pte) >= MiSessionBasePte) && (((PMMPTE)Pte) < MiSessionLastPte))
 181
 182 #define MI_IS_PAGE_TABLE_ADDRESS(Address) \
 183     (((PVOID)(Address) >= (PVOID)PTE_BASE) && ((PVOID)(Address) <= (PVOID)PTE_TOP))
 184
 185 #define MI_IS_SYSTEM_PAGE_TABLE_ADDRESS(Address) \
 186     (((Address) >= (PVOID)MiAddressToPte(MmSystemRangeStart)) && ((Address) <= (PVOID)PTE_TOP))
 187
 188 #define MI_IS_PAGE_TABLE_OR_HYPER_ADDRESS(Address) \
 189     (((PVOID)(Address) >= (PVOID)PTE_BASE) && ((PVOID)(Address) <= (PVOID)MmHyperSpaceEnd))
 190
 191 //
 192 // Corresponds to MMPTE_SOFTWARE.Protection
 193 //
 194 #ifdef _M_IX86
 195 #define MM_PTE_SOFTWARE_PROTECTION_BITS   5
 196 #elif _M_ARM
 197 #define MM_PTE_SOFTWARE_PROTECTION_BITS   6
 198 #elif _M_AMD64
 199 #define MM_PTE_SOFTWARE_PROTECTION_BITS   5
 200 #else
 201 #error Define these please!
 202 #endif
 203
 204 //
 205 // Creates a software PTE with the given protection
 206 //
 207 #define MI_MAKE_SOFTWARE_PTE(p, x)          ((p)->u.Long = (x << MM_PTE_SOFTWARE_PROTECTION_BITS))
 208
 209 //
 210 // Marks a PTE as deleted
 211 //
 212 #define MI_SET_PFN_DELETED(x)               ((x)->PteAddress = (PMMPTE)((ULONG_PTR)(x)->PteAddress | 1))
 213 #define MI_IS_PFN_DELETED(x)                ((ULONG_PTR)((x)->PteAddress) & 1)
 214
 215 //
 216 // Special values for LoadedImports
 217 //
 218 #define MM_SYSLDR_NO_IMPORTS   (PVOID)0xFFFFFFFE
 219 #define MM_SYSLDR_BOOT_LOADED  (PVOID)0xFFFFFFFF
 220 #define MM_SYSLDR_SINGLE_ENTRY 0x1
 221
 222 #if defined(_M_IX86) || defined(_M_ARM)
 223 //
 224 // PFN List Sentinel
 225 //
 226 #define LIST_HEAD 0xFFFFFFFF
 227
 228 //
 229 // Because GCC cannot automatically downcast 0xFFFFFFFF to lesser-width bits,
 230 // we need a manual definition suited to the number of bits in the PteFrame.
 231 // This is used as a LIST_HEAD for the colored list
 232 //
 233 #define COLORED_LIST_HEAD ((1 << 25) - 1) // 0x1FFFFFF
 234 #elif defined(_M_AMD64)
 235 #define LIST_HEAD 0xFFFFFFFFFFFFFFFFLL
 236 #define COLORED_LIST_HEAD ((1ULL << 57) - 1) // 0x1FFFFFFFFFFFFFFLL
 237 #else
 238 #error Define these please!
 239 #endif
 240
 241 //
 242 // Special IRQL value (found in assertions)
 243 //
 244 #define MM_NOIRQL (KIRQL)0xFFFFFFFF
 245
 246 //
 247 // Returns the color of a page
 248 //
 249 #define MI_GET_PAGE_COLOR(x)                ((x) & MmSecondaryColorMask)
 250 #define MI_GET_NEXT_COLOR()                 (MI_GET_PAGE_COLOR(++MmSystemPageColor))
 251 #define MI_GET_NEXT_PROCESS_COLOR(x)        (MI_GET_PAGE_COLOR(++(x)->NextPageColor))
 252
 253 #ifndef _M_AMD64
 254 //
 255 // Decodes a Prototype PTE into the underlying PTE
 256 //
 257 #define MiProtoPteToPte(x)                  \
 258     (PMMPTE)((ULONG_PTR)MmPagedPoolStart +  \
 259              (((x)->u.Proto.ProtoAddressHigh << 7) | (x)->u.Proto.ProtoAddressLow))
 260 #endif
 261
 262 //
 263 // Prototype PTEs that don't yet have a pagefile association
 264 //
 265 #define MI_PTE_LOOKUP_NEEDED 0xFFFFF
 266
 267 //
 268 // System views are binned into 64K chunks
 269 //
 270 #define MI_SYSTEM_VIEW_BUCKET_SIZE  _64K
 271
 272 //
 273 // FIXFIX: These should go in ex.h after the pool merge
 274 //
 275 #ifdef _M_AMD64
 276 #define POOL_BLOCK_SIZE 16
 277 #else
 278 #define POOL_BLOCK_SIZE  8
 279 #endif
 280 #define POOL_LISTS_PER_PAGE (PAGE_SIZE / POOL_BLOCK_SIZE)
 281 #define BASE_POOL_TYPE_MASK 1
 282 #define POOL_MAX_ALLOC (PAGE_SIZE - (sizeof(POOL_HEADER) + POOL_BLOCK_SIZE))
 283
 284 typedef struct _POOL_DESCRIPTOR
 285 {
 286     POOL_TYPE PoolType;
 287     ULONG PoolIndex;
 288     ULONG RunningAllocs;
 289     ULONG RunningDeAllocs;
 290     ULONG TotalPages;
 291     ULONG TotalBigPages;
 292     ULONG Threshold;
 293     PVOID LockAddress;
 294     PVOID PendingFrees;
 295     LONG PendingFreeDepth;
 296     SIZE_T TotalBytes;
 297     SIZE_T Spare0;
 298     LIST_ENTRY ListHeads[POOL_LISTS_PER_PAGE];
 299 } POOL_DESCRIPTOR, *PPOOL_DESCRIPTOR;
 300
 301 typedef struct _POOL_HEADER
 302 {
 303     union
 304     {
 305         struct
 306         {
 307 #ifdef _M_AMD64
 308             USHORT PreviousSize:8;
 309             USHORT PoolIndex:8;
 310             USHORT BlockSize:8;
 311             USHORT PoolType:8;
 312 #else
 313             USHORT PreviousSize:9;
 314             USHORT PoolIndex:7;
 315             USHORT BlockSize:9;
 316             USHORT PoolType:7;
 317 #endif
 318         };
 319         ULONG Ulong1;
 320     };
 321 #ifdef _M_AMD64
 322     ULONG PoolTag;
 323 #endif
 324     union
 325     {
 326 #ifdef _M_AMD64
 327         PEPROCESS ProcessBilled;
 328 #else
 329         ULONG PoolTag;
 330 #endif
 331         struct
 332         {
 333             USHORT AllocatorBackTraceIndex;
 334             USHORT PoolTagHash;
 335         };
 336     };
 337 } POOL_HEADER, *PPOOL_HEADER;
 338
 339 C_ASSERT(sizeof(POOL_HEADER) == POOL_BLOCK_SIZE);
 340 C_ASSERT(POOL_BLOCK_SIZE == sizeof(LIST_ENTRY));
 341
 342 extern ULONG ExpNumberOfPagedPools;
 343 extern POOL_DESCRIPTOR NonPagedPoolDescriptor;
 344 extern PPOOL_DESCRIPTOR ExpPagedPoolDescriptor[16 + 1];
 345 extern PVOID PoolTrackTable;
 346
 347 //
 348 // END FIXFIX
 349 //
 350
 351 typedef struct _MI_LARGE_PAGE_DRIVER_ENTRY
 352 {
 353     LIST_ENTRY Links;
 354     UNICODE_STRING BaseName;
 355 } MI_LARGE_PAGE_DRIVER_ENTRY, *PMI_LARGE_PAGE_DRIVER_ENTRY;
 356
 357 typedef enum _MMSYSTEM_PTE_POOL_TYPE
 358 {
 359     SystemPteSpace,
 360     NonPagedPoolExpansion,
 361     MaximumPtePoolTypes
 362 } MMSYSTEM_PTE_POOL_TYPE;
 363
 364 typedef enum _MI_PFN_CACHE_ATTRIBUTE
 365 {
 366     MiNonCached,
 367     MiCached,
 368     MiWriteCombined,
 369     MiNotMapped
 370 } MI_PFN_CACHE_ATTRIBUTE, *PMI_PFN_CACHE_ATTRIBUTE;
 371
 372 typedef struct _PHYSICAL_MEMORY_RUN
 373 {
 374     PFN_NUMBER BasePage;
 375     PFN_NUMBER PageCount;
 376 } PHYSICAL_MEMORY_RUN, *PPHYSICAL_MEMORY_RUN;
 377
 378 typedef struct _PHYSICAL_MEMORY_DESCRIPTOR
 379 {
 380     ULONG NumberOfRuns;
 381     PFN_NUMBER NumberOfPages;
 382     PHYSICAL_MEMORY_RUN Run[1];
 383 } PHYSICAL_MEMORY_DESCRIPTOR, *PPHYSICAL_MEMORY_DESCRIPTOR;
 384
 385 typedef struct _MMCOLOR_TABLES
 386 {
 387     PFN_NUMBER Flink;
 388     PVOID Blink;
 389     PFN_NUMBER Count;
 390 } MMCOLOR_TABLES, *PMMCOLOR_TABLES;
 391
 392 typedef struct _MI_LARGE_PAGE_RANGES
 393 {
 394     PFN_NUMBER StartFrame;
 395     PFN_NUMBER LastFrame;
 396 } MI_LARGE_PAGE_RANGES, *PMI_LARGE_PAGE_RANGES;
 397
 398 typedef struct _MMVIEW
 399 {
 400     ULONG_PTR Entry;
 401     PCONTROL_AREA ControlArea;
 402 } MMVIEW, *PMMVIEW;
 403
 404 typedef struct _MMSESSION
 405 {
 406     KGUARDED_MUTEX SystemSpaceViewLock;
 407     PKGUARDED_MUTEX SystemSpaceViewLockPointer;
 408     PCHAR SystemSpaceViewStart;
 409     PMMVIEW SystemSpaceViewTable;
 410     ULONG SystemSpaceHashSize;
 411     ULONG SystemSpaceHashEntries;
 412     ULONG SystemSpaceHashKey;
 413     ULONG BitmapFailures;
 414     PRTL_BITMAP SystemSpaceBitMap;
 415 } MMSESSION, *PMMSESSION;
 416
 417 extern MMPTE HyperTemplatePte;
 418 extern MMPDE ValidKernelPde;
 419 extern MMPTE ValidKernelPte;
 420 extern MMPDE DemandZeroPde;
 421 extern MMPTE DemandZeroPte;
 422 extern MMPTE PrototypePte;
 423 extern BOOLEAN MmLargeSystemCache;
 424 extern BOOLEAN MmZeroPageFile;
 425 extern BOOLEAN MmProtectFreedNonPagedPool;
 426 extern BOOLEAN MmTrackLockedPages;
 427 extern BOOLEAN MmTrackPtes;
 428 extern BOOLEAN MmDynamicPfn;
 429 extern BOOLEAN MmMirroring;
 430 extern BOOLEAN MmMakeLowMemory;
 431 extern BOOLEAN MmEnforceWriteProtection;
 432 extern SIZE_T MmAllocationFragment;
 433 extern ULONG MmConsumedPoolPercentage;
 434 extern ULONG MmVerifyDriverBufferType;
 435 extern ULONG MmVerifyDriverLevel;
 436 extern WCHAR MmVerifyDriverBuffer[512];
 437 extern WCHAR MmLargePageDriverBuffer[512];
 438 extern LIST_ENTRY MiLargePageDriverList;
 439 extern BOOLEAN MiLargePageAllDrivers;
 440 extern ULONG MmVerifyDriverBufferLength;
 441 extern ULONG MmLargePageDriverBufferLength;
 442 extern SIZE_T MmSizeOfNonPagedPoolInBytes;
 443 extern SIZE_T MmMaximumNonPagedPoolInBytes;
 444 extern PFN_NUMBER MmMaximumNonPagedPoolInPages;
 445 extern PFN_NUMBER MmSizeOfPagedPoolInPages;
 446 extern PVOID MmNonPagedSystemStart;
 447 extern PVOID MmNonPagedPoolStart;
 448 extern PVOID MmNonPagedPoolExpansionStart;
 449 extern PVOID MmNonPagedPoolEnd;
 450 extern SIZE_T MmSizeOfPagedPoolInBytes;
 451 extern PVOID MmPagedPoolStart;
 452 extern PVOID MmPagedPoolEnd;
 453 extern PVOID MmSessionBase;
 454 extern SIZE_T MmSessionSize;
 455 extern PMMPTE MmFirstReservedMappingPte, MmLastReservedMappingPte;
 456 extern PMMPTE MiFirstReservedZeroingPte;
 457 extern MI_PFN_CACHE_ATTRIBUTE MiPlatformCacheAttributes[2][MmMaximumCacheType];
 458 extern PPHYSICAL_MEMORY_DESCRIPTOR MmPhysicalMemoryBlock;
 459 extern SIZE_T MmBootImageSize;
 460 extern PMMPTE MmSystemPtesStart[MaximumPtePoolTypes];
 461 extern PMMPTE MmSystemPtesEnd[MaximumPtePoolTypes];
 462 extern PMEMORY_ALLOCATION_DESCRIPTOR MxFreeDescriptor;
 463 extern MEMORY_ALLOCATION_DESCRIPTOR MxOldFreeDescriptor;
 464 extern ULONG_PTR MxPfnAllocation;
 465 extern MM_PAGED_POOL_INFO MmPagedPoolInfo;
 466 extern RTL_BITMAP MiPfnBitMap;
 467 extern KGUARDED_MUTEX MmPagedPoolMutex;
 468 extern PVOID MmPagedPoolStart;
 469 extern PVOID MmPagedPoolEnd;
 470 extern PVOID MmNonPagedSystemStart;
 471 extern PVOID MiSystemViewStart;
 472 extern SIZE_T MmSystemViewSize;
 473 extern PVOID MmSessionBase;
 474 extern PVOID MiSessionSpaceEnd;
 475 extern PMMPTE MiSessionImagePteStart;
 476 extern PMMPTE MiSessionImagePteEnd;
 477 extern PMMPTE MiSessionBasePte;
 478 extern PMMPTE MiSessionLastPte;
 479 extern SIZE_T MmSizeOfPagedPoolInBytes;
 480 extern PMMPDE MmSystemPagePtes;
 481 extern PVOID MmSystemCacheStart;
 482 extern PVOID MmSystemCacheEnd;
 483 extern MMSUPPORT MmSystemCacheWs;
 484 extern SIZE_T MmAllocatedNonPagedPool;
 485 extern ULONG_PTR MmSubsectionBase;
 486 extern ULONG MmSpecialPoolTag;
 487 extern PVOID MmHyperSpaceEnd;
 488 extern PMMWSL MmSystemCacheWorkingSetList;
 489 extern SIZE_T MmMinimumNonPagedPoolSize;
 490 extern ULONG MmMinAdditionNonPagedPoolPerMb;
 491 extern SIZE_T MmDefaultMaximumNonPagedPool;
 492 extern ULONG MmMaxAdditionNonPagedPoolPerMb;
 493 extern ULONG MmSecondaryColors;
 494 extern ULONG MmSecondaryColorMask;
 495 extern ULONG MmNumberOfSystemPtes;
 496 extern ULONG MmMaximumNonPagedPoolPercent;
 497 extern ULONG MmLargeStackSize;
 498 extern PMMCOLOR_TABLES MmFreePagesByColor[FreePageList + 1];
 499 extern ULONG MmProductType;
 500 extern MM_SYSTEMSIZE MmSystemSize;
 501 extern PKEVENT MiLowMemoryEvent;
 502 extern PKEVENT MiHighMemoryEvent;
 503 extern PKEVENT MiLowPagedPoolEvent;
 504 extern PKEVENT MiHighPagedPoolEvent;
 505 extern PKEVENT MiLowNonPagedPoolEvent;
 506 extern PKEVENT MiHighNonPagedPoolEvent;
 507 extern PFN_NUMBER MmLowMemoryThreshold;
 508 extern PFN_NUMBER MmHighMemoryThreshold;
 509 extern PFN_NUMBER MiLowPagedPoolThreshold;
 510 extern PFN_NUMBER MiHighPagedPoolThreshold;
 511 extern PFN_NUMBER MiLowNonPagedPoolThreshold;
 512 extern PFN_NUMBER MiHighNonPagedPoolThreshold;
 513 extern PFN_NUMBER MmMinimumFreePages;
 514 extern PFN_NUMBER MmPlentyFreePages;
 515 extern PFN_COUNT MiExpansionPoolPagesInitialCharge;
 516 extern PFN_NUMBER MmResidentAvailablePages;
 517 extern PFN_NUMBER MmResidentAvailableAtInit;
 518 extern ULONG MmTotalFreeSystemPtes[MaximumPtePoolTypes];
 519 extern PFN_NUMBER MmTotalSystemDriverPages;
 520 extern PVOID MiSessionImageStart;
 521 extern PVOID MiSessionImageEnd;
 522 extern PMMPTE MiHighestUserPte;
 523 extern PMMPDE MiHighestUserPde;
 524 extern PFN_NUMBER MmSystemPageDirectory[PD_COUNT];
 525 extern PMMPTE MmSharedUserDataPte;
 526 extern LIST_ENTRY MmProcessList;
 527 extern BOOLEAN MmZeroingPageThreadActive;
 528 extern KEVENT MmZeroingPageEvent;
 529 extern ULONG MmSystemPageColor;
 530 extern ULONG MmProcessColorSeed;
 531 extern PMMWSL MmWorkingSetList;
 532 extern PFN_NUMBER MiNumberOfFreePages;
 533 extern SIZE_T MmSessionViewSize;
 534 extern SIZE_T MmSessionPoolSize;
 535 extern SIZE_T MmSessionImageSize;
 536 extern PVOID MiSystemViewStart;
 537 extern PVOID MiSessionPoolEnd;     // 0xBE000000
 538 extern PVOID MiSessionPoolStart;   // 0xBD000000
 539 extern PVOID MiSessionViewStart;   // 0xBE000000
 540
 541 BOOLEAN
 542 FORCEINLINE
 543 MiIsMemoryTypeFree(TYPE_OF_MEMORY MemoryType)
 544 {
 545     return ((MemoryType == LoaderFree) ||
 546             (MemoryType == LoaderLoadedProgram) ||
 547             (MemoryType == LoaderFirmwareTemporary) ||
 548             (MemoryType == LoaderOsloaderStack));
 549 }
 550
 551 BOOLEAN
 552 FORCEINLINE
 553 MiIsMemoryTypeInvisible(TYPE_OF_MEMORY MemoryType)
 554 {
 555     return ((MemoryType == LoaderFirmwarePermanent) ||
 556             (MemoryType == LoaderSpecialMemory) ||
 557             (MemoryType == LoaderHALCachedMemory) ||
 558             (MemoryType == LoaderBBTMemory));
 559 }
 560
 561
 562 //
 563 // Figures out the hardware bits for a PTE
 564 //
 565 ULONG_PTR
 566 FORCEINLINE
 567 MiDetermineUserGlobalPteMask(IN PVOID PointerPte)
 568 {
 569     MMPTE TempPte;
 570
 571     /* Start fresh */
 572     TempPte.u.Long = 0;
 573
 574     /* Make it valid and accessed */
 575     TempPte.u.Hard.Valid = TRUE;
 576     MI_MAKE_ACCESSED_PAGE(&TempPte);
 577
 578     /* Is this for user-mode? */
 579     if ((PointerPte <= (PVOID)MiHighestUserPte) ||
 580         ((PointerPte >= (PVOID)MiAddressToPde(NULL)) &&
 581          (PointerPte <= (PVOID)MiHighestUserPde)))
 582     {
 583         /* Set the owner bit */
 584         MI_MAKE_OWNER_PAGE(&TempPte);
 585     }
 586
 587     /* FIXME: We should also set the global bit */
 588
 589     /* Return the protection */
 590     return TempPte.u.Long;
 591 }
 592
 593 //
 594 // Creates a valid kernel PTE with the given protection
 595 //
 596 FORCEINLINE
 597 VOID
 598 MI_MAKE_HARDWARE_PTE_KERNEL(IN PMMPTE NewPte,
 599                             IN PMMPTE MappingPte,
 600                             IN ULONG_PTR ProtectionMask,
 601                             IN PFN_NUMBER PageFrameNumber)
 602 {
 603     /* Only valid for kernel, non-session PTEs */
 604     ASSERT(MappingPte > MiHighestUserPte);
 605     ASSERT(!MI_IS_SESSION_PTE(MappingPte));
 606     ASSERT((MappingPte < (PMMPTE)PDE_BASE) || (MappingPte > (PMMPTE)PDE_TOP));
 607
 608     /* Start fresh */
 609     *NewPte = ValidKernelPte;
 610
 611     /* Set the protection and page */
 612     NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
 613     NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
 614 }
 615
 616 //
 617 // Creates a valid PTE with the given protection
 618 //
 619 FORCEINLINE
 620 VOID
 621 MI_MAKE_HARDWARE_PTE(IN PMMPTE NewPte,
 622                      IN PMMPTE MappingPte,
 623                      IN ULONG_PTR ProtectionMask,
 624                      IN PFN_NUMBER PageFrameNumber)
 625 {
 626     /* Set the protection and page */
 627     NewPte->u.Long = MiDetermineUserGlobalPteMask(MappingPte);
 628     NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
 629     NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
 630 }
 631
 632 //
 633 // Creates a valid user PTE with the given protection
 634 //
 635 FORCEINLINE
 636 VOID
 637 MI_MAKE_HARDWARE_PTE_USER(IN PMMPTE NewPte,
 638                           IN PMMPTE MappingPte,
 639                           IN ULONG_PTR ProtectionMask,
 640                           IN PFN_NUMBER PageFrameNumber)
 641 {
 642     /* Only valid for kernel, non-session PTEs */
 643     ASSERT(MappingPte <= MiHighestUserPte);
 644
 645     /* Start fresh */
 646     *NewPte = ValidKernelPte;
 647
 648     /* Set the protection and page */
 649     NewPte->u.Hard.Owner = TRUE;
 650     NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
 651     NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
 652 }
 653
 654 #ifndef _M_AMD64
 655 //
 656 // Builds a Prototype PTE for the address of the PTE
 657 //
 658 FORCEINLINE
 659 VOID
 660 MI_MAKE_PROTOTYPE_PTE(IN PMMPTE NewPte,
 661                       IN PMMPTE PointerPte)
 662 {
 663     ULONG_PTR Offset;
 664
 665     /* Mark this as a prototype */
 666     NewPte->u.Long = 0;
 667     NewPte->u.Proto.Prototype = 1;
 668
 669     /*
 670      * Prototype PTEs are only valid in paged pool by design, this little trick
 671      * lets us only use 28 bits for the adress of the PTE
 672      */
 673     Offset = (ULONG_PTR)PointerPte - (ULONG_PTR)MmPagedPoolStart;
 674
 675     /* 7 bits go in the "low", and the other 21 bits go in the "high" */
 676     NewPte->u.Proto.ProtoAddressLow = Offset & 0x7F;
 677     NewPte->u.Proto.ProtoAddressHigh = (Offset & 0xFFFFFF80) >> 7;
 678     ASSERT(MiProtoPteToPte(NewPte) == PointerPte);
 679 }
 680 #endif
 681
 682 //
 683 // Returns if the page is physically resident (ie: a large page)
 684 // FIXFIX: CISC/x86 only?
 685 //
 686 FORCEINLINE
 687 BOOLEAN
 688 MI_IS_PHYSICAL_ADDRESS(IN PVOID Address)
 689 {
 690     PMMPDE PointerPde;
 691
 692     /* Large pages are never paged out, always physically resident */
 693     PointerPde = MiAddressToPde(Address);
 694     return ((PointerPde->u.Hard.LargePage) && (PointerPde->u.Hard.Valid));
 695 }
 696
 697 //
 698 // Writes a valid PTE
 699 //
 700 VOID
 701 FORCEINLINE
 702 MI_WRITE_VALID_PTE(IN PMMPTE PointerPte,
 703                    IN MMPTE TempPte)
 704 {
 705     /* Write the valid PTE */
 706     ASSERT(PointerPte->u.Hard.Valid == 0);
 707     ASSERT(TempPte.u.Hard.Valid == 1);
 708     *PointerPte = TempPte;
 709 }
 710
 711 //
 712 // Writes an invalid PTE
 713 //
 714 VOID
 715 FORCEINLINE
 716 MI_WRITE_INVALID_PTE(IN PMMPTE PointerPte,
 717                      IN MMPTE InvalidPte)
 718 {
 719     /* Write the invalid PTE */
 720     ASSERT(InvalidPte.u.Hard.Valid == 0);
 721     *PointerPte = InvalidPte;
 722 }
 723
 724 //
 725 // Writes a valid PDE
 726 //
 727 VOID
 728 FORCEINLINE
 729 MI_WRITE_VALID_PDE(IN PMMPDE PointerPde,
 730                    IN MMPDE TempPde)
 731 {
 732     /* Write the valid PDE */
 733     ASSERT(PointerPde->u.Hard.Valid == 0);
 734     ASSERT(TempPde.u.Hard.Valid == 1);
 735     *PointerPde = TempPde;
 736 }
 737
 738 //
 739 // Writes an invalid PDE
 740 //
 741 VOID
 742 FORCEINLINE
 743 MI_WRITE_INVALID_PDE(IN PMMPDE PointerPde,
 744                      IN MMPDE InvalidPde)
 745 {
 746     /* Write the invalid PDE */
 747     ASSERT(InvalidPde.u.Hard.Valid == 0);
 748     *PointerPde = InvalidPde;
 749 }
 750
 751 //
 752 // Checks if the thread already owns a working set
 753 //
 754 FORCEINLINE
 755 BOOLEAN
 756 MM_ANY_WS_LOCK_HELD(IN PETHREAD Thread)
 757 {
 758     /* If any of these are held, return TRUE */
 759     return ((Thread->OwnsProcessWorkingSetExclusive) ||
 760             (Thread->OwnsProcessWorkingSetShared) ||
 761             (Thread->OwnsSystemWorkingSetExclusive) ||
 762             (Thread->OwnsSystemWorkingSetShared) ||
 763             (Thread->OwnsSessionWorkingSetExclusive) ||
 764             (Thread->OwnsSessionWorkingSetShared));
 765 }
 766
 767 //
 768 // Checks if the process owns the working set lock
 769 //
 770 FORCEINLINE
 771 BOOLEAN
 772 MI_WS_OWNER(IN PEPROCESS Process)
 773 {
 774     /* Check if this process is the owner, and that the thread owns the WS */
 775     return ((KeGetCurrentThread()->ApcState.Process == &Process->Pcb) &&
 776             ((PsGetCurrentThread()->OwnsProcessWorkingSetExclusive) ||
 777              (PsGetCurrentThread()->OwnsProcessWorkingSetShared)));
 778 }
 779
 780 //
 781 // Locks the working set for the given process
 782 //
 783 FORCEINLINE
 784 VOID
 785 MiLockProcessWorkingSet(IN PEPROCESS Process,
 786                         IN PETHREAD Thread)
 787 {
 788     /* Shouldn't already be owning the process working set */
 789     ASSERT(Thread->OwnsProcessWorkingSetShared == FALSE);
 790     ASSERT(Thread->OwnsProcessWorkingSetExclusive == FALSE);
 791
 792     /* Block APCs, make sure that still nothing is already held */
 793     KeEnterGuardedRegion();
 794     ASSERT(!MM_ANY_WS_LOCK_HELD(Thread));
 795
 796     /* FIXME: Actually lock it (we can't because Vm is used by MAREAs) */
 797
 798     /* FIXME: This also can't be checked because Vm is used by MAREAs) */
 799     //ASSERT(Process->Vm.Flags.AcquiredUnsafe == 0);
 800
 801     /* Okay, now we can own it exclusively */
 802     ASSERT(Thread->OwnsProcessWorkingSetExclusive == FALSE);
 803     Thread->OwnsProcessWorkingSetExclusive = TRUE;
 804 }
 805
 806 //
 807 // Unlocks the working set for the given process
 808 //
 809 FORCEINLINE
 810 VOID
 811 MiUnlockProcessWorkingSet(IN PEPROCESS Process,
 812                           IN PETHREAD Thread)
 813 {
 814     /* Make sure this process really is owner, and it was a safe acquisition */
 815     ASSERT(MI_WS_OWNER(Process));
 816     /* This can't be checked because Vm is used by MAREAs) */
 817     //ASSERT(Process->Vm.Flags.AcquiredUnsafe == 0);
 818
 819     /* The thread doesn't own it anymore */
 820     ASSERT(Thread->OwnsProcessWorkingSetExclusive == TRUE);
 821     Thread->OwnsProcessWorkingSetExclusive = FALSE;
 822
 823     /* FIXME: Actually release it (we can't because Vm is used by MAREAs) */
 824
 825     /* Unblock APCs */
 826     KeLeaveGuardedRegion();
 827 }
 828
 829 //
 830 // Locks the working set
 831 //
 832 FORCEINLINE
 833 VOID
 834 MiLockWorkingSet(IN PETHREAD Thread,
 835                  IN PMMSUPPORT WorkingSet)
 836 {
 837     /* Block APCs */
 838     KeEnterGuardedRegion();
 839
 840     /* Working set should be in global memory */
 841     ASSERT(MI_IS_SESSION_ADDRESS((PVOID)WorkingSet) == FALSE);
 842
 843     /* Thread shouldn't already be owning something */
 844     ASSERT(!MM_ANY_WS_LOCK_HELD(Thread));
 845
 846     /* FIXME: Actually lock it (we can't because Vm is used by MAREAs) */
 847
 848     /* Which working set is this? */
 849     if (WorkingSet == &MmSystemCacheWs)
 850     {
 851         /* Own the system working set */
 852         ASSERT((Thread->OwnsSystemWorkingSetExclusive == FALSE) &&
 853                (Thread->OwnsSystemWorkingSetShared == FALSE));
 854         Thread->OwnsSystemWorkingSetExclusive = TRUE;
 855     }
 856     else if (WorkingSet->Flags.SessionSpace)
 857     {
 858         /* We don't implement this yet */
 859         UNIMPLEMENTED;
 860         while (TRUE);
 861     }
 862     else
 863     {
 864         /* Own the process working set */
 865         ASSERT((Thread->OwnsProcessWorkingSetExclusive == FALSE) &&
 866                (Thread->OwnsProcessWorkingSetShared == FALSE));
 867         Thread->OwnsProcessWorkingSetExclusive = TRUE;
 868     }
 869 }
 870
 871 //
 872 // Unlocks the working set
 873 //
 874 FORCEINLINE
 875 VOID
 876 MiUnlockWorkingSet(IN PETHREAD Thread,
 877                    IN PMMSUPPORT WorkingSet)
 878 {
 879     /* Working set should be in global memory */
 880     ASSERT(MI_IS_SESSION_ADDRESS((PVOID)WorkingSet) == FALSE);
 881
 882     /* Which working set is this? */
 883     if (WorkingSet == &MmSystemCacheWs)
 884     {
 885         /* Release the system working set */
 886         ASSERT((Thread->OwnsSystemWorkingSetExclusive == TRUE) ||
 887                (Thread->OwnsSystemWorkingSetShared == TRUE));
 888         Thread->OwnsSystemWorkingSetExclusive = FALSE;
 889     }
 890     else if (WorkingSet->Flags.SessionSpace)
 891     {
 892         /* We don't implement this yet */
 893         UNIMPLEMENTED;
 894         while (TRUE);
 895     }
 896     else
 897     {
 898         /* Release the process working set */
 899         ASSERT((Thread->OwnsProcessWorkingSetExclusive) ||
 900                (Thread->OwnsProcessWorkingSetShared));
 901         Thread->OwnsProcessWorkingSetExclusive = FALSE;
 902     }
 903
 904     /* FIXME: Actually release it (we can't because Vm is used by MAREAs) */
 905
 906     /* Unblock APCs */
 907     KeLeaveGuardedRegion();
 908 }
 909
 910 //
 911 // Returns the ProtoPTE inside a VAD for the given VPN
 912 //
 913 FORCEINLINE
 914 PMMPTE
 915 MI_GET_PROTOTYPE_PTE_FOR_VPN(IN PMMVAD Vad,
 916                              IN ULONG_PTR Vpn)
 917 {
 918     PMMPTE ProtoPte;
 919
 920     /* Find the offset within the VAD's prototype PTEs */
 921     ProtoPte = Vad->FirstPrototypePte + (Vpn - Vad->StartingVpn);
 922     ASSERT(ProtoPte <= Vad->LastContiguousPte);
 923     return ProtoPte;
 924 }
 925
 926 //
 927 // Returns the PFN Database entry for the given page number
 928 // Warning: This is not necessarily a valid PFN database entry!
 929 //
 930 FORCEINLINE
 931 PMMPFN
 932 MI_PFN_ELEMENT(IN PFN_NUMBER Pfn)
 933 {
 934     /* Get the entry */
 935     return &MmPfnDatabase[Pfn];
 936 };
 937
 938 BOOLEAN
 939 NTAPI
 940 MmArmInitSystem(
 941     IN ULONG Phase,
 942     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 943 );
 944
 945 VOID
 946 NTAPI
 947 MiInitializeSessionSpaceLayout();
 948
 949 NTSTATUS
 950 NTAPI
 951 MiInitMachineDependent(
 952     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 953 );
 954
 955 VOID
 956 NTAPI
 957 MiComputeColorInformation(
 958     VOID
 959 );
 960
 961 VOID
 962 NTAPI
 963 MiMapPfnDatabase(
 964     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 965 );
 966
 967 VOID
 968 NTAPI
 969 MiInitializeColorTables(
 970     VOID
 971 );
 972
 973 VOID
 974 NTAPI
 975 MiInitializePfnDatabase(
 976     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 977 );
 978
 979 BOOLEAN
 980 NTAPI
 981 MiInitializeMemoryEvents(
 982     VOID
 983 );
 984
 985 PFN_NUMBER
 986 NTAPI
 987 MxGetNextPage(
 988     IN PFN_NUMBER PageCount
 989 );
 990
 991 PPHYSICAL_MEMORY_DESCRIPTOR
 992 NTAPI
 993 MmInitializeMemoryLimits(
 994     IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 995     IN PBOOLEAN IncludeType
 996 );
 997
 998 PFN_NUMBER
 999 NTAPI
1000 MiPagesInLoaderBlock(
1001     IN PLOADER_PARAMETER_BLOCK LoaderBlock,
1002     IN PBOOLEAN IncludeType
1003 );
1004
1005 VOID
1006 FASTCALL
1007 MiSyncARM3WithROS(
1008     IN PVOID AddressStart,
1009     IN PVOID AddressEnd
1010 );
1011
1012 NTSTATUS
1013 NTAPI
1014 MmArmAccessFault(
1015     IN BOOLEAN StoreInstruction,
1016     IN PVOID Address,
1017     IN KPROCESSOR_MODE Mode,
1018     IN PVOID TrapInformation
1019 );
1020
1021 NTSTATUS
1022 FASTCALL
1023 MiCheckPdeForPagedPool(
1024     IN PVOID Address
1025 );
1026
1027 VOID
1028 NTAPI
1029 MiInitializeNonPagedPool(
1030     VOID
1031 );
1032
1033 VOID
1034 NTAPI
1035 MiInitializeNonPagedPoolThresholds(
1036     VOID
1037 );
1038
1039 VOID
1040 NTAPI
1041 MiInitializePoolEvents(
1042     VOID
1043 );
1044
1045 VOID                      //
1046 NTAPI                     //
1047 InitializePool(           //
1048     IN POOL_TYPE PoolType,// FIXFIX: This should go in ex.h after the pool merge
1049     IN ULONG Threshold    //
1050 );                        //
1051
1052 VOID
1053 NTAPI
1054 MiInitializeSystemPtes(
1055     IN PMMPTE StartingPte,
1056     IN ULONG NumberOfPtes,
1057     IN MMSYSTEM_PTE_POOL_TYPE PoolType
1058 );
1059
1060 PMMPTE
1061 NTAPI
1062 MiReserveSystemPtes(
1063     IN ULONG NumberOfPtes,
1064     IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType
1065 );
1066
1067 VOID
1068 NTAPI
1069 MiReleaseSystemPtes(
1070     IN PMMPTE StartingPte,
1071     IN ULONG NumberOfPtes,
1072     IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType
1073 );
1074
1075
1076 PFN_NUMBER
1077 NTAPI
1078 MiFindContiguousPages(
1079     IN PFN_NUMBER LowestPfn,
1080     IN PFN_NUMBER HighestPfn,
1081     IN PFN_NUMBER BoundaryPfn,
1082     IN PFN_NUMBER SizeInPages,
1083     IN MEMORY_CACHING_TYPE CacheType
1084 );
1085
1086 PVOID
1087 NTAPI
1088 MiCheckForContiguousMemory(
1089     IN PVOID BaseAddress,
1090     IN PFN_NUMBER BaseAddressPages,
1091     IN PFN_NUMBER SizeInPages,
1092     IN PFN_NUMBER LowestPfn,
1093     IN PFN_NUMBER HighestPfn,
1094     IN PFN_NUMBER BoundaryPfn,
1095     IN MI_PFN_CACHE_ATTRIBUTE CacheAttribute
1096 );
1097
1098 PMDL
1099 NTAPI
1100 MiAllocatePagesForMdl(
1101     IN PHYSICAL_ADDRESS LowAddress,
1102     IN PHYSICAL_ADDRESS HighAddress,
1103     IN PHYSICAL_ADDRESS SkipBytes,
1104     IN SIZE_T TotalBytes,
1105     IN MI_PFN_CACHE_ATTRIBUTE CacheAttribute,
1106     IN ULONG Flags
1107 );
1108
1109 PVOID
1110 NTAPI
1111 MiMapLockedPagesInUserSpace(
1112     IN PMDL Mdl,
1113     IN PVOID BaseVa,
1114     IN MEMORY_CACHING_TYPE CacheType,
1115     IN PVOID BaseAddress
1116 );
1117
1118 VOID
1119 NTAPI
1120 MiUnmapLockedPagesInUserSpace(
1121     IN PVOID BaseAddress,
1122     IN PMDL Mdl
1123 );
1124
1125 VOID
1126 NTAPI
1127 MiInsertPageInList(
1128     IN PMMPFNLIST ListHead,
1129     IN PFN_NUMBER PageFrameIndex
1130 );
1131
1132 VOID
1133 NTAPI
1134 MiUnlinkFreeOrZeroedPage(
1135     IN PMMPFN Entry
1136 );
1137
1138 PFN_NUMBER
1139 NTAPI
1140 MiAllocatePfn(
1141     IN PMMPTE PointerPte,
1142     IN ULONG Protection
1143 );
1144
1145 VOID
1146 NTAPI
1147 MiInitializePfn(
1148     IN PFN_NUMBER PageFrameIndex,
1149     IN PMMPTE PointerPte,
1150     IN BOOLEAN Modified
1151 );
1152
1153 VOID
1154 NTAPI
1155 MiInitializePfnAndMakePteValid(
1156     IN PFN_NUMBER PageFrameIndex,
1157     IN PMMPTE PointerPte,
1158     IN MMPTE TempPte
1159 );
1160
1161 VOID
1162 NTAPI
1163 MiInitializePfnForOtherProcess(
1164     IN PFN_NUMBER PageFrameIndex,
1165     IN PMMPTE PointerPte,
1166     IN PFN_NUMBER PteFrame
1167 );
1168
1169 VOID
1170 NTAPI
1171 MiDecrementShareCount(
1172     IN PMMPFN Pfn1,
1173     IN PFN_NUMBER PageFrameIndex
1174 );
1175
1176 VOID
1177 NTAPI
1178 MiDecrementReferenceCount(
1179     IN PMMPFN Pfn1,
1180     IN PFN_NUMBER PageFrameIndex
1181 );
1182
1183 PFN_NUMBER
1184 NTAPI
1185 MiRemoveAnyPage(
1186     IN ULONG Color
1187 );
1188
1189 PFN_NUMBER
1190 NTAPI
1191 MiRemoveZeroPage(
1192     IN ULONG Color
1193 );
1194
1195 VOID
1196 NTAPI
1197 MiZeroPhysicalPage(
1198     IN PFN_NUMBER PageFrameIndex
1199 );
1200
1201 VOID
1202 NTAPI
1203 MiInsertPageInFreeList(
1204     IN PFN_NUMBER PageFrameIndex
1205 );
1206
1207 PFN_COUNT
1208 NTAPI
1209 MiDeleteSystemPageableVm(
1210     IN PMMPTE PointerPte,
1211     IN PFN_NUMBER PageCount,
1212     IN ULONG Flags,
1213     OUT PPFN_NUMBER ValidPages
1214 );
1215
1216 PLDR_DATA_TABLE_ENTRY
1217 NTAPI
1218 MiLookupDataTableEntry(
1219     IN PVOID Address
1220 );
1221
1222 VOID
1223 NTAPI
1224 MiInitializeDriverLargePageList(
1225     VOID
1226 );
1227
1228 VOID
1229 NTAPI
1230 MiInitializeLargePageSupport(
1231     VOID
1232 );
1233
1234 VOID
1235 NTAPI
1236 MiSyncCachedRanges(
1237     VOID
1238 );
1239
1240 BOOLEAN
1241 NTAPI
1242 MiIsPfnInUse(
1243     IN PMMPFN Pfn1
1244 );
1245
1246 PMMVAD
1247 NTAPI
1248 MiLocateAddress(
1249     IN PVOID VirtualAddress
1250 );
1251
1252 PMMADDRESS_NODE
1253 NTAPI
1254 MiCheckForConflictingNode(
1255     IN ULONG_PTR StartVpn,
1256     IN ULONG_PTR EndVpn,
1257     IN PMM_AVL_TABLE Table
1258 );
1259
1260 TABLE_SEARCH_RESULT
1261 NTAPI
1262 MiFindEmptyAddressRangeDownTree(
1263     IN SIZE_T Length,
1264     IN ULONG_PTR BoundaryAddress,
1265     IN ULONG_PTR Alignment,
1266     IN PMM_AVL_TABLE Table,
1267     OUT PULONG_PTR Base,
1268     OUT PMMADDRESS_NODE *Parent
1269 );
1270
1271 NTSTATUS
1272 NTAPI
1273 MiFindEmptyAddressRangeInTree(
1274     IN SIZE_T Length,
1275     IN ULONG_PTR Alignment,
1276     IN PMM_AVL_TABLE Table,
1277     OUT PMMADDRESS_NODE *PreviousVad,
1278     OUT PULONG_PTR Base
1279 );
1280
1281 VOID
1282 NTAPI
1283 MiInsertVad(
1284     IN PMMVAD Vad,
1285     IN PEPROCESS Process
1286 );
1287
1288 VOID
1289 NTAPI
1290 MiInsertNode(
1291     IN PMM_AVL_TABLE Table,
1292     IN PMMADDRESS_NODE NewNode,
1293     PMMADDRESS_NODE Parent,
1294     TABLE_SEARCH_RESULT Result
1295 );
1296
1297 VOID
1298 NTAPI
1299 MiRemoveNode(
1300     IN PMMADDRESS_NODE Node,
1301     IN PMM_AVL_TABLE Table
1302 );
1303
1304 PMMADDRESS_NODE
1305 NTAPI
1306 MiGetPreviousNode(
1307     IN PMMADDRESS_NODE Node
1308 );
1309
1310 PMMADDRESS_NODE
1311 NTAPI
1312 MiGetNextNode(
1313     IN PMMADDRESS_NODE Node
1314 );
1315
1316 BOOLEAN
1317 NTAPI
1318 MiInitializeSystemSpaceMap(
1319     IN PVOID InputSession OPTIONAL
1320 );
1321
1322 ULONG
1323 NTAPI
1324 MiMakeProtectionMask(
1325     IN ULONG Protect
1326 );
1327
1328 VOID
1329 NTAPI
1330 MiDeleteVirtualAddresses(
1331     IN ULONG_PTR Va,
1332     IN ULONG_PTR EndingAddress,
1333     IN PMMVAD Vad
1334 );
1335
1336 ULONG
1337 NTAPI
1338 MiMakeSystemAddressValid(
1339     IN PVOID PageTableVirtualAddress,
1340     IN PEPROCESS CurrentProcess
1341 );
1342
1343 ULONG
1344 NTAPI
1345 MiMakeSystemAddressValidPfn(
1346     IN PVOID VirtualAddress,
1347     IN KIRQL OldIrql
1348 );
1349
1350 VOID
1351 NTAPI
1352 MiRemoveMappedView(
1353     IN PEPROCESS CurrentProcess,
1354     IN PMMVAD Vad
1355 );
1356
1357 PSUBSECTION
1358 NTAPI
1359 MiLocateSubsection(
1360     IN PMMVAD Vad,
1361     IN ULONG_PTR Vpn
1362 );
1363
1364 //
1365 // MiRemoveZeroPage will use inline code to zero out the page manually if only
1366 // free pages are available. In some scenarios, we don't/can't run that piece of
1367 // code and would rather only have a real zero page. If we can't have a zero page,
1368 // then we'd like to have our own code to grab a free page and zero it out, by
1369 // using MiRemoveAnyPage. This macro implements this.
1370 //
1371 PFN_NUMBER
1372 FORCEINLINE
1373 MiRemoveZeroPageSafe(IN ULONG Color)
1374 {
1375     if (MmFreePagesByColor[ZeroedPageList][Color].Flink != LIST_HEAD) return MiRemoveZeroPage(Color);
1376     return 0;
1377 }
1378
1379 //
1380 // New ARM3<->RosMM PAGE Architecture
1381 //
1382 #define MI_GET_ROS_DATA(x)   ((PMMROSPFN)(x->RosMmData))
1383 #define MI_IS_ROS_PFN(x)     (((x)->u4.AweAllocation == TRUE) && (MI_GET_ROS_DATA(x) != NULL))
1384 #define ASSERT_IS_ROS_PFN(x) ASSERT(MI_IS_ROS_PFN(x) == TRUE);
1385 typedef struct _MMROSPFN
1386 {
1387     PMM_RMAP_ENTRY RmapListHead;
1388     SWAPENTRY SwapEntry;
1389 } MMROSPFN, *PMMROSPFN;
1390
1391 #define RosMmData            AweReferenceCount
1392
1393 /* EOF */