ntoskrnl/mm/ARM3/miarm.h

   1 /*
   2  * PROJECT:         ReactOS Kernel
   3  * LICENSE:         BSD - See COPYING.ARM in the top level directory
   4  * FILE:            ntoskrnl/mm/ARM3/miarm.h
   5  * PURPOSE:         ARM Memory Manager Header
   6  * PROGRAMMERS:     ReactOS Portable Systems Group
   7  */
   8
   9 #ifndef _M_AMD64
  10
  11 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING   ((255 * _1MB) >> PAGE_SHIFT)
  12 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING          ((19 * _1MB) >> PAGE_SHIFT)
  13 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST           ((32 * _1MB) >> PAGE_SHIFT)
  14 #define MI_MAX_INIT_NONPAGED_POOL_SIZE          (128 * _1MB)
  15 #define MI_MAX_NONPAGED_POOL_SIZE               (128 * _1MB)
  16 #define MI_MAX_FREE_PAGE_LISTS                  4
  17
  18 #define MI_MIN_INIT_PAGED_POOLSIZE              (32 * _1MB)
  19
  20 #define MI_SESSION_VIEW_SIZE                    (20 * _1MB)
  21 #define MI_SESSION_POOL_SIZE                    (16 * _1MB)
  22 #define MI_SESSION_IMAGE_SIZE                   (8 * _1MB)
  23 #define MI_SESSION_WORKING_SET_SIZE             (4 * _1MB)
  24 #define MI_SESSION_SIZE                         (MI_SESSION_VIEW_SIZE + \
  25                                                  MI_SESSION_POOL_SIZE + \
  26                                                  MI_SESSION_IMAGE_SIZE + \
  27                                                  MI_SESSION_WORKING_SET_SIZE)
  28
  29 #define MI_SYSTEM_VIEW_SIZE                     (16 * _1MB)
  30
  31 #define MI_SYSTEM_CACHE_WS_START                (PVOID)0xC0C00000
  32 #define MI_PAGED_POOL_START                     (PVOID)0xE1000000
  33 #define MI_NONPAGED_POOL_END                    (PVOID)0xFFBE0000
  34 #define MI_DEBUG_MAPPING                        (PVOID)0xFFBFF000
  35
  36 #define MI_SYSTEM_PTE_BASE                      (PVOID)MiAddressToPte(NULL)
  37
  38 #define MI_MIN_SECONDARY_COLORS                 8
  39 #define MI_SECONDARY_COLORS                     64
  40 #define MI_MAX_SECONDARY_COLORS                 1024
  41
  42 #define MI_MIN_ALLOCATION_FRAGMENT              (4 * _1KB)
  43 #define MI_ALLOCATION_FRAGMENT                  (64 * _1KB)
  44 #define MI_MAX_ALLOCATION_FRAGMENT              (2  * _1MB)
  45
  46 #define MM_HIGHEST_VAD_ADDRESS \
  47     (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
  48
  49 /* The range 0x10000->0x7FEFFFFF is reserved for the ROSMM MAREA Allocator */
  50 #define MI_LOWEST_VAD_ADDRESS                   (PVOID)0x7FF00000
  51
  52 #endif /* !_M_AMD64 */
  53
  54 /* Make the code cleaner with some definitions for size multiples */
  55 #define _1KB (1024u)
  56 #define _1MB (1024 * _1KB)
  57 #define _1GB (1024 * _1MB)
  58
  59 /* Everyone loves 64K */
  60 #define _64K (64 * _1KB)
  61
  62 /* Area mapped by a PDE */
  63 #define PDE_MAPPED_VA  (PTE_COUNT * PAGE_SIZE)
  64
  65 /* Size of a page table */
  66 #define PT_SIZE  (PTE_COUNT * sizeof(MMPTE))
  67
  68 /* Size of a page directory */
  69 #define PD_SIZE  (PDE_COUNT * sizeof(MMPDE))
  70
  71 /* Size of all page directories for a process */
  72 #define SYSTEM_PD_SIZE (PD_COUNT * PD_SIZE)
  73
  74 /* Architecture specific count of PDEs in a directory, and count of PTEs in a PT */
  75 #ifdef _M_IX86
  76 #define PD_COUNT  1
  77 #define PDE_COUNT 1024
  78 #define PTE_COUNT 1024
  79 C_ASSERT(SYSTEM_PD_SIZE == PAGE_SIZE);
  80 #elif _M_ARM
  81 #define PD_COUNT  1
  82 #define PDE_COUNT 4096
  83 #define PTE_COUNT 256
  84 #else
  85 #define PD_COUNT  PPE_PER_PAGE
  86 #define PDE_COUNT PDE_PER_PAGE
  87 #define PTE_COUNT PTE_PER_PAGE
  88 #endif
  89
  90 #ifdef _M_IX86
  91 #define IMAGE_FILE_MACHINE_NATIVE   IMAGE_FILE_MACHINE_I386
  92 #elif _M_ARM
  93 #define IMAGE_FILE_MACHINE_NATIVE   IMAGE_FILE_MACHINE_ARM
  94 #elif _M_AMD64
  95 #define IMAGE_FILE_MACHINE_NATIVE   IMAGE_FILE_MACHINE_AMD64
  96 #else
  97 #error Define these please!
  98 #endif
  99
 100 //
 101 // Protection Bits part of the internal memory manager Protection Mask
 102 // Taken from http://www.reactos.org/wiki/Techwiki:Memory_management_in_the_Windows_XP_kernel
 103 // and public assertions.
 104 //
 105 #define MM_ZERO_ACCESS         0
 106 #define MM_READONLY            1
 107 #define MM_EXECUTE             2
 108 #define MM_EXECUTE_READ        3
 109 #define MM_READWRITE           4
 110 #define MM_WRITECOPY           5
 111 #define MM_EXECUTE_READWRITE   6
 112 #define MM_EXECUTE_WRITECOPY   7
 113 #define MM_NOCACHE             8
 114 #define MM_DECOMMIT            0x10
 115 #define MM_NOACCESS            (MM_DECOMMIT | MM_NOCACHE)
 116 #define MM_INVALID_PROTECTION  0xFFFFFFFF
 117
 118 //
 119 // Specific PTE Definitions that map to the Memory Manager's Protection Mask Bits
 120 // The Memory Manager's definition define the attributes that must be preserved
 121 // and these PTE definitions describe the attributes in the hardware sense. This
 122 // helps deal with hardware differences between the actual boolean expression of
 123 // the argument.
 124 //
 125 // For example, in the logical attributes, we want to express read-only as a flag
 126 // but on x86, it is writability that must be set. On the other hand, on x86, just
 127 // like in the kernel, it is disabling the caches that requires a special flag,
 128 // while on certain architectures such as ARM, it is enabling the cache which
 129 // requires a flag.
 130 //
 131 #if defined(_M_IX86) || defined(_M_AMD64)
 132 //
 133 // Access Flags
 134 //
 135 #define PTE_READONLY            0
 136 #define PTE_EXECUTE             0 // Not worrying about NX yet
 137 #define PTE_EXECUTE_READ        0 // Not worrying about NX yet
 138 #define PTE_READWRITE           0x2
 139 #define PTE_WRITECOPY           0x200
 140 #define PTE_EXECUTE_READWRITE   0x0
 141 #define PTE_EXECUTE_WRITECOPY   0x200
 142 #define PTE_PROTOTYPE           0x400
 143 //
 144 // Cache flags
 145 //
 146 #define PTE_ENABLE_CACHE        0
 147 #define PTE_DISABLE_CACHE       0x10
 148 #define PTE_WRITECOMBINED_CACHE 0x10
 149 #elif defined(_M_ARM)
 150 #else
 151 #error Define these please!
 152 #endif
 153
 154 extern const ULONG MmProtectToPteMask[32];
 155
 156 //
 157 // Assertions for session images, addresses, and PTEs
 158 //
 159 #define MI_IS_SESSION_IMAGE_ADDRESS(Address) \
 160     (((Address) >= MiSessionImageStart) && ((Address) < MiSessionImageEnd))
 161
 162 #define MI_IS_SESSION_ADDRESS(Address) \
 163     (((Address) >= MmSessionBase) && ((Address) < MiSessionSpaceEnd))
 164
 165 #define MI_IS_SESSION_PTE(Pte) \
 166     ((((PMMPTE)Pte) >= MiSessionBasePte) && (((PMMPTE)Pte) < MiSessionLastPte))
 167
 168 #define MI_IS_PAGE_TABLE_ADDRESS(Address) \
 169     (((PVOID)(Address) >= (PVOID)PTE_BASE) && ((PVOID)(Address) <= (PVOID)PTE_TOP))
 170
 171 #define MI_IS_SYSTEM_PAGE_TABLE_ADDRESS(Address) \
 172     (((Address) >= (PVOID)MiAddressToPte(MmSystemRangeStart)) && ((Address) <= (PVOID)PTE_TOP))
 173
 174 #define MI_IS_PAGE_TABLE_OR_HYPER_ADDRESS(Address) \
 175     (((PVOID)(Address) >= (PVOID)PTE_BASE) && ((PVOID)(Address) <= (PVOID)MmHyperSpaceEnd))
 176
 177 //
 178 // Corresponds to MMPTE_SOFTWARE.Protection
 179 //
 180 #ifdef _M_IX86
 181 #define MM_PTE_SOFTWARE_PROTECTION_BITS   5
 182 #elif _M_ARM
 183 #define MM_PTE_SOFTWARE_PROTECTION_BITS   5
 184 #elif _M_AMD64
 185 #define MM_PTE_SOFTWARE_PROTECTION_BITS   5
 186 #else
 187 #error Define these please!
 188 #endif
 189
 190 //
 191 // Creates a software PTE with the given protection
 192 //
 193 #define MI_MAKE_SOFTWARE_PTE(p, x)          ((p)->u.Long = (x << MM_PTE_SOFTWARE_PROTECTION_BITS))
 194
 195 //
 196 // Marks a PTE as deleted
 197 //
 198 #define MI_SET_PFN_DELETED(x)               ((x)->PteAddress = (PMMPTE)((ULONG_PTR)(x)->PteAddress | 1))
 199 #define MI_IS_PFN_DELETED(x)                ((ULONG_PTR)((x)->PteAddress) & 1)
 200
 201 //
 202 // Special values for LoadedImports
 203 //
 204 #define MM_SYSLDR_NO_IMPORTS   (PVOID)0xFFFFFFFE
 205 #define MM_SYSLDR_BOOT_LOADED  (PVOID)0xFFFFFFFF
 206 #define MM_SYSLDR_SINGLE_ENTRY 0x1
 207
 208 #if defined(_M_IX86) || defined(_M_ARM)
 209 //
 210 // PFN List Sentinel
 211 //
 212 #define LIST_HEAD 0xFFFFFFFF
 213
 214 //
 215 // Because GCC cannot automatically downcast 0xFFFFFFFF to lesser-width bits,
 216 // we need a manual definition suited to the number of bits in the PteFrame.
 217 // This is used as a LIST_HEAD for the colored list
 218 //
 219 #define COLORED_LIST_HEAD ((1 << 25) - 1) // 0x1FFFFFF
 220 #elif defined(_M_AMD64)
 221 #define LIST_HEAD 0xFFFFFFFFFFFFFFFFLL
 222 #define COLORED_LIST_HEAD ((1 << 57) - 1) // 0x1FFFFFFFFFFFFFFLL
 223 #else
 224 #error Define these please!
 225 #endif
 226
 227 //
 228 // Special IRQL value (found in assertions)
 229 //
 230 #define MM_NOIRQL (KIRQL)0xFFFFFFFF
 231
 232 //
 233 // Returns the color of a page
 234 //
 235 #define MI_GET_PAGE_COLOR(x)                ((x) & MmSecondaryColorMask)
 236 #define MI_GET_NEXT_COLOR(x)                (MI_GET_PAGE_COLOR(++MmSystemPageColor))
 237 #define MI_GET_NEXT_PROCESS_COLOR(x)        (MI_GET_PAGE_COLOR(++(x)->NextPageColor))
 238
 239 #ifdef _M_IX86
 240 //
 241 // Decodes a Prototype PTE into the underlying PTE
 242 //
 243 #define MiProtoPteToPte(x)                  \
 244     (PMMPTE)((ULONG_PTR)MmPagedPoolStart +  \
 245              ((x)->u.Proto.ProtoAddressHigh | (x)->u.Proto.ProtoAddressLow))
 246 #endif
 247
 248 //
 249 // Prototype PTEs that don't yet have a pagefile association
 250 //
 251 #define MI_PTE_LOOKUP_NEEDED 0xFFFFF
 252
 253 //
 254 // System views are binned into 64K chunks
 255 //
 256 #define MI_SYSTEM_VIEW_BUCKET_SIZE  _64K
 257
 258 //
 259 // FIXFIX: These should go in ex.h after the pool merge
 260 //
 261 #ifdef _M_AMD64
 262 #define POOL_BLOCK_SIZE 16
 263 #else
 264 #define POOL_BLOCK_SIZE  8
 265 #endif
 266 #define POOL_LISTS_PER_PAGE (PAGE_SIZE / POOL_BLOCK_SIZE)
 267 #define BASE_POOL_TYPE_MASK 1
 268 #define POOL_MAX_ALLOC (PAGE_SIZE - (sizeof(POOL_HEADER) + POOL_BLOCK_SIZE))
 269
 270 typedef struct _POOL_DESCRIPTOR
 271 {
 272     POOL_TYPE PoolType;
 273     ULONG PoolIndex;
 274     ULONG RunningAllocs;
 275     ULONG RunningDeAllocs;
 276     ULONG TotalPages;
 277     ULONG TotalBigPages;
 278     ULONG Threshold;
 279     PVOID LockAddress;
 280     PVOID PendingFrees;
 281     LONG PendingFreeDepth;
 282     SIZE_T TotalBytes;
 283     SIZE_T Spare0;
 284     LIST_ENTRY ListHeads[POOL_LISTS_PER_PAGE];
 285 } POOL_DESCRIPTOR, *PPOOL_DESCRIPTOR;
 286
 287 typedef struct _POOL_HEADER
 288 {
 289     union
 290     {
 291         struct
 292         {
 293 #ifdef _M_AMD64
 294             ULONG PreviousSize:8;
 295             ULONG PoolIndex:8;
 296             ULONG BlockSize:8;
 297             ULONG PoolType:8;
 298 #else
 299             USHORT PreviousSize:9;
 300             USHORT PoolIndex:7;
 301             USHORT BlockSize:9;
 302             USHORT PoolType:7;
 303 #endif
 304         };
 305         ULONG Ulong1;
 306     };
 307 #ifdef _M_AMD64
 308     ULONG PoolTag;
 309 #endif
 310     union
 311     {
 312 #ifdef _M_AMD64
 313         PEPROCESS ProcessBilled;
 314 #else
 315         ULONG PoolTag;
 316 #endif
 317         struct
 318         {
 319             USHORT AllocatorBackTraceIndex;
 320             USHORT PoolTagHash;
 321         };
 322     };
 323 } POOL_HEADER, *PPOOL_HEADER;
 324
 325 C_ASSERT(sizeof(POOL_HEADER) == POOL_BLOCK_SIZE);
 326 C_ASSERT(POOL_BLOCK_SIZE == sizeof(LIST_ENTRY));
 327
 328 extern ULONG ExpNumberOfPagedPools;
 329 extern POOL_DESCRIPTOR NonPagedPoolDescriptor;
 330 extern PPOOL_DESCRIPTOR ExpPagedPoolDescriptor[16 + 1];
 331 extern PVOID PoolTrackTable;
 332
 333 //
 334 // END FIXFIX
 335 //
 336
 337 typedef struct _MI_LARGE_PAGE_DRIVER_ENTRY
 338 {
 339     LIST_ENTRY Links;
 340     UNICODE_STRING BaseName;
 341 } MI_LARGE_PAGE_DRIVER_ENTRY, *PMI_LARGE_PAGE_DRIVER_ENTRY;
 342
 343 typedef enum _MMSYSTEM_PTE_POOL_TYPE
 344 {
 345     SystemPteSpace,
 346     NonPagedPoolExpansion,
 347     MaximumPtePoolTypes
 348 } MMSYSTEM_PTE_POOL_TYPE;
 349
 350 typedef enum _MI_PFN_CACHE_ATTRIBUTE
 351 {
 352     MiNonCached,
 353     MiCached,
 354     MiWriteCombined,
 355     MiNotMapped
 356 } MI_PFN_CACHE_ATTRIBUTE, *PMI_PFN_CACHE_ATTRIBUTE;
 357
 358 typedef struct _PHYSICAL_MEMORY_RUN
 359 {
 360     ULONG BasePage;
 361     ULONG PageCount;
 362 } PHYSICAL_MEMORY_RUN, *PPHYSICAL_MEMORY_RUN;
 363
 364 typedef struct _PHYSICAL_MEMORY_DESCRIPTOR
 365 {
 366     ULONG NumberOfRuns;
 367     ULONG NumberOfPages;
 368     PHYSICAL_MEMORY_RUN Run[1];
 369 } PHYSICAL_MEMORY_DESCRIPTOR, *PPHYSICAL_MEMORY_DESCRIPTOR;
 370
 371 typedef struct _MMCOLOR_TABLES
 372 {
 373     PFN_NUMBER Flink;
 374     PVOID Blink;
 375     PFN_NUMBER Count;
 376 } MMCOLOR_TABLES, *PMMCOLOR_TABLES;
 377
 378 typedef struct _MI_LARGE_PAGE_RANGES
 379 {
 380     PFN_NUMBER StartFrame;
 381     PFN_NUMBER LastFrame;
 382 } MI_LARGE_PAGE_RANGES, *PMI_LARGE_PAGE_RANGES;
 383
 384 typedef struct _MMVIEW
 385 {
 386     ULONG_PTR Entry;
 387     PCONTROL_AREA ControlArea;
 388 } MMVIEW, *PMMVIEW;
 389
 390 typedef struct _MMSESSION
 391 {
 392     KGUARDED_MUTEX SystemSpaceViewLock;
 393     PKGUARDED_MUTEX SystemSpaceViewLockPointer;
 394     PCHAR SystemSpaceViewStart;
 395     PMMVIEW SystemSpaceViewTable;
 396     ULONG SystemSpaceHashSize;
 397     ULONG SystemSpaceHashEntries;
 398     ULONG SystemSpaceHashKey;
 399     ULONG BitmapFailures;
 400     PRTL_BITMAP SystemSpaceBitMap;
 401 } MMSESSION, *PMMSESSION;
 402
 403 extern MMPTE HyperTemplatePte;
 404 extern MMPDE ValidKernelPde;
 405 extern MMPTE ValidKernelPte;
 406 extern MMPDE DemandZeroPde;
 407 extern MMPTE PrototypePte;
 408 extern BOOLEAN MmLargeSystemCache;
 409 extern BOOLEAN MmZeroPageFile;
 410 extern BOOLEAN MmProtectFreedNonPagedPool;
 411 extern BOOLEAN MmTrackLockedPages;
 412 extern BOOLEAN MmTrackPtes;
 413 extern BOOLEAN MmDynamicPfn;
 414 extern BOOLEAN MmMirroring;
 415 extern BOOLEAN MmMakeLowMemory;
 416 extern BOOLEAN MmEnforceWriteProtection;
 417 extern SIZE_T MmAllocationFragment;
 418 extern ULONG MmConsumedPoolPercentage;
 419 extern ULONG MmVerifyDriverBufferType;
 420 extern ULONG MmVerifyDriverLevel;
 421 extern WCHAR MmVerifyDriverBuffer[512];
 422 extern WCHAR MmLargePageDriverBuffer[512];
 423 extern LIST_ENTRY MiLargePageDriverList;
 424 extern BOOLEAN MiLargePageAllDrivers;
 425 extern ULONG MmVerifyDriverBufferLength;
 426 extern ULONG MmLargePageDriverBufferLength;
 427 extern SIZE_T MmSizeOfNonPagedPoolInBytes;
 428 extern SIZE_T MmMaximumNonPagedPoolInBytes;
 429 extern PFN_NUMBER MmMaximumNonPagedPoolInPages;
 430 extern PFN_NUMBER MmSizeOfPagedPoolInPages;
 431 extern PVOID MmNonPagedSystemStart;
 432 extern PVOID MmNonPagedPoolStart;
 433 extern PVOID MmNonPagedPoolExpansionStart;
 434 extern PVOID MmNonPagedPoolEnd;
 435 extern SIZE_T MmSizeOfPagedPoolInBytes;
 436 extern PVOID MmPagedPoolStart;
 437 extern PVOID MmPagedPoolEnd;
 438 extern PVOID MmSessionBase;
 439 extern SIZE_T MmSessionSize;
 440 extern PMMPTE MmFirstReservedMappingPte, MmLastReservedMappingPte;
 441 extern PMMPTE MiFirstReservedZeroingPte;
 442 extern MI_PFN_CACHE_ATTRIBUTE MiPlatformCacheAttributes[2][MmMaximumCacheType];
 443 extern PPHYSICAL_MEMORY_DESCRIPTOR MmPhysicalMemoryBlock;
 444 extern SIZE_T MmBootImageSize;
 445 extern PMMPTE MmSystemPtesStart[MaximumPtePoolTypes];
 446 extern PMMPTE MmSystemPtesEnd[MaximumPtePoolTypes];
 447 extern PMEMORY_ALLOCATION_DESCRIPTOR MxFreeDescriptor;
 448 extern MEMORY_ALLOCATION_DESCRIPTOR MxOldFreeDescriptor;
 449 extern ULONG_PTR MxPfnAllocation;
 450 extern MM_PAGED_POOL_INFO MmPagedPoolInfo;
 451 extern RTL_BITMAP MiPfnBitMap;
 452 extern KGUARDED_MUTEX MmPagedPoolMutex;
 453 extern PVOID MmPagedPoolStart;
 454 extern PVOID MmPagedPoolEnd;
 455 extern PVOID MmNonPagedSystemStart;
 456 extern PVOID MiSystemViewStart;
 457 extern SIZE_T MmSystemViewSize;
 458 extern PVOID MmSessionBase;
 459 extern PVOID MiSessionSpaceEnd;
 460 extern PMMPTE MiSessionImagePteStart;
 461 extern PMMPTE MiSessionImagePteEnd;
 462 extern PMMPTE MiSessionBasePte;
 463 extern PMMPTE MiSessionLastPte;
 464 extern SIZE_T MmSizeOfPagedPoolInBytes;
 465 extern PMMPTE MmSystemPagePtes;
 466 extern PVOID MmSystemCacheStart;
 467 extern PVOID MmSystemCacheEnd;
 468 extern MMSUPPORT MmSystemCacheWs;
 469 extern SIZE_T MmAllocatedNonPagedPool;
 470 extern ULONG_PTR MmSubsectionBase;
 471 extern ULONG MmSpecialPoolTag;
 472 extern PVOID MmHyperSpaceEnd;
 473 extern PMMWSL MmSystemCacheWorkingSetList;
 474 extern SIZE_T MmMinimumNonPagedPoolSize;
 475 extern ULONG MmMinAdditionNonPagedPoolPerMb;
 476 extern SIZE_T MmDefaultMaximumNonPagedPool;
 477 extern ULONG MmMaxAdditionNonPagedPoolPerMb;
 478 extern ULONG MmSecondaryColors;
 479 extern ULONG MmSecondaryColorMask;
 480 extern ULONG_PTR MmNumberOfSystemPtes;
 481 extern ULONG MmMaximumNonPagedPoolPercent;
 482 extern ULONG MmLargeStackSize;
 483 extern PMMCOLOR_TABLES MmFreePagesByColor[FreePageList + 1];
 484 extern ULONG MmProductType;
 485 extern MM_SYSTEMSIZE MmSystemSize;
 486 extern PKEVENT MiLowMemoryEvent;
 487 extern PKEVENT MiHighMemoryEvent;
 488 extern PKEVENT MiLowPagedPoolEvent;
 489 extern PKEVENT MiHighPagedPoolEvent;
 490 extern PKEVENT MiLowNonPagedPoolEvent;
 491 extern PKEVENT MiHighNonPagedPoolEvent;
 492 extern PFN_NUMBER MmLowMemoryThreshold;
 493 extern PFN_NUMBER MmHighMemoryThreshold;
 494 extern PFN_NUMBER MiLowPagedPoolThreshold;
 495 extern PFN_NUMBER MiHighPagedPoolThreshold;
 496 extern PFN_NUMBER MiLowNonPagedPoolThreshold;
 497 extern PFN_NUMBER MiHighNonPagedPoolThreshold;
 498 extern PFN_NUMBER MmMinimumFreePages;
 499 extern PFN_NUMBER MmPlentyFreePages;
 500 extern PFN_NUMBER MiExpansionPoolPagesInitialCharge;
 501 extern PFN_NUMBER MmResidentAvailablePages;
 502 extern PFN_NUMBER MmResidentAvailableAtInit;
 503 extern ULONG MmTotalFreeSystemPtes[MaximumPtePoolTypes];
 504 extern PFN_NUMBER MmTotalSystemDriverPages;
 505 extern PVOID MiSessionImageStart;
 506 extern PVOID MiSessionImageEnd;
 507 extern PMMPTE MiHighestUserPte;
 508 extern PMMPDE MiHighestUserPde;
 509 extern PFN_NUMBER MmSystemPageDirectory[PD_COUNT];
 510 extern PMMPTE MmSharedUserDataPte;
 511 extern LIST_ENTRY MmProcessList;
 512 extern BOOLEAN MmZeroingPageThreadActive;
 513 extern KEVENT MmZeroingPageEvent;
 514 extern ULONG MmSystemPageColor;
 515 extern ULONG MmProcessColorSeed;
 516
 517 //
 518 // Figures out the hardware bits for a PTE
 519 //
 520 ULONG
 521 FORCEINLINE
 522 MiDetermineUserGlobalPteMask(IN PMMPTE PointerPte)
 523 {
 524     MMPTE TempPte;
 525
 526     /* Start fresh */
 527     TempPte.u.Long = 0;
 528
 529     /* Make it valid and accessed */
 530     TempPte.u.Hard.Valid = TRUE;
 531     TempPte.u.Hard.Accessed = TRUE;
 532
 533     /* Is this for user-mode? */
 534     if ((PointerPte <= MiHighestUserPte) ||
 535         ((PointerPte >= MiAddressToPde(NULL)) && (PointerPte <= MiHighestUserPde)))
 536     {
 537         /* Set the owner bit */
 538         TempPte.u.Hard.Owner = TRUE;
 539     }
 540
 541     /* FIXME: We should also set the global bit */
 542
 543     /* Return the protection */
 544     return TempPte.u.Long;
 545 }
 546
 547 //
 548 // Creates a valid kernel PTE with the given protection
 549 //
 550 FORCEINLINE
 551 VOID
 552 MI_MAKE_HARDWARE_PTE_KERNEL(IN PMMPTE NewPte,
 553                             IN PMMPTE MappingPte,
 554                             IN ULONG ProtectionMask,
 555                             IN PFN_NUMBER PageFrameNumber)
 556 {
 557     /* Only valid for kernel, non-session PTEs */
 558     ASSERT(MappingPte > MiHighestUserPte);
 559     ASSERT(!MI_IS_SESSION_PTE(MappingPte));
 560     ASSERT((MappingPte < (PMMPTE)PDE_BASE) || (MappingPte > (PMMPTE)PDE_TOP));
 561
 562     /* Start fresh */
 563     *NewPte = ValidKernelPte;
 564
 565     /* Set the protection and page */
 566     NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
 567     NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
 568 }
 569
 570 //
 571 // Creates a valid PTE with the given protection
 572 //
 573 FORCEINLINE
 574 VOID
 575 MI_MAKE_HARDWARE_PTE(IN PMMPTE NewPte,
 576                      IN PMMPTE MappingPte,
 577                      IN ULONG ProtectionMask,
 578                      IN PFN_NUMBER PageFrameNumber)
 579 {
 580     /* Set the protection and page */
 581     NewPte->u.Long = MiDetermineUserGlobalPteMask(MappingPte);
 582     NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
 583     NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
 584 }
 585
 586 //
 587 // Creates a valid user PTE with the given protection
 588 //
 589 FORCEINLINE
 590 VOID
 591 MI_MAKE_HARDWARE_PTE_USER(IN PMMPTE NewPte,
 592                           IN PMMPTE MappingPte,
 593                           IN ULONG ProtectionMask,
 594                           IN PFN_NUMBER PageFrameNumber)
 595 {
 596     /* Only valid for kernel, non-session PTEs */
 597     ASSERT(MappingPte <= MiHighestUserPte);
 598
 599     /* Start fresh */
 600     *NewPte = ValidKernelPte;
 601
 602     /* Set the protection and page */
 603     NewPte->u.Hard.Owner = TRUE;
 604     NewPte->u.Hard.PageFrameNumber = PageFrameNumber;
 605     NewPte->u.Long |= MmProtectToPteMask[ProtectionMask];
 606 }
 607
 608 #ifdef _M_IX86
 609 //
 610 // Builds a Prototype PTE for the address of the PTE
 611 //
 612 FORCEINLINE
 613 VOID
 614 MI_MAKE_PROTOTYPE_PTE(IN PMMPTE NewPte,
 615                       IN PMMPTE PointerPte)
 616 {
 617     ULONG_PTR Offset;
 618
 619     /* Mark this as a prototype */
 620     NewPte->u.Long = 0;
 621     NewPte->u.Proto.Prototype = 1;
 622
 623     /*
 624      * Prototype PTEs are only valid in paged pool by design, this little trick
 625      * lets us only use 28 bits for the adress of the PTE
 626      */
 627     Offset = (ULONG_PTR)PointerPte - (ULONG_PTR)MmPagedPoolStart;
 628
 629     /* 7 bits go in the "low", and the other 21 bits go in the "high" */
 630     NewPte->u.Proto.ProtoAddressLow = Offset & 0x7F;
 631     NewPte->u.Proto.ProtoAddressHigh = Offset & 0xFFFFF80;
 632 }
 633 #endif
 634
 635 //
 636 // Returns if the page is physically resident (ie: a large page)
 637 // FIXFIX: CISC/x86 only?
 638 //
 639 FORCEINLINE
 640 BOOLEAN
 641 MI_IS_PHYSICAL_ADDRESS(IN PVOID Address)
 642 {
 643     PMMPDE PointerPde;
 644
 645     /* Large pages are never paged out, always physically resident */
 646     PointerPde = MiAddressToPde(Address);
 647     return ((PointerPde->u.Hard.LargePage) && (PointerPde->u.Hard.Valid));
 648 }
 649
 650 //
 651 // Writes a valid PTE
 652 //
 653 VOID
 654 FORCEINLINE
 655 MI_WRITE_VALID_PTE(IN PMMPTE PointerPte,
 656                    IN MMPTE TempPte)
 657 {
 658     /* Write the valid PTE */
 659     ASSERT(PointerPte->u.Hard.Valid == 0);
 660     ASSERT(TempPte.u.Hard.Valid == 1);
 661     *PointerPte = TempPte;
 662 }
 663
 664 //
 665 // Writes an invalid PTE
 666 //
 667 VOID
 668 FORCEINLINE
 669 MI_WRITE_INVALID_PTE(IN PMMPTE PointerPte,
 670                      IN MMPTE InvalidPte)
 671 {
 672     /* Write the invalid PTE */
 673     ASSERT(InvalidPte.u.Hard.Valid == 0);
 674     *PointerPte = InvalidPte;
 675 }
 676
 677 //
 678 // Checks if the thread already owns a working set
 679 //
 680 FORCEINLINE
 681 BOOLEAN
 682 MM_ANY_WS_LOCK_HELD(IN PETHREAD Thread)
 683 {
 684     /* If any of these are held, return TRUE */
 685     return ((Thread->OwnsProcessWorkingSetExclusive) ||
 686             (Thread->OwnsProcessWorkingSetShared) ||
 687             (Thread->OwnsSystemWorkingSetExclusive) ||
 688             (Thread->OwnsSystemWorkingSetShared) ||
 689             (Thread->OwnsSessionWorkingSetExclusive) ||
 690             (Thread->OwnsSessionWorkingSetShared));
 691 }
 692
 693 //
 694 // Checks if the process owns the working set lock
 695 //
 696 FORCEINLINE
 697 BOOLEAN
 698 MI_WS_OWNER(IN PEPROCESS Process)
 699 {
 700     /* Check if this process is the owner, and that the thread owns the WS */
 701     return ((KeGetCurrentThread()->ApcState.Process == &Process->Pcb) &&
 702             ((PsGetCurrentThread()->OwnsProcessWorkingSetExclusive) ||
 703              (PsGetCurrentThread()->OwnsProcessWorkingSetShared)));
 704 }
 705
 706 //
 707 // Locks the working set for the given process
 708 //
 709 FORCEINLINE
 710 VOID
 711 MiLockProcessWorkingSet(IN PEPROCESS Process,
 712                         IN PETHREAD Thread)
 713 {
 714     /* Shouldn't already be owning the process working set */
 715     ASSERT(Thread->OwnsProcessWorkingSetShared == FALSE);
 716     ASSERT(Thread->OwnsProcessWorkingSetExclusive == FALSE);
 717
 718     /* Block APCs, make sure that still nothing is already held */
 719     KeEnterGuardedRegion();
 720     ASSERT(!MM_ANY_WS_LOCK_HELD(Thread));
 721
 722     /* FIXME: Actually lock it (we can't because Vm is used by MAREAs) */
 723
 724     /* FIXME: This also can't be checked because Vm is used by MAREAs) */
 725     //ASSERT(Process->Vm.Flags.AcquiredUnsafe == 0);
 726
 727     /* Okay, now we can own it exclusively */
 728     ASSERT(Thread->OwnsProcessWorkingSetExclusive == FALSE);
 729     Thread->OwnsProcessWorkingSetExclusive = TRUE;
 730 }
 731
 732 //
 733 // Unlocks the working set for the given process
 734 //
 735 FORCEINLINE
 736 VOID
 737 MiUnlockProcessWorkingSet(IN PEPROCESS Process,
 738                           IN PETHREAD Thread)
 739 {
 740     /* Make sure this process really is owner, and it was a safe acquisition */
 741     ASSERT(MI_WS_OWNER(Process));
 742     /* This can't be checked because Vm is used by MAREAs) */
 743     //ASSERT(Process->Vm.Flags.AcquiredUnsafe == 0);
 744
 745     /* The thread doesn't own it anymore */
 746     ASSERT(Thread->OwnsProcessWorkingSetExclusive == TRUE);
 747     Thread->OwnsProcessWorkingSetExclusive = FALSE;
 748
 749     /* FIXME: Actually release it (we can't because Vm is used by MAREAs) */
 750
 751     /* Unblock APCs */
 752     KeLeaveGuardedRegion();
 753 }
 754
 755 //
 756 // Locks the working set
 757 //
 758 FORCEINLINE
 759 VOID
 760 MiLockWorkingSet(IN PETHREAD Thread,
 761                  IN PMMSUPPORT WorkingSet)
 762 {
 763     /* Block APCs */
 764     KeEnterGuardedRegion();
 765
 766     /* Working set should be in global memory */
 767     ASSERT(MI_IS_SESSION_ADDRESS((PVOID)WorkingSet) == FALSE);
 768
 769     /* Thread shouldn't already be owning something */
 770     ASSERT(!MM_ANY_WS_LOCK_HELD(Thread));
 771
 772     /* FIXME: Actually lock it (we can't because Vm is used by MAREAs) */
 773
 774     /* Which working set is this? */
 775     if (WorkingSet == &MmSystemCacheWs)
 776     {
 777         /* Own the system working set */
 778         ASSERT((Thread->OwnsSystemWorkingSetExclusive == FALSE) &&
 779                (Thread->OwnsSystemWorkingSetShared == FALSE));
 780         Thread->OwnsSystemWorkingSetExclusive = TRUE;
 781     }
 782     else if (WorkingSet->Flags.SessionSpace)
 783     {
 784         /* We don't implement this yet */
 785         UNIMPLEMENTED;
 786         while (TRUE);
 787     }
 788     else
 789     {
 790         /* Own the process working set */
 791         ASSERT((Thread->OwnsProcessWorkingSetExclusive == FALSE) &&
 792                (Thread->OwnsProcessWorkingSetShared == FALSE));
 793         Thread->OwnsProcessWorkingSetExclusive = TRUE;
 794     }
 795 }
 796
 797 //
 798 // Unlocks the working set
 799 //
 800 FORCEINLINE
 801 VOID
 802 MiUnlockWorkingSet(IN PETHREAD Thread,
 803                    IN PMMSUPPORT WorkingSet)
 804 {
 805     /* Working set should be in global memory */
 806     ASSERT(MI_IS_SESSION_ADDRESS((PVOID)WorkingSet) == FALSE);
 807
 808     /* Which working set is this? */
 809     if (WorkingSet == &MmSystemCacheWs)
 810     {
 811         /* Release the system working set */
 812         ASSERT((Thread->OwnsSystemWorkingSetExclusive == TRUE) ||
 813                (Thread->OwnsSystemWorkingSetShared == TRUE));
 814         Thread->OwnsSystemWorkingSetExclusive = FALSE;
 815     }
 816     else if (WorkingSet->Flags.SessionSpace)
 817     {
 818         /* We don't implement this yet */
 819         UNIMPLEMENTED;
 820         while (TRUE);
 821     }
 822     else
 823     {
 824         /* Release the process working set */
 825         ASSERT((Thread->OwnsProcessWorkingSetExclusive) ||
 826                (Thread->OwnsProcessWorkingSetShared));
 827         Thread->OwnsProcessWorkingSetExclusive = FALSE;
 828     }
 829
 830     /* FIXME: Actually release it (we can't because Vm is used by MAREAs) */
 831
 832     /* Unblock APCs */
 833     KeLeaveGuardedRegion();
 834 }
 835
 836 NTSTATUS
 837 NTAPI
 838 MmArmInitSystem(
 839     IN ULONG Phase,
 840     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 841 );
 842
 843 NTSTATUS
 844 NTAPI
 845 MiInitMachineDependent(
 846     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 847 );
 848
 849 VOID
 850 NTAPI
 851 MiComputeColorInformation(
 852     VOID
 853 );
 854
 855 VOID
 856 NTAPI
 857 MiMapPfnDatabase(
 858     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 859 );
 860
 861 VOID
 862 NTAPI
 863 MiInitializeColorTables(
 864     VOID
 865 );
 866
 867 VOID
 868 NTAPI
 869 MiInitializePfnDatabase(
 870     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 871 );
 872
 873 BOOLEAN
 874 NTAPI
 875 MiInitializeMemoryEvents(
 876     VOID
 877 );
 878
 879 PFN_NUMBER
 880 NTAPI
 881 MxGetNextPage(
 882     IN PFN_NUMBER PageCount
 883 );
 884
 885 PPHYSICAL_MEMORY_DESCRIPTOR
 886 NTAPI
 887 MmInitializeMemoryLimits(
 888     IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 889     IN PBOOLEAN IncludeType
 890 );
 891
 892 PFN_NUMBER
 893 NTAPI
 894 MiPagesInLoaderBlock(
 895     IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 896     IN PBOOLEAN IncludeType
 897 );
 898
 899 VOID
 900 FASTCALL
 901 MiSyncARM3WithROS(
 902     IN PVOID AddressStart,
 903     IN PVOID AddressEnd
 904 );
 905
 906 NTSTATUS
 907 NTAPI
 908 MmArmAccessFault(
 909     IN BOOLEAN StoreInstruction,
 910     IN PVOID Address,
 911     IN KPROCESSOR_MODE Mode,
 912     IN PVOID TrapInformation
 913 );
 914
 915 NTSTATUS
 916 FASTCALL
 917 MiCheckPdeForPagedPool(
 918     IN PVOID Address
 919 );
 920
 921 VOID
 922 NTAPI
 923 MiInitializeNonPagedPool(
 924     VOID
 925 );
 926
 927 VOID
 928 NTAPI
 929 MiInitializeNonPagedPoolThresholds(
 930     VOID
 931 );
 932
 933 VOID
 934 NTAPI
 935 MiInitializePoolEvents(
 936     VOID
 937 );
 938
 939 VOID                      //
 940 NTAPI                     //
 941 InitializePool(           //
 942     IN POOL_TYPE PoolType,// FIXFIX: This should go in ex.h after the pool merge
 943     IN ULONG Threshold    //
 944 );                        //
 945
 946 VOID
 947 NTAPI
 948 MiInitializeSystemPtes(
 949     IN PMMPTE StartingPte,
 950     IN ULONG NumberOfPtes,
 951     IN MMSYSTEM_PTE_POOL_TYPE PoolType
 952 );
 953
 954 PMMPTE
 955 NTAPI
 956 MiReserveSystemPtes(
 957     IN ULONG NumberOfPtes,
 958     IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType
 959 );
 960
 961 VOID
 962 NTAPI
 963 MiReleaseSystemPtes(
 964     IN PMMPTE StartingPte,
 965     IN ULONG NumberOfPtes,
 966     IN MMSYSTEM_PTE_POOL_TYPE SystemPtePoolType
 967 );
 968
 969
 970 PFN_NUMBER
 971 NTAPI
 972 MiFindContiguousPages(
 973     IN PFN_NUMBER LowestPfn,
 974     IN PFN_NUMBER HighestPfn,
 975     IN PFN_NUMBER BoundaryPfn,
 976     IN PFN_NUMBER SizeInPages,
 977     IN MEMORY_CACHING_TYPE CacheType
 978 );
 979
 980 PVOID
 981 NTAPI
 982 MiCheckForContiguousMemory(
 983     IN PVOID BaseAddress,
 984     IN PFN_NUMBER BaseAddressPages,
 985     IN PFN_NUMBER SizeInPages,
 986     IN PFN_NUMBER LowestPfn,
 987     IN PFN_NUMBER HighestPfn,
 988     IN PFN_NUMBER BoundaryPfn,
 989     IN MI_PFN_CACHE_ATTRIBUTE CacheAttribute
 990 );
 991
 992 PMDL
 993 NTAPI
 994 MiAllocatePagesForMdl(
 995     IN PHYSICAL_ADDRESS LowAddress,
 996     IN PHYSICAL_ADDRESS HighAddress,
 997     IN PHYSICAL_ADDRESS SkipBytes,
 998     IN SIZE_T TotalBytes,
 999     IN MI_PFN_CACHE_ATTRIBUTE CacheAttribute,
1000     IN ULONG Flags
1001 );
1002
1003 PVOID
1004 NTAPI
1005 MiMapLockedPagesInUserSpace(
1006     IN PMDL Mdl,
1007     IN PVOID BaseVa,
1008     IN MEMORY_CACHING_TYPE CacheType,
1009     IN PVOID BaseAddress
1010 );
1011
1012 VOID
1013 NTAPI
1014 MiUnmapLockedPagesInUserSpace(
1015     IN PVOID BaseAddress,
1016     IN PMDL Mdl
1017 );
1018
1019 VOID
1020 NTAPI
1021 MiInsertPageInList(
1022     IN PMMPFNLIST ListHead,
1023     IN PFN_NUMBER PageFrameIndex
1024 );
1025
1026 VOID
1027 NTAPI
1028 MiUnlinkFreeOrZeroedPage(
1029     IN PMMPFN Entry
1030 );
1031
1032 PFN_NUMBER
1033 NTAPI
1034 MiAllocatePfn(
1035     IN PMMPTE PointerPte,
1036     IN ULONG Protection
1037 );
1038
1039 VOID
1040 NTAPI
1041 MiInitializePfn(
1042     IN PFN_NUMBER PageFrameIndex,
1043     IN PMMPTE PointerPte,
1044     IN BOOLEAN Modified
1045 );
1046
1047 VOID
1048 NTAPI
1049 MiInitializePfnForOtherProcess(
1050     IN PFN_NUMBER PageFrameIndex,
1051     IN PMMPTE PointerPte,
1052     IN PFN_NUMBER PteFrame
1053 );
1054
1055 VOID
1056 NTAPI
1057 MiDecrementShareCount(
1058     IN PMMPFN Pfn1,
1059     IN PFN_NUMBER PageFrameIndex
1060 );
1061
1062 PFN_NUMBER
1063 NTAPI
1064 MiRemoveAnyPage(
1065     IN ULONG Color
1066 );
1067
1068 PFN_NUMBER
1069 NTAPI
1070 MiRemoveZeroPage(
1071     IN ULONG Color
1072 );
1073
1074 VOID
1075 NTAPI
1076 MiZeroPhysicalPage(
1077     IN PFN_NUMBER PageFrameIndex
1078 );
1079
1080 VOID
1081 NTAPI
1082 MiInsertPageInFreeList(
1083     IN PFN_NUMBER PageFrameIndex
1084 );
1085
1086 PFN_NUMBER
1087 NTAPI
1088 MiDeleteSystemPageableVm(
1089     IN PMMPTE PointerPte,
1090     IN PFN_NUMBER PageCount,
1091     IN ULONG Flags,
1092     OUT PPFN_NUMBER ValidPages
1093 );
1094
1095 PLDR_DATA_TABLE_ENTRY
1096 NTAPI
1097 MiLookupDataTableEntry(
1098     IN PVOID Address
1099 );
1100
1101 VOID
1102 NTAPI
1103 MiInitializeDriverLargePageList(
1104     VOID
1105 );
1106
1107 VOID
1108 NTAPI
1109 MiInitializeLargePageSupport(
1110     VOID
1111 );
1112
1113 VOID
1114 NTAPI
1115 MiSyncCachedRanges(
1116     VOID
1117 );
1118
1119 BOOLEAN
1120 NTAPI
1121 MiIsPfnInUse(
1122     IN PMMPFN Pfn1
1123 );
1124
1125 PMMVAD
1126 NTAPI
1127 MiLocateAddress(
1128     IN PVOID VirtualAddress
1129 );
1130
1131 PMMADDRESS_NODE
1132 NTAPI
1133 MiCheckForConflictingNode(
1134     IN ULONG_PTR StartVpn,
1135     IN ULONG_PTR EndVpn,
1136     IN PMM_AVL_TABLE Table
1137 );
1138
1139 TABLE_SEARCH_RESULT
1140 NTAPI
1141 MiFindEmptyAddressRangeDownTree(
1142     IN SIZE_T Length,
1143     IN ULONG_PTR BoundaryAddress,
1144     IN ULONG_PTR Alignment,
1145     IN PMM_AVL_TABLE Table,
1146     OUT PULONG_PTR Base,
1147     OUT PMMADDRESS_NODE *Parent
1148 );
1149
1150 NTSTATUS
1151 NTAPI
1152 MiFindEmptyAddressRangeInTree(
1153     IN SIZE_T Length,
1154     IN ULONG_PTR Alignment,
1155     IN PMM_AVL_TABLE Table,
1156     OUT PMMADDRESS_NODE *PreviousVad,
1157     OUT PULONG_PTR Base
1158 );
1159
1160 VOID
1161 NTAPI
1162 MiInsertVad(
1163     IN PMMVAD Vad,
1164     IN PEPROCESS Process
1165 );
1166
1167 VOID
1168 NTAPI
1169 MiInsertNode(
1170     IN PMM_AVL_TABLE Table,
1171     IN PMMADDRESS_NODE NewNode,
1172     PMMADDRESS_NODE Parent,
1173     TABLE_SEARCH_RESULT Result
1174 );
1175
1176 VOID
1177 NTAPI
1178 MiRemoveNode(
1179     IN PMMADDRESS_NODE Node,
1180     IN PMM_AVL_TABLE Table
1181 );
1182
1183 PMMADDRESS_NODE
1184 NTAPI
1185 MiGetPreviousNode(
1186     IN PMMADDRESS_NODE Node
1187 );
1188
1189 PMMADDRESS_NODE
1190 NTAPI
1191 MiGetNextNode(
1192     IN PMMADDRESS_NODE Node
1193 );
1194
1195 BOOLEAN
1196 NTAPI
1197 MiInitializeSystemSpaceMap(
1198     IN PVOID InputSession OPTIONAL
1199 );
1200
1201 ULONG
1202 NTAPI
1203 MiMakeProtectionMask(
1204     IN ULONG Protect
1205 );
1206
1207 //
1208 // MiRemoveZeroPage will use inline code to zero out the page manually if only
1209 // free pages are available. In some scenarios, we don't/can't run that piece of
1210 // code and would rather only have a real zero page. If we can't have a zero page,
1211 // then we'd like to have our own code to grab a free page and zero it out, by
1212 // using MiRemoveAnyPage. This macro implements this.
1213 //
1214 PFN_NUMBER
1215 FORCEINLINE
1216 MiRemoveZeroPageSafe(IN ULONG Color)
1217 {
1218     if (MmFreePagesByColor[ZeroedPageList][Color].Flink != LIST_HEAD) return MiRemoveZeroPage(Color);
1219     return 0;
1220 }
1221
1222 /* EOF */