2 * PROJECT: ReactOS Kernel
3 * LICENSE: BSD - See COPYING.ARM in the top level directory
4 * FILE: ntoskrnl/mm/ARM3/mminit.c
5 * PURPOSE: ARM Memory Manager Initialization
6 * PROGRAMMERS: ReactOS Portable Systems Group
9 /* INCLUDES *******************************************************************/
16 #define MODULE_INVOLVED_IN_ARM3
19 /* GLOBALS ********************************************************************/
22 // These are all registry-configurable, but by default, the memory manager will
23 // figure out the most appropriate values.
25 ULONG MmMaximumNonPagedPoolPercent
;
26 ULONG MmSizeOfNonPagedPoolInBytes
;
27 ULONG MmMaximumNonPagedPoolInBytes
;
29 /* Some of the same values, in pages */
30 PFN_NUMBER MmMaximumNonPagedPoolInPages
;
33 // These numbers describe the discrete equation components of the nonpaged
34 // pool sizing algorithm.
36 // They are described on http://support.microsoft.com/default.aspx/kb/126402/ja
37 // along with the algorithm that uses them, which is implemented later below.
39 ULONG MmMinimumNonPagedPoolSize
= 256 * 1024;
40 ULONG MmMinAdditionNonPagedPoolPerMb
= 32 * 1024;
41 ULONG MmDefaultMaximumNonPagedPool
= 1024 * 1024;
42 ULONG MmMaxAdditionNonPagedPoolPerMb
= 400 * 1024;
45 // The memory layout (and especially variable names) of the NT kernel mode
46 // components can be a bit hard to twig, especially when it comes to the non
49 // There are really two components to the non-paged pool:
51 // - The initial nonpaged pool, sized dynamically up to a maximum.
52 // - The expansion nonpaged pool, sized dynamically up to a maximum.
54 // The initial nonpaged pool is physically continuous for performance, and
55 // immediately follows the PFN database, typically sharing the same PDE. It is
56 // a very small resource (32MB on a 1GB system), and capped at 128MB.
58 // Right now we call this the "ARM³ Nonpaged Pool" and it begins somewhere after
59 // the PFN database (which starts at 0xB0000000).
61 // The expansion nonpaged pool, on the other hand, can grow much bigger (400MB
62 // for a 1GB system). On ARM³ however, it is currently capped at 128MB.
64 // The address where the initial nonpaged pool starts is aptly named
65 // MmNonPagedPoolStart, and it describes a range of MmSizeOfNonPagedPoolInBytes
68 // Expansion nonpaged pool starts at an address described by the variable called
69 // MmNonPagedPoolExpansionStart, and it goes on for MmMaximumNonPagedPoolInBytes
70 // minus MmSizeOfNonPagedPoolInBytes bytes, always reaching MmNonPagedPoolEnd
71 // (because of the way it's calculated) at 0xFFBE0000.
73 // Initial nonpaged pool is allocated and mapped early-on during boot, but what
74 // about the expansion nonpaged pool? It is instead composed of special pages
75 // which belong to what are called System PTEs. These PTEs are the matter of a
76 // later discussion, but they are also considered part of the "nonpaged" OS, due
77 // to the fact that they are never paged out -- once an address is described by
78 // a System PTE, it is always valid, until the System PTE is torn down.
80 // System PTEs are actually composed of two "spaces", the system space proper,
81 // and the nonpaged pool expansion space. The latter, as we've already seen,
82 // begins at MmNonPagedPoolExpansionStart. Based on the number of System PTEs
83 // that the system will support, the remaining address space below this address
84 // is used to hold the system space PTEs. This address, in turn, is held in the
85 // variable named MmNonPagedSystemStart, which itself is never allowed to go
86 // below 0xEB000000 (thus creating an upper bound on the number of System PTEs).
88 // This means that 330MB are reserved for total nonpaged system VA, on top of
89 // whatever the initial nonpaged pool allocation is.
91 // The following URLs, valid as of April 23rd, 2008, support this evidence:
93 // http://www.cs.miami.edu/~burt/journal/NT/memory.html
94 // http://www.ditii.com/2007/09/28/windows-memory-management-x86-virtual-address-space/
96 PVOID MmNonPagedSystemStart
;
97 PVOID MmNonPagedPoolStart
;
98 PVOID MmNonPagedPoolExpansionStart
;
99 PVOID MmNonPagedPoolEnd
= MI_NONPAGED_POOL_END
;
102 // This is where paged pool starts by default
104 PVOID MmPagedPoolStart
= MI_PAGED_POOL_START
;
105 PVOID MmPagedPoolEnd
;
108 // And this is its default size
110 ULONG MmSizeOfPagedPoolInBytes
= MI_MIN_INIT_PAGED_POOLSIZE
;
111 PFN_NUMBER MmSizeOfPagedPoolInPages
= MI_MIN_INIT_PAGED_POOLSIZE
/ PAGE_SIZE
;
114 // Session space starts at 0xBFFFFFFF and grows downwards
115 // By default, it includes an 8MB image area where we map win32k and video card
116 // drivers, followed by a 4MB area containing the session's working set. This is
117 // then followed by a 20MB mapped view area and finally by the session's paged
118 // pool, by default 16MB.
120 // On a normal system, this results in session space occupying the region from
121 // 0xBD000000 to 0xC0000000
123 // See miarm.h for the defines that determine the sizing of this region. On an
124 // NT system, some of these can be configured through the registry, but we don't
127 PVOID MiSessionSpaceEnd
; // 0xC0000000
128 PVOID MiSessionImageEnd
; // 0xC0000000
129 PVOID MiSessionImageStart
; // 0xBF800000
130 PVOID MiSessionViewStart
; // 0xBE000000
131 PVOID MiSessionPoolEnd
; // 0xBE000000
132 PVOID MiSessionPoolStart
; // 0xBD000000
133 PVOID MmSessionBase
; // 0xBD000000
135 ULONG MmSessionViewSize
;
136 ULONG MmSessionPoolSize
;
137 ULONG MmSessionImageSize
;
140 * These are the PTE addresses of the boundaries carved out above
142 PMMPTE MiSessionImagePteStart
;
143 PMMPTE MiSessionImagePteEnd
;
144 PMMPTE MiSessionBasePte
;
145 PMMPTE MiSessionLastPte
;
148 // The system view space, on the other hand, is where sections that are memory
149 // mapped into "system space" end up.
151 // By default, it is a 16MB region.
153 PVOID MiSystemViewStart
;
154 ULONG MmSystemViewSize
;
157 // A copy of the system page directory (the page directory associated with the
158 // System process) is kept (double-mapped) by the manager in order to lazily
159 // map paged pool PDEs into external processes when they fault on a paged pool
162 PFN_NUMBER MmSystemPageDirectory
[PD_COUNT
];
163 PMMPTE MmSystemPagePtes
;
166 // The system cache starts right after hyperspace. The first few pages are for
167 // keeping track of the system working set list.
169 // This should be 0xC0C00000 -- the cache itself starts at 0xC1000000
171 PMMWSL MmSystemCacheWorkingSetList
= MI_SYSTEM_CACHE_WS_START
;
174 // Windows NT seems to choose between 7000, 11000 and 50000
175 // On systems with more than 32MB, this number is then doubled, and further
176 // aligned up to a PDE boundary (4MB).
178 ULONG MmNumberOfSystemPtes
;
181 // This is how many pages the PFN database will take up
182 // In Windows, this includes the Quark Color Table, but not in ARM³
184 ULONG MxPfnAllocation
;
187 // Unlike the old ReactOS Memory Manager, ARM³ (and Windows) does not keep track
188 // of pages that are not actually valid physical memory, such as ACPI reserved
189 // regions, BIOS address ranges, or holes in physical memory address space which
190 // could indicate device-mapped I/O memory.
192 // In fact, the lack of a PFN entry for a page usually indicates that this is
193 // I/O space instead.
195 // A bitmap, called the PFN bitmap, keeps track of all page frames by assigning
196 // a bit to each. If the bit is set, then the page is valid physical RAM.
198 RTL_BITMAP MiPfnBitMap
;
201 // This structure describes the different pieces of RAM-backed address space
203 PPHYSICAL_MEMORY_DESCRIPTOR MmPhysicalMemoryBlock
;
206 // This is where we keep track of the most basic physical layout markers
208 ULONG MmNumberOfPhysicalPages
, MmHighestPhysicalPage
, MmLowestPhysicalPage
= -1;
211 // The total number of pages mapped by the boot loader, which include the kernel
212 // HAL, boot drivers, registry, NLS files and other loader data structures is
213 // kept track of here. This depends on "LoaderPagesSpanned" being correct when
214 // coming from the loader.
216 // This number is later aligned up to a PDE boundary.
218 ULONG MmBootImageSize
;
221 // These three variables keep track of the core separation of address space that
222 // exists between kernel mode and user mode.
224 ULONG MmUserProbeAddress
;
225 PVOID MmHighestUserAddress
;
226 PVOID MmSystemRangeStart
;
228 /* And these store the respective highest PTE/PDE address */
229 PMMPTE MiHighestUserPte
;
230 PMMPDE MiHighestUserPde
;
232 /* These variables define the system cache address space */
233 PVOID MmSystemCacheStart
;
234 PVOID MmSystemCacheEnd
;
235 MMSUPPORT MmSystemCacheWs
;
238 // This is where hyperspace ends (followed by the system cache working set)
240 PVOID MmHyperSpaceEnd
;
243 // Page coloring algorithm data
245 ULONG MmSecondaryColors
;
246 ULONG MmSecondaryColorMask
;
249 // Actual (registry-configurable) size of a GUI thread's stack
251 ULONG MmLargeStackSize
= KERNEL_LARGE_STACK_SIZE
;
254 // Before we have a PFN database, memory comes straight from our physical memory
255 // blocks, which is nice because it's guaranteed contiguous and also because once
256 // we take a page from here, the system doesn't see it anymore.
257 // However, once the fun is over, those pages must be re-integrated back into
258 // PFN society life, and that requires us keeping a copy of the original layout
259 // so that we can parse it later.
261 PMEMORY_ALLOCATION_DESCRIPTOR MxFreeDescriptor
;
262 MEMORY_ALLOCATION_DESCRIPTOR MxOldFreeDescriptor
;
265 * For each page's worth bytes of L2 cache in a given set/way line, the zero and
266 * free lists are organized in what is called a "color".
268 * This array points to the two lists, so it can be thought of as a multi-dimensional
269 * array of MmFreePagesByColor[2][MmSecondaryColors]. Since the number is dynamic,
270 * we describe the array in pointer form instead.
272 * On a final note, the color tables themselves are right after the PFN database.
274 C_ASSERT(FreePageList
== 1);
275 PMMCOLOR_TABLES MmFreePagesByColor
[FreePageList
+ 1];
277 /* An event used in Phase 0 before the rest of the system is ready to go */
280 /* All the events used for memory threshold notifications */
281 PKEVENT MiLowMemoryEvent
;
282 PKEVENT MiHighMemoryEvent
;
283 PKEVENT MiLowPagedPoolEvent
;
284 PKEVENT MiHighPagedPoolEvent
;
285 PKEVENT MiLowNonPagedPoolEvent
;
286 PKEVENT MiHighNonPagedPoolEvent
;
288 /* The actual thresholds themselves, in page numbers */
289 PFN_NUMBER MmLowMemoryThreshold
;
290 PFN_NUMBER MmHighMemoryThreshold
;
291 PFN_NUMBER MiLowPagedPoolThreshold
;
292 PFN_NUMBER MiHighPagedPoolThreshold
;
293 PFN_NUMBER MiLowNonPagedPoolThreshold
;
294 PFN_NUMBER MiHighNonPagedPoolThreshold
;
297 * This number determines how many free pages must exist, at minimum, until we
298 * start trimming working sets and flushing modified pages to obtain more free
301 * This number changes if the system detects that this is a server product
303 PFN_NUMBER MmMinimumFreePages
= 26;
306 * This number indicates how many pages we consider to be a low limit of having
307 * "plenty" of free memory.
309 * It is doubled on systems that have more than 63MB of memory
311 PFN_NUMBER MmPlentyFreePages
= 400;
313 /* These values store the type of system this is (small, med, large) and if server */
315 MM_SYSTEMSIZE MmSystemSize
;
318 * These values store the cache working set minimums and maximums, in pages
320 * The minimum value is boosted on systems with more than 24MB of RAM, and cut
321 * down to only 32 pages on embedded (<24MB RAM) systems.
323 * An extra boost of 2MB is given on systems with more than 33MB of RAM.
325 PFN_NUMBER MmSystemCacheWsMinimum
= 288;
326 PFN_NUMBER MmSystemCacheWsMaximum
= 350;
328 /* FIXME: Move to cache/working set code later */
329 BOOLEAN MmLargeSystemCache
;
331 /* PRIVATE FUNCTIONS **********************************************************/
334 // In Bavaria, this is probably a hate crime
338 MiSyncARM3WithROS(IN PVOID AddressStart
,
342 // Puerile piece of junk-grade carbonized horseshit puss sold to the lowest bidder
344 ULONG Pde
= ADDR_TO_PDE_OFFSET(AddressStart
);
345 while (Pde
<= ADDR_TO_PDE_OFFSET(AddressEnd
))
348 // This both odious and heinous
350 extern ULONG MmGlobalKernelPageDirectory
[1024];
351 MmGlobalKernelPageDirectory
[Pde
] = ((PULONG
)PDE_BASE
)[Pde
];
358 MxGetNextPage(IN PFN_NUMBER PageCount
)
362 /* Make sure we have enough pages */
363 if (PageCount
> MxFreeDescriptor
->PageCount
)
365 /* Crash the system */
366 KeBugCheckEx(INSTALL_MORE_MEMORY
,
367 MmNumberOfPhysicalPages
,
368 MxFreeDescriptor
->PageCount
,
369 MxOldFreeDescriptor
.PageCount
,
373 /* Use our lowest usable free pages */
374 Pfn
= MxFreeDescriptor
->BasePage
;
375 MxFreeDescriptor
->BasePage
+= PageCount
;
376 MxFreeDescriptor
->PageCount
-= PageCount
;
382 MiComputeColorInformation(VOID
)
384 ULONG L2Associativity
;
386 /* Check if no setting was provided already */
387 if (!MmSecondaryColors
)
389 /* Get L2 cache information */
390 L2Associativity
= KeGetPcr()->SecondLevelCacheAssociativity
;
392 /* The number of colors is the number of cache bytes by set/way */
393 MmSecondaryColors
= KeGetPcr()->SecondLevelCacheSize
;
394 if (L2Associativity
) MmSecondaryColors
/= L2Associativity
;
397 /* Now convert cache bytes into pages */
398 MmSecondaryColors
>>= PAGE_SHIFT
;
399 if (!MmSecondaryColors
)
401 /* If there was no cache data from the KPCR, use the default colors */
402 MmSecondaryColors
= MI_SECONDARY_COLORS
;
406 /* Otherwise, make sure there aren't too many colors */
407 if (MmSecondaryColors
> MI_MAX_SECONDARY_COLORS
)
409 /* Set the maximum */
410 MmSecondaryColors
= MI_MAX_SECONDARY_COLORS
;
413 /* Make sure there aren't too little colors */
414 if (MmSecondaryColors
< MI_MIN_SECONDARY_COLORS
)
416 /* Set the default */
417 MmSecondaryColors
= MI_SECONDARY_COLORS
;
420 /* Finally make sure the colors are a power of two */
421 if (MmSecondaryColors
& (MmSecondaryColors
- 1))
423 /* Set the default */
424 MmSecondaryColors
= MI_SECONDARY_COLORS
;
428 /* Compute the mask and store it */
429 MmSecondaryColorMask
= MmSecondaryColors
- 1;
430 KeGetCurrentPrcb()->SecondaryColorMask
= MmSecondaryColorMask
;
435 MiInitializeColorTables(VOID
)
438 PMMPTE PointerPte
, LastPte
;
439 MMPTE TempPte
= ValidKernelPte
;
441 /* The color table starts after the ARM3 PFN database */
442 MmFreePagesByColor
[0] = (PMMCOLOR_TABLES
)&MmPfnDatabase
[MmHighestPhysicalPage
+ 1];
444 /* Loop the PTEs. We have two color tables for each secondary color */
445 PointerPte
= MiAddressToPte(&MmFreePagesByColor
[0][0]);
446 LastPte
= MiAddressToPte((ULONG_PTR
)MmFreePagesByColor
[0] +
447 (2 * MmSecondaryColors
* sizeof(MMCOLOR_TABLES
))
449 while (PointerPte
<= LastPte
)
451 /* Check for valid PTE */
452 if (PointerPte
->u
.Hard
.Valid
== 0)
454 /* Get a page and map it */
455 TempPte
.u
.Hard
.PageFrameNumber
= MxGetNextPage(1);
456 MI_WRITE_VALID_PTE(PointerPte
, TempPte
);
458 /* Zero out the page */
459 RtlZeroMemory(MiPteToAddress(PointerPte
), PAGE_SIZE
);
466 /* Now set the address of the next list, right after this one */
467 MmFreePagesByColor
[1] = &MmFreePagesByColor
[0][MmSecondaryColors
];
469 /* Now loop the lists to set them up */
470 for (i
= 0; i
< MmSecondaryColors
; i
++)
472 /* Set both free and zero lists for each color */
473 MmFreePagesByColor
[ZeroedPageList
][i
].Flink
= 0xFFFFFFFF;
474 MmFreePagesByColor
[ZeroedPageList
][i
].Blink
= (PVOID
)0xFFFFFFFF;
475 MmFreePagesByColor
[ZeroedPageList
][i
].Count
= 0;
476 MmFreePagesByColor
[FreePageList
][i
].Flink
= 0xFFFFFFFF;
477 MmFreePagesByColor
[FreePageList
][i
].Blink
= (PVOID
)0xFFFFFFFF;
478 MmFreePagesByColor
[FreePageList
][i
].Count
= 0;
484 MiIsRegularMemory(IN PLOADER_PARAMETER_BLOCK LoaderBlock
,
487 PLIST_ENTRY NextEntry
;
488 PMEMORY_ALLOCATION_DESCRIPTOR MdBlock
;
490 /* Loop the memory descriptors */
491 NextEntry
= LoaderBlock
->MemoryDescriptorListHead
.Flink
;
492 while (NextEntry
!= &LoaderBlock
->MemoryDescriptorListHead
)
494 /* Get the memory descriptor */
495 MdBlock
= CONTAINING_RECORD(NextEntry
,
496 MEMORY_ALLOCATION_DESCRIPTOR
,
499 /* Check if this PFN could be part of the block */
500 if (Pfn
>= (MdBlock
->BasePage
))
502 /* Check if it really is part of the block */
503 if (Pfn
< (MdBlock
->BasePage
+ MdBlock
->PageCount
))
505 /* Check if the block is actually memory we don't map */
506 if ((MdBlock
->MemoryType
== LoaderFirmwarePermanent
) ||
507 (MdBlock
->MemoryType
== LoaderBBTMemory
) ||
508 (MdBlock
->MemoryType
== LoaderSpecialMemory
))
510 /* We don't need PFN database entries for this memory */
514 /* This is memory we want to map */
520 /* Blocks are ordered, so if it's not here, it doesn't exist */
524 /* Get to the next descriptor */
525 NextEntry
= MdBlock
->ListEntry
.Flink
;
528 /* Check if this PFN is actually from our free memory descriptor */
529 if ((Pfn
>= MxOldFreeDescriptor
.BasePage
) &&
530 (Pfn
< MxOldFreeDescriptor
.BasePage
+ MxOldFreeDescriptor
.PageCount
))
532 /* We use these pages for initial mappings, so we do want to count them */
536 /* Otherwise this isn't memory that we describe or care about */
542 MiMapPfnDatabase(IN PLOADER_PARAMETER_BLOCK LoaderBlock
)
544 ULONG FreePage
, FreePageCount
, PagesLeft
, BasePage
, PageCount
;
545 PLIST_ENTRY NextEntry
;
546 PMEMORY_ALLOCATION_DESCRIPTOR MdBlock
;
547 PMMPTE PointerPte
, LastPte
;
548 MMPTE TempPte
= ValidKernelPte
;
550 /* Get current page data, since we won't be using MxGetNextPage as it would corrupt our state */
551 FreePage
= MxFreeDescriptor
->BasePage
;
552 FreePageCount
= MxFreeDescriptor
->PageCount
;
555 /* Loop the memory descriptors */
556 NextEntry
= LoaderBlock
->MemoryDescriptorListHead
.Flink
;
557 while (NextEntry
!= &LoaderBlock
->MemoryDescriptorListHead
)
559 /* Get the descriptor */
560 MdBlock
= CONTAINING_RECORD(NextEntry
,
561 MEMORY_ALLOCATION_DESCRIPTOR
,
563 if ((MdBlock
->MemoryType
== LoaderFirmwarePermanent
) ||
564 (MdBlock
->MemoryType
== LoaderBBTMemory
) ||
565 (MdBlock
->MemoryType
== LoaderSpecialMemory
))
567 /* These pages are not part of the PFN database */
568 NextEntry
= MdBlock
->ListEntry
.Flink
;
572 /* Next, check if this is our special free descriptor we've found */
573 if (MdBlock
== MxFreeDescriptor
)
575 /* Use the real numbers instead */
576 BasePage
= MxOldFreeDescriptor
.BasePage
;
577 PageCount
= MxOldFreeDescriptor
.PageCount
;
581 /* Use the descriptor's numbers */
582 BasePage
= MdBlock
->BasePage
;
583 PageCount
= MdBlock
->PageCount
;
586 /* Get the PTEs for this range */
587 PointerPte
= MiAddressToPte(&MmPfnDatabase
[BasePage
]);
588 LastPte
= MiAddressToPte(((ULONG_PTR
)&MmPfnDatabase
[BasePage
+ PageCount
]) - 1);
589 DPRINT("MD Type: %lx Base: %lx Count: %lx\n", MdBlock
->MemoryType
, BasePage
, PageCount
);
592 while (PointerPte
<= LastPte
)
594 /* We'll only touch PTEs that aren't already valid */
595 if (PointerPte
->u
.Hard
.Valid
== 0)
597 /* Use the next free page */
598 TempPte
.u
.Hard
.PageFrameNumber
= FreePage
;
599 ASSERT(FreePageCount
!= 0);
601 /* Consume free pages */
607 KeBugCheckEx(INSTALL_MORE_MEMORY
,
608 MmNumberOfPhysicalPages
,
610 MxOldFreeDescriptor
.PageCount
,
614 /* Write out this PTE */
616 MI_WRITE_VALID_PTE(PointerPte
, TempPte
);
619 RtlZeroMemory(MiPteToAddress(PointerPte
), PAGE_SIZE
);
626 /* Do the next address range */
627 NextEntry
= MdBlock
->ListEntry
.Flink
;
630 /* Now update the free descriptors to consume the pages we used up during the PFN allocation loop */
631 MxFreeDescriptor
->BasePage
= FreePage
;
632 MxFreeDescriptor
->PageCount
= FreePageCount
;
637 MiBuildPfnDatabaseFromPages(IN PLOADER_PARAMETER_BLOCK LoaderBlock
)
642 PFN_NUMBER PageFrameIndex
, StartupPdIndex
, PtePageIndex
;
644 ULONG_PTR BaseAddress
= 0;
646 /* PFN of the startup page directory */
647 StartupPdIndex
= PFN_FROM_PTE(MiAddressToPde(PDE_BASE
));
649 /* Start with the first PDE and scan them all */
650 PointerPde
= MiAddressToPde(NULL
);
651 Count
= PD_COUNT
* PDE_COUNT
;
652 for (i
= 0; i
< Count
; i
++)
654 /* Check for valid PDE */
655 if (PointerPde
->u
.Hard
.Valid
== 1)
657 /* Get the PFN from it */
658 PageFrameIndex
= PFN_FROM_PTE(PointerPde
);
660 /* Do we want a PFN entry for this page? */
661 if (MiIsRegularMemory(LoaderBlock
, PageFrameIndex
))
663 /* Yes we do, set it up */
664 Pfn1
= MiGetPfnEntry(PageFrameIndex
);
665 Pfn1
->u4
.PteFrame
= StartupPdIndex
;
666 Pfn1
->PteAddress
= PointerPde
;
667 Pfn1
->u2
.ShareCount
++;
668 Pfn1
->u3
.e2
.ReferenceCount
= 1;
669 Pfn1
->u3
.e1
.PageLocation
= ActiveAndValid
;
670 Pfn1
->u3
.e1
.CacheAttribute
= MiNonCached
;
678 /* Now get the PTE and scan the pages */
679 PointerPte
= MiAddressToPte(BaseAddress
);
680 for (j
= 0; j
< PTE_COUNT
; j
++)
682 /* Check for a valid PTE */
683 if (PointerPte
->u
.Hard
.Valid
== 1)
685 /* Increase the shared count of the PFN entry for the PDE */
686 ASSERT(Pfn1
!= NULL
);
687 Pfn1
->u2
.ShareCount
++;
689 /* Now check if the PTE is valid memory too */
690 PtePageIndex
= PFN_FROM_PTE(PointerPte
);
691 if (MiIsRegularMemory(LoaderBlock
, PtePageIndex
))
694 * Only add pages above the end of system code or pages
695 * that are part of nonpaged pool
697 if ((BaseAddress
>= 0xA0000000) ||
698 ((BaseAddress
>= (ULONG_PTR
)MmNonPagedPoolStart
) &&
699 (BaseAddress
< (ULONG_PTR
)MmNonPagedPoolStart
+
700 MmSizeOfNonPagedPoolInBytes
)))
702 /* Get the PFN entry and make sure it too is valid */
703 Pfn2
= MiGetPfnEntry(PtePageIndex
);
704 if ((MmIsAddressValid(Pfn2
)) &&
705 (MmIsAddressValid(Pfn2
+ 1)))
707 /* Setup the PFN entry */
708 Pfn2
->u4
.PteFrame
= PageFrameIndex
;
709 Pfn2
->PteAddress
= PointerPte
;
710 Pfn2
->u2
.ShareCount
++;
711 Pfn2
->u3
.e2
.ReferenceCount
= 1;
712 Pfn2
->u3
.e1
.PageLocation
= ActiveAndValid
;
713 Pfn2
->u3
.e1
.CacheAttribute
= MiNonCached
;
721 BaseAddress
+= PAGE_SIZE
;
726 /* Next PDE mapped address */
727 BaseAddress
+= PDE_MAPPED_VA
;
737 MiBuildPfnDatabaseZeroPage(VOID
)
742 /* Grab the lowest page and check if it has no real references */
743 Pfn1
= MiGetPfnEntry(MmLowestPhysicalPage
);
744 if (!(MmLowestPhysicalPage
) && !(Pfn1
->u3
.e2
.ReferenceCount
))
746 /* Make it a bogus page to catch errors */
747 PointerPde
= MiAddressToPde(0xFFFFFFFF);
748 Pfn1
->u4
.PteFrame
= PFN_FROM_PTE(PointerPde
);
749 Pfn1
->PteAddress
= PointerPde
;
750 Pfn1
->u2
.ShareCount
++;
751 Pfn1
->u3
.e2
.ReferenceCount
= 0xFFF0;
752 Pfn1
->u3
.e1
.PageLocation
= ActiveAndValid
;
753 Pfn1
->u3
.e1
.CacheAttribute
= MiNonCached
;
759 MiBuildPfnDatabaseFromLoaderBlock(IN PLOADER_PARAMETER_BLOCK LoaderBlock
)
761 PLIST_ENTRY NextEntry
;
762 PFN_NUMBER PageCount
= 0;
763 PMEMORY_ALLOCATION_DESCRIPTOR MdBlock
;
764 PFN_NUMBER PageFrameIndex
;
770 /* Now loop through the descriptors */
771 NextEntry
= LoaderBlock
->MemoryDescriptorListHead
.Flink
;
772 while (NextEntry
!= &LoaderBlock
->MemoryDescriptorListHead
)
774 /* Get the current descriptor */
775 MdBlock
= CONTAINING_RECORD(NextEntry
,
776 MEMORY_ALLOCATION_DESCRIPTOR
,
780 PageCount
= MdBlock
->PageCount
;
781 PageFrameIndex
= MdBlock
->BasePage
;
783 /* Don't allow memory above what the PFN database is mapping */
784 if (PageFrameIndex
> MmHighestPhysicalPage
)
786 /* Since they are ordered, everything past here will be larger */
790 /* On the other hand, the end page might be higher up... */
791 if ((PageFrameIndex
+ PageCount
) > (MmHighestPhysicalPage
+ 1))
793 /* In which case we'll trim the descriptor to go as high as we can */
794 PageCount
= MmHighestPhysicalPage
+ 1 - PageFrameIndex
;
795 MdBlock
->PageCount
= PageCount
;
797 /* But if there's nothing left to trim, we got too high, so quit */
798 if (!PageCount
) break;
801 /* Now check the descriptor type */
802 switch (MdBlock
->MemoryType
)
804 /* Check for bad RAM */
807 DPRINT1("You have damaged RAM modules. Stopping boot\n");
811 /* Check for free RAM */
813 case LoaderLoadedProgram
:
814 case LoaderFirmwareTemporary
:
815 case LoaderOsloaderStack
:
817 /* Get the last page of this descriptor. Note we loop backwards */
818 PageFrameIndex
+= PageCount
- 1;
819 Pfn1
= MiGetPfnEntry(PageFrameIndex
);
821 /* Lock the PFN Database */
822 OldIrql
= KeAcquireQueuedSpinLock(LockQueuePfnLock
);
825 /* If the page really has no references, mark it as free */
826 if (!Pfn1
->u3
.e2
.ReferenceCount
)
828 /* Add it to the free list */
829 Pfn1
->u3
.e1
.CacheAttribute
= MiNonCached
;
830 MiInsertPageInFreeList(PageFrameIndex
);
833 /* Go to the next page */
838 /* Release PFN database */
839 KeReleaseQueuedSpinLock(LockQueuePfnLock
, OldIrql
);
841 /* Done with this block */
844 /* Check for pages that are invisible to us */
845 case LoaderFirmwarePermanent
:
846 case LoaderSpecialMemory
:
847 case LoaderBBTMemory
:
854 /* Map these pages with the KSEG0 mapping that adds 0x80000000 */
855 PointerPte
= MiAddressToPte(KSEG0_BASE
+ (PageFrameIndex
<< PAGE_SHIFT
));
856 Pfn1
= MiGetPfnEntry(PageFrameIndex
);
859 /* Check if the page is really unused */
860 PointerPde
= MiAddressToPde(KSEG0_BASE
+ (PageFrameIndex
<< PAGE_SHIFT
));
861 if (!Pfn1
->u3
.e2
.ReferenceCount
)
863 /* Mark it as being in-use */
864 Pfn1
->u4
.PteFrame
= PFN_FROM_PTE(PointerPde
);
865 Pfn1
->PteAddress
= PointerPte
;
866 Pfn1
->u2
.ShareCount
++;
867 Pfn1
->u3
.e2
.ReferenceCount
= 1;
868 Pfn1
->u3
.e1
.PageLocation
= ActiveAndValid
;
869 Pfn1
->u3
.e1
.CacheAttribute
= MiNonCached
;
871 /* Check for RAM disk page */
872 if (MdBlock
->MemoryType
== LoaderXIPRom
)
874 /* Make it a pseudo-I/O ROM mapping */
876 Pfn1
->u2
.ShareCount
= 0;
877 Pfn1
->u3
.e2
.ReferenceCount
= 0;
878 Pfn1
->u3
.e1
.PageLocation
= 0;
880 Pfn1
->u4
.InPageError
= 0;
881 Pfn1
->u3
.e1
.PrototypePte
= 1;
885 /* Advance page structures */
893 /* Next descriptor entry */
894 NextEntry
= MdBlock
->ListEntry
.Flink
;
900 MiBuildPfnDatabaseSelf(VOID
)
902 PMMPTE PointerPte
, LastPte
;
905 /* Loop the PFN database page */
906 PointerPte
= MiAddressToPte(MiGetPfnEntry(MmLowestPhysicalPage
));
907 LastPte
= MiAddressToPte(MiGetPfnEntry(MmHighestPhysicalPage
));
908 while (PointerPte
<= LastPte
)
910 /* Make sure the page is valid */
911 if (PointerPte
->u
.Hard
.Valid
== 1)
913 /* Get the PFN entry and just mark it referenced */
914 Pfn1
= MiGetPfnEntry(PointerPte
->u
.Hard
.PageFrameNumber
);
915 Pfn1
->u2
.ShareCount
= 1;
916 Pfn1
->u3
.e2
.ReferenceCount
= 1;
926 MiInitializePfnDatabase(IN PLOADER_PARAMETER_BLOCK LoaderBlock
)
928 /* Scan memory and start setting up PFN entries */
929 MiBuildPfnDatabaseFromPages(LoaderBlock
);
931 /* Add the zero page */
932 MiBuildPfnDatabaseZeroPage();
934 /* Scan the loader block and build the rest of the PFN database */
935 MiBuildPfnDatabaseFromLoaderBlock(LoaderBlock
);
937 /* Finally add the pages for the PFN database itself */
938 MiBuildPfnDatabaseSelf();
943 MiAdjustWorkingSetManagerParameters(IN BOOLEAN Client
)
945 /* This function needs to do more work, for now, we tune page minimums */
947 /* Check for a system with around 64MB RAM or more */
948 if (MmNumberOfPhysicalPages
>= (63 * _1MB
) / PAGE_SIZE
)
950 /* Double the minimum amount of pages we consider for a "plenty free" scenario */
951 MmPlentyFreePages
*= 2;
957 MiNotifyMemoryEvents(VOID
)
959 /* Are we in a low-memory situation? */
960 if (MmAvailablePages
< MmLowMemoryThreshold
)
962 /* Clear high, set low */
963 if (KeReadStateEvent(MiHighMemoryEvent
)) KeClearEvent(MiHighMemoryEvent
);
964 if (!KeReadStateEvent(MiLowMemoryEvent
)) KeSetEvent(MiLowMemoryEvent
, 0, FALSE
);
966 else if (MmAvailablePages
< MmHighMemoryThreshold
)
968 /* We are in between, clear both */
969 if (KeReadStateEvent(MiHighMemoryEvent
)) KeClearEvent(MiHighMemoryEvent
);
970 if (KeReadStateEvent(MiLowMemoryEvent
)) KeClearEvent(MiLowMemoryEvent
);
974 /* Clear low, set high */
975 if (KeReadStateEvent(MiLowMemoryEvent
)) KeClearEvent(MiLowMemoryEvent
);
976 if (!KeReadStateEvent(MiHighMemoryEvent
)) KeSetEvent(MiHighMemoryEvent
, 0, FALSE
);
982 MiCreateMemoryEvent(IN PUNICODE_STRING Name
,
989 OBJECT_ATTRIBUTES ObjectAttributes
;
990 SECURITY_DESCRIPTOR SecurityDescriptor
;
993 Status
= RtlCreateSecurityDescriptor(&SecurityDescriptor
,
994 SECURITY_DESCRIPTOR_REVISION
);
995 if (!NT_SUCCESS(Status
)) return Status
;
997 /* One ACL with 3 ACEs, containing each one SID */
998 DaclLength
= sizeof(ACL
) +
999 3 * sizeof(ACCESS_ALLOWED_ACE
) +
1000 RtlLengthSid(SeLocalSystemSid
) +
1001 RtlLengthSid(SeAliasAdminsSid
) +
1002 RtlLengthSid(SeWorldSid
);
1004 /* Allocate space for the DACL */
1005 Dacl
= ExAllocatePoolWithTag(PagedPool
, DaclLength
, 'lcaD');
1006 if (!Dacl
) return STATUS_INSUFFICIENT_RESOURCES
;
1008 /* Setup the ACL inside it */
1009 Status
= RtlCreateAcl(Dacl
, DaclLength
, ACL_REVISION
);
1010 if (!NT_SUCCESS(Status
)) goto CleanUp
;
1012 /* Add query rights for everyone */
1013 Status
= RtlAddAccessAllowedAce(Dacl
,
1015 SYNCHRONIZE
| EVENT_QUERY_STATE
| READ_CONTROL
,
1017 if (!NT_SUCCESS(Status
)) goto CleanUp
;
1019 /* Full rights for the admin */
1020 Status
= RtlAddAccessAllowedAce(Dacl
,
1024 if (!NT_SUCCESS(Status
)) goto CleanUp
;
1026 /* As well as full rights for the system */
1027 Status
= RtlAddAccessAllowedAce(Dacl
,
1031 if (!NT_SUCCESS(Status
)) goto CleanUp
;
1033 /* Set this DACL inside the SD */
1034 Status
= RtlSetDaclSecurityDescriptor(&SecurityDescriptor
,
1038 if (!NT_SUCCESS(Status
)) goto CleanUp
;
1040 /* Setup the event attributes, making sure it's a permanent one */
1041 InitializeObjectAttributes(&ObjectAttributes
,
1043 OBJ_KERNEL_HANDLE
| OBJ_PERMANENT
,
1045 &SecurityDescriptor
);
1047 /* Create the event */
1048 Status
= ZwCreateEvent(&EventHandle
,
1057 /* Check if this is the success path */
1058 if (NT_SUCCESS(Status
))
1060 /* Add a reference to the object, then close the handle we had */
1061 Status
= ObReferenceObjectByHandle(EventHandle
,
1067 ZwClose (EventHandle
);
1076 MiInitializeMemoryEvents(VOID
)
1078 UNICODE_STRING LowString
= RTL_CONSTANT_STRING(L
"\\KernelObjects\\LowMemoryCondition");
1079 UNICODE_STRING HighString
= RTL_CONSTANT_STRING(L
"\\KernelObjects\\HighMemoryCondition");
1080 UNICODE_STRING LowPagedPoolString
= RTL_CONSTANT_STRING(L
"\\KernelObjects\\LowPagedPoolCondition");
1081 UNICODE_STRING HighPagedPoolString
= RTL_CONSTANT_STRING(L
"\\KernelObjects\\HighPagedPoolCondition");
1082 UNICODE_STRING LowNonPagedPoolString
= RTL_CONSTANT_STRING(L
"\\KernelObjects\\LowNonPagedPoolCondition");
1083 UNICODE_STRING HighNonPagedPoolString
= RTL_CONSTANT_STRING(L
"\\KernelObjects\\HighNonPagedPoolCondition");
1086 /* Check if we have a registry setting */
1087 if (MmLowMemoryThreshold
)
1089 /* Convert it to pages */
1090 MmLowMemoryThreshold
*= (_1MB
/ PAGE_SIZE
);
1094 /* The low memory threshold is hit when we don't consider that we have "plenty" of free pages anymore */
1095 MmLowMemoryThreshold
= MmPlentyFreePages
;
1097 /* More than one GB of memory? */
1098 if (MmNumberOfPhysicalPages
> 0x40000)
1100 /* Start at 32MB, and add another 16MB for each GB */
1101 MmLowMemoryThreshold
= (32 * _1MB
) / PAGE_SIZE
;
1102 MmLowMemoryThreshold
+= ((MmNumberOfPhysicalPages
- 0x40000) >> 7);
1104 else if (MmNumberOfPhysicalPages
> 0x8000)
1106 /* For systems with > 128MB RAM, add another 4MB for each 128MB */
1107 MmLowMemoryThreshold
+= ((MmNumberOfPhysicalPages
- 0x8000) >> 5);
1110 /* Don't let the minimum threshold go past 64MB */
1111 MmLowMemoryThreshold
= min(MmLowMemoryThreshold
, (64 * _1MB
) / PAGE_SIZE
);
1114 /* Check if we have a registry setting */
1115 if (MmHighMemoryThreshold
)
1117 /* Convert it into pages */
1118 MmHighMemoryThreshold
*= (_1MB
/ PAGE_SIZE
);
1122 /* Otherwise, the default is three times the low memory threshold */
1123 MmHighMemoryThreshold
= 3 * MmLowMemoryThreshold
;
1124 ASSERT(MmHighMemoryThreshold
> MmLowMemoryThreshold
);
1127 /* Make sure high threshold is actually higher than the low */
1128 MmHighMemoryThreshold
= max(MmHighMemoryThreshold
, MmLowMemoryThreshold
);
1130 /* Create the memory events for all the thresholds */
1131 Status
= MiCreateMemoryEvent(&LowString
, &MiLowMemoryEvent
);
1132 if (!NT_SUCCESS(Status
)) return FALSE
;
1133 Status
= MiCreateMemoryEvent(&HighString
, &MiHighMemoryEvent
);
1134 if (!NT_SUCCESS(Status
)) return FALSE
;
1135 Status
= MiCreateMemoryEvent(&LowPagedPoolString
, &MiLowPagedPoolEvent
);
1136 if (!NT_SUCCESS(Status
)) return FALSE
;
1137 Status
= MiCreateMemoryEvent(&HighPagedPoolString
, &MiHighPagedPoolEvent
);
1138 if (!NT_SUCCESS(Status
)) return FALSE
;
1139 Status
= MiCreateMemoryEvent(&LowNonPagedPoolString
, &MiLowNonPagedPoolEvent
);
1140 if (!NT_SUCCESS(Status
)) return FALSE
;
1141 Status
= MiCreateMemoryEvent(&HighNonPagedPoolString
, &MiHighNonPagedPoolEvent
);
1142 if (!NT_SUCCESS(Status
)) return FALSE
;
1144 /* Now setup the pool events */
1145 MiInitializePoolEvents();
1147 /* Set the initial event state */
1148 MiNotifyMemoryEvents();
1154 MiAddHalIoMappings(VOID
)
1159 ULONG i
, j
, PdeCount
;
1160 PFN_NUMBER PageFrameIndex
;
1162 /* HAL Heap address -- should be on a PDE boundary */
1163 BaseAddress
= (PVOID
)0xFFC00000;
1164 ASSERT(MiAddressToPteOffset(BaseAddress
) == 0);
1166 /* Check how many PDEs the heap has */
1167 PointerPde
= MiAddressToPde(BaseAddress
);
1168 PdeCount
= PDE_COUNT
- ADDR_TO_PDE_OFFSET(BaseAddress
);
1169 for (i
= 0; i
< PdeCount
; i
++)
1171 /* Does the HAL own this mapping? */
1172 if ((PointerPde
->u
.Hard
.Valid
== 1) &&
1173 (PointerPde
->u
.Hard
.LargePage
== 0))
1175 /* Get the PTE for it and scan each page */
1176 PointerPte
= MiAddressToPte(BaseAddress
);
1177 for (j
= 0 ; j
< PTE_COUNT
; j
++)
1179 /* Does the HAL own this page? */
1180 if (PointerPte
->u
.Hard
.Valid
== 1)
1182 /* Is the HAL using it for device or I/O mapped memory? */
1183 PageFrameIndex
= PFN_FROM_PTE(PointerPte
);
1184 if (!MiGetPfnEntry(PageFrameIndex
))
1186 /* FIXME: For PAT, we need to track I/O cache attributes for coherency */
1187 DPRINT1("HAL I/O Mapping at %p is unsafe\n", BaseAddress
);
1191 /* Move to the next page */
1192 BaseAddress
= (PVOID
)((ULONG_PTR
)BaseAddress
+ PAGE_SIZE
);
1198 /* Move to the next address */
1199 BaseAddress
= (PVOID
)((ULONG_PTR
)BaseAddress
+ PDE_MAPPED_VA
);
1202 /* Move to the next PDE */
1209 MmDumpArmPfnDatabase(VOID
)
1213 PCHAR Consumer
= "Unknown";
1215 ULONG ActivePages
= 0, FreePages
= 0, OtherPages
= 0;
1217 KeRaiseIrql(HIGH_LEVEL
, &OldIrql
);
1220 // Loop the PFN database
1222 for (i
= 0; i
<= MmHighestPhysicalPage
; i
++)
1224 Pfn1
= MiGetPfnEntry(i
);
1225 if (!Pfn1
) continue;
1228 // Get the page location
1230 switch (Pfn1
->u3
.e1
.PageLocation
)
1232 case ActiveAndValid
:
1234 Consumer
= "Active and Valid";
1240 Consumer
= "Free Page List";
1246 Consumer
= "Other (ASSERT!)";
1252 // Pretty-print the page
1254 DbgPrint("0x%08p:\t%20s\t(%02d.%02d) [%08p-%08p])\n",
1257 Pfn1
->u3
.e2
.ReferenceCount
,
1258 Pfn1
->u2
.ShareCount
,
1263 DbgPrint("Active: %d pages\t[%d KB]\n", ActivePages
, (ActivePages
<< PAGE_SHIFT
) / 1024);
1264 DbgPrint("Free: %d pages\t[%d KB]\n", FreePages
, (FreePages
<< PAGE_SHIFT
) / 1024);
1265 DbgPrint("Other: %d pages\t[%d KB]\n", OtherPages
, (OtherPages
<< PAGE_SHIFT
) / 1024);
1267 KeLowerIrql(OldIrql
);
1272 MiPagesInLoaderBlock(IN PLOADER_PARAMETER_BLOCK LoaderBlock
,
1273 IN PBOOLEAN IncludeType
)
1275 PLIST_ENTRY NextEntry
;
1276 PFN_NUMBER PageCount
= 0;
1277 PMEMORY_ALLOCATION_DESCRIPTOR MdBlock
;
1280 // Now loop through the descriptors
1282 NextEntry
= LoaderBlock
->MemoryDescriptorListHead
.Flink
;
1283 while (NextEntry
!= &LoaderBlock
->MemoryDescriptorListHead
)
1286 // Grab each one, and check if it's one we should include
1288 MdBlock
= CONTAINING_RECORD(NextEntry
,
1289 MEMORY_ALLOCATION_DESCRIPTOR
,
1291 if ((MdBlock
->MemoryType
< LoaderMaximum
) &&
1292 (IncludeType
[MdBlock
->MemoryType
]))
1295 // Add this to our running total
1297 PageCount
+= MdBlock
->PageCount
;
1301 // Try the next descriptor
1303 NextEntry
= MdBlock
->ListEntry
.Flink
;
1312 PPHYSICAL_MEMORY_DESCRIPTOR
1314 MmInitializeMemoryLimits(IN PLOADER_PARAMETER_BLOCK LoaderBlock
,
1315 IN PBOOLEAN IncludeType
)
1317 PLIST_ENTRY NextEntry
;
1318 ULONG Run
= 0, InitialRuns
= 0;
1319 PFN_NUMBER NextPage
= -1, PageCount
= 0;
1320 PPHYSICAL_MEMORY_DESCRIPTOR Buffer
, NewBuffer
;
1321 PMEMORY_ALLOCATION_DESCRIPTOR MdBlock
;
1324 // Scan the memory descriptors
1326 NextEntry
= LoaderBlock
->MemoryDescriptorListHead
.Flink
;
1327 while (NextEntry
!= &LoaderBlock
->MemoryDescriptorListHead
)
1330 // For each one, increase the memory allocation estimate
1333 NextEntry
= NextEntry
->Flink
;
1337 // Allocate the maximum we'll ever need
1339 Buffer
= ExAllocatePoolWithTag(NonPagedPool
,
1340 sizeof(PHYSICAL_MEMORY_DESCRIPTOR
) +
1341 sizeof(PHYSICAL_MEMORY_RUN
) *
1344 if (!Buffer
) return NULL
;
1347 // For now that's how many runs we have
1349 Buffer
->NumberOfRuns
= InitialRuns
;
1352 // Now loop through the descriptors again
1354 NextEntry
= LoaderBlock
->MemoryDescriptorListHead
.Flink
;
1355 while (NextEntry
!= &LoaderBlock
->MemoryDescriptorListHead
)
1358 // Grab each one, and check if it's one we should include
1360 MdBlock
= CONTAINING_RECORD(NextEntry
,
1361 MEMORY_ALLOCATION_DESCRIPTOR
,
1363 if ((MdBlock
->MemoryType
< LoaderMaximum
) &&
1364 (IncludeType
[MdBlock
->MemoryType
]))
1367 // Add this to our running total
1369 PageCount
+= MdBlock
->PageCount
;
1372 // Check if the next page is described by the next descriptor
1374 if (MdBlock
->BasePage
== NextPage
)
1377 // Combine it into the same physical run
1379 ASSERT(MdBlock
->PageCount
!= 0);
1380 Buffer
->Run
[Run
- 1].PageCount
+= MdBlock
->PageCount
;
1381 NextPage
+= MdBlock
->PageCount
;
1386 // Otherwise just duplicate the descriptor's contents
1388 Buffer
->Run
[Run
].BasePage
= MdBlock
->BasePage
;
1389 Buffer
->Run
[Run
].PageCount
= MdBlock
->PageCount
;
1390 NextPage
= Buffer
->Run
[Run
].BasePage
+ Buffer
->Run
[Run
].PageCount
;
1393 // And in this case, increase the number of runs
1400 // Try the next descriptor
1402 NextEntry
= MdBlock
->ListEntry
.Flink
;
1406 // We should not have been able to go past our initial estimate
1408 ASSERT(Run
<= Buffer
->NumberOfRuns
);
1411 // Our guess was probably exaggerated...
1413 if (InitialRuns
> Run
)
1416 // Allocate a more accurately sized buffer
1418 NewBuffer
= ExAllocatePoolWithTag(NonPagedPool
,
1419 sizeof(PHYSICAL_MEMORY_DESCRIPTOR
) +
1420 sizeof(PHYSICAL_MEMORY_RUN
) *
1426 // Copy the old buffer into the new, then free it
1428 RtlCopyMemory(NewBuffer
->Run
,
1430 sizeof(PHYSICAL_MEMORY_RUN
) * Run
);
1434 // Now use the new buffer
1441 // Write the final numbers, and return it
1443 Buffer
->NumberOfRuns
= Run
;
1444 Buffer
->NumberOfPages
= PageCount
;
1450 MiBuildPagedPool(VOID
)
1452 PMMPTE PointerPte
, PointerPde
;
1453 MMPTE TempPte
= ValidKernelPte
;
1454 PFN_NUMBER PageFrameIndex
;
1456 ULONG Size
, BitMapSize
;
1459 // Get the page frame number for the system page directory
1461 PointerPte
= MiAddressToPte(PDE_BASE
);
1462 ASSERT(PD_COUNT
== 1);
1463 MmSystemPageDirectory
[0] = PFN_FROM_PTE(PointerPte
);
1466 // Allocate a system PTE which will hold a copy of the page directory
1468 PointerPte
= MiReserveSystemPtes(1, SystemPteSpace
);
1470 MmSystemPagePtes
= MiPteToAddress(PointerPte
);
1473 // Make this system PTE point to the system page directory.
1474 // It is now essentially double-mapped. This will be used later for lazy
1475 // evaluation of PDEs accross process switches, similarly to how the Global
1476 // page directory array in the old ReactOS Mm is used (but in a less hacky
1479 TempPte
= ValidKernelPte
;
1480 ASSERT(PD_COUNT
== 1);
1481 TempPte
.u
.Hard
.PageFrameNumber
= MmSystemPageDirectory
[0];
1482 MI_WRITE_VALID_PTE(PointerPte
, TempPte
);
1485 // Let's get back to paged pool work: size it up.
1486 // By default, it should be twice as big as nonpaged pool.
1488 MmSizeOfPagedPoolInBytes
= 2 * MmMaximumNonPagedPoolInBytes
;
1489 if (MmSizeOfPagedPoolInBytes
> ((ULONG_PTR
)MmNonPagedSystemStart
-
1490 (ULONG_PTR
)MmPagedPoolStart
))
1493 // On the other hand, we have limited VA space, so make sure that the VA
1494 // for paged pool doesn't overflow into nonpaged pool VA. Otherwise, set
1495 // whatever maximum is possible.
1497 MmSizeOfPagedPoolInBytes
= (ULONG_PTR
)MmNonPagedSystemStart
-
1498 (ULONG_PTR
)MmPagedPoolStart
;
1502 // Get the size in pages and make sure paged pool is at least 32MB.
1504 Size
= MmSizeOfPagedPoolInBytes
;
1505 if (Size
< MI_MIN_INIT_PAGED_POOLSIZE
) Size
= MI_MIN_INIT_PAGED_POOLSIZE
;
1506 Size
= BYTES_TO_PAGES(Size
);
1509 // Now check how many PTEs will be required for these many pages.
1511 Size
= (Size
+ (1024 - 1)) / 1024;
1514 // Recompute the page-aligned size of the paged pool, in bytes and pages.
1516 MmSizeOfPagedPoolInBytes
= Size
* PAGE_SIZE
* 1024;
1517 MmSizeOfPagedPoolInPages
= MmSizeOfPagedPoolInBytes
>> PAGE_SHIFT
;
1520 // Let's be really sure this doesn't overflow into nonpaged system VA
1522 ASSERT((MmSizeOfPagedPoolInBytes
+ (ULONG_PTR
)MmPagedPoolStart
) <=
1523 (ULONG_PTR
)MmNonPagedSystemStart
);
1526 // This is where paged pool ends
1528 MmPagedPoolEnd
= (PVOID
)(((ULONG_PTR
)MmPagedPoolStart
+
1529 MmSizeOfPagedPoolInBytes
) - 1);
1532 // So now get the PDE for paged pool and zero it out
1534 PointerPde
= MiAddressToPde(MmPagedPoolStart
);
1535 RtlZeroMemory(PointerPde
,
1536 (1 + MiAddressToPde(MmPagedPoolEnd
) - PointerPde
) * sizeof(MMPTE
));
1539 // Next, get the first and last PTE
1541 PointerPte
= MiAddressToPte(MmPagedPoolStart
);
1542 MmPagedPoolInfo
.FirstPteForPagedPool
= PointerPte
;
1543 MmPagedPoolInfo
.LastPteForPagedPool
= MiAddressToPte(MmPagedPoolEnd
);
1546 // Lock the PFN database
1548 OldIrql
= KeAcquireQueuedSpinLock(LockQueuePfnLock
);
1550 /* Allocate a page and map the first paged pool PDE */
1551 PageFrameIndex
= MiRemoveZeroPage(0);
1552 TempPte
.u
.Hard
.PageFrameNumber
= PageFrameIndex
;
1553 MI_WRITE_VALID_PTE(PointerPde
, TempPte
);
1555 /* Initialize the PFN entry for it */
1556 MiInitializePfnForOtherProcess(PageFrameIndex
,
1558 MmSystemPageDirectory
[(PointerPde
- (PMMPTE
)PDE_BASE
) / PDE_COUNT
]);
1561 // Release the PFN database lock
1563 KeReleaseQueuedSpinLock(LockQueuePfnLock
, OldIrql
);
1566 // We only have one PDE mapped for now... at fault time, additional PDEs
1567 // will be allocated to handle paged pool growth. This is where they'll have
1570 MmPagedPoolInfo
.NextPdeForPagedPoolExpansion
= PointerPde
+ 1;
1573 // We keep track of each page via a bit, so check how big the bitmap will
1574 // have to be (make sure to align our page count such that it fits nicely
1575 // into a 4-byte aligned bitmap.
1577 // We'll also allocate the bitmap header itself part of the same buffer.
1580 ASSERT(Size
== MmSizeOfPagedPoolInPages
);
1582 Size
= sizeof(RTL_BITMAP
) + (((Size
+ 31) / 32) * sizeof(ULONG
));
1585 // Allocate the allocation bitmap, which tells us which regions have not yet
1586 // been mapped into memory
1588 MmPagedPoolInfo
.PagedPoolAllocationMap
= ExAllocatePoolWithTag(NonPagedPool
,
1591 ASSERT(MmPagedPoolInfo
.PagedPoolAllocationMap
);
1594 // Initialize it such that at first, only the first page's worth of PTEs is
1595 // marked as allocated (incidentially, the first PDE we allocated earlier).
1597 RtlInitializeBitMap(MmPagedPoolInfo
.PagedPoolAllocationMap
,
1598 (PULONG
)(MmPagedPoolInfo
.PagedPoolAllocationMap
+ 1),
1600 RtlSetAllBits(MmPagedPoolInfo
.PagedPoolAllocationMap
);
1601 RtlClearBits(MmPagedPoolInfo
.PagedPoolAllocationMap
, 0, 1024);
1604 // We have a second bitmap, which keeps track of where allocations end.
1605 // Given the allocation bitmap and a base address, we can therefore figure
1606 // out which page is the last page of that allocation, and thus how big the
1607 // entire allocation is.
1609 MmPagedPoolInfo
.EndOfPagedPoolBitmap
= ExAllocatePoolWithTag(NonPagedPool
,
1612 ASSERT(MmPagedPoolInfo
.EndOfPagedPoolBitmap
);
1613 RtlInitializeBitMap(MmPagedPoolInfo
.EndOfPagedPoolBitmap
,
1614 (PULONG
)(MmPagedPoolInfo
.EndOfPagedPoolBitmap
+ 1),
1618 // Since no allocations have been made yet, there are no bits set as the end
1620 RtlClearAllBits(MmPagedPoolInfo
.EndOfPagedPoolBitmap
);
1623 // Initialize paged pool.
1625 InitializePool(PagedPool
, 0);
1627 /* Default low threshold of 30MB or one fifth of paged pool */
1628 MiLowPagedPoolThreshold
= (30 * _1MB
) >> PAGE_SHIFT
;
1629 MiLowPagedPoolThreshold
= min(MiLowPagedPoolThreshold
, Size
/ 5);
1631 /* Default high threshold of 60MB or 25% */
1632 MiHighPagedPoolThreshold
= (60 * _1MB
) >> PAGE_SHIFT
;
1633 MiHighPagedPoolThreshold
= min(MiHighPagedPoolThreshold
, (Size
* 2) / 5);
1634 ASSERT(MiLowPagedPoolThreshold
< MiHighPagedPoolThreshold
);
1639 MmArmInitSystem(IN ULONG Phase
,
1640 IN PLOADER_PARAMETER_BLOCK LoaderBlock
)
1643 BOOLEAN IncludeType
[LoaderMaximum
];
1645 PPHYSICAL_MEMORY_RUN Run
;
1646 PFN_NUMBER PageCount
;
1649 // Instantiate memory that we don't consider RAM/usable
1650 // We use the same exclusions that Windows does, in order to try to be
1651 // compatible with WinLDR-style booting
1653 for (i
= 0; i
< LoaderMaximum
; i
++) IncludeType
[i
] = TRUE
;
1654 IncludeType
[LoaderBad
] = FALSE
;
1655 IncludeType
[LoaderFirmwarePermanent
] = FALSE
;
1656 IncludeType
[LoaderSpecialMemory
] = FALSE
;
1657 IncludeType
[LoaderBBTMemory
] = FALSE
;
1660 /* Initialize the phase 0 temporary event */
1661 KeInitializeEvent(&MiTempEvent
, NotificationEvent
, FALSE
);
1663 /* Set all the events to use the temporary event for now */
1664 MiLowMemoryEvent
= &MiTempEvent
;
1665 MiHighMemoryEvent
= &MiTempEvent
;
1666 MiLowPagedPoolEvent
= &MiTempEvent
;
1667 MiHighPagedPoolEvent
= &MiTempEvent
;
1668 MiLowNonPagedPoolEvent
= &MiTempEvent
;
1669 MiHighNonPagedPoolEvent
= &MiTempEvent
;
1672 // Define the basic user vs. kernel address space separation
1674 MmSystemRangeStart
= (PVOID
)KSEG0_BASE
;
1675 MmUserProbeAddress
= (ULONG_PTR
)MmSystemRangeStart
- 0x10000;
1676 MmHighestUserAddress
= (PVOID
)(MmUserProbeAddress
- 1);
1678 /* Highest PTE and PDE based on the addresses above */
1679 MiHighestUserPte
= MiAddressToPte(MmHighestUserAddress
);
1680 MiHighestUserPde
= MiAddressToPde(MmHighestUserAddress
);
1683 // Get the size of the boot loader's image allocations and then round
1684 // that region up to a PDE size, so that any PDEs we might create for
1685 // whatever follows are separate from the PDEs that boot loader might've
1686 // already created (and later, we can blow all that away if we want to).
1688 MmBootImageSize
= KeLoaderBlock
->Extension
->LoaderPagesSpanned
;
1689 MmBootImageSize
*= PAGE_SIZE
;
1690 MmBootImageSize
= (MmBootImageSize
+ PDE_MAPPED_VA
- 1) & ~(PDE_MAPPED_VA
- 1);
1691 ASSERT((MmBootImageSize
% PDE_MAPPED_VA
) == 0);
1694 // Set the size of session view, pool, and image
1696 MmSessionSize
= MI_SESSION_SIZE
;
1697 MmSessionViewSize
= MI_SESSION_VIEW_SIZE
;
1698 MmSessionPoolSize
= MI_SESSION_POOL_SIZE
;
1699 MmSessionImageSize
= MI_SESSION_IMAGE_SIZE
;
1702 // Set the size of system view
1704 MmSystemViewSize
= MI_SYSTEM_VIEW_SIZE
;
1707 // This is where it all ends
1709 MiSessionImageEnd
= (PVOID
)PTE_BASE
;
1712 // This is where we will load Win32k.sys and the video driver
1714 MiSessionImageStart
= (PVOID
)((ULONG_PTR
)MiSessionImageEnd
-
1715 MmSessionImageSize
);
1718 // So the view starts right below the session working set (itself below
1721 MiSessionViewStart
= (PVOID
)((ULONG_PTR
)MiSessionImageEnd
-
1722 MmSessionImageSize
-
1723 MI_SESSION_WORKING_SET_SIZE
-
1727 // Session pool follows
1729 MiSessionPoolEnd
= MiSessionViewStart
;
1730 MiSessionPoolStart
= (PVOID
)((ULONG_PTR
)MiSessionPoolEnd
-
1734 // And it all begins here
1736 MmSessionBase
= MiSessionPoolStart
;
1739 // Sanity check that our math is correct
1741 ASSERT((ULONG_PTR
)MmSessionBase
+ MmSessionSize
== PTE_BASE
);
1744 // Session space ends wherever image session space ends
1746 MiSessionSpaceEnd
= MiSessionImageEnd
;
1749 // System view space ends at session space, so now that we know where
1750 // this is, we can compute the base address of system view space itself.
1752 MiSystemViewStart
= (PVOID
)((ULONG_PTR
)MmSessionBase
-
1755 /* Compute the PTE addresses for all the addresses we carved out */
1756 MiSessionImagePteStart
= MiAddressToPte(MiSessionImageStart
);
1757 MiSessionImagePteEnd
= MiAddressToPte(MiSessionImageEnd
);
1758 MiSessionBasePte
= MiAddressToPte(MmSessionBase
);
1759 MiSessionLastPte
= MiAddressToPte(MiSessionSpaceEnd
);
1761 /* Initialize the user mode image list */
1762 InitializeListHead(&MmLoadedUserImageList
);
1764 /* Initialize the paged pool mutex */
1765 KeInitializeGuardedMutex(&MmPagedPoolMutex
);
1767 /* Initialize the Loader Lock */
1768 KeInitializeMutant(&MmSystemLoadLock
, FALSE
);
1771 // Count physical pages on the system
1773 PageCount
= MiPagesInLoaderBlock(LoaderBlock
, IncludeType
);
1776 // Check if this is a machine with less than 19MB of RAM
1778 if (PageCount
< MI_MIN_PAGES_FOR_SYSPTE_TUNING
)
1781 // Use the very minimum of system PTEs
1783 MmNumberOfSystemPtes
= 7000;
1788 // Use the default, but check if we have more than 32MB of RAM
1790 MmNumberOfSystemPtes
= 11000;
1791 if (PageCount
> MI_MIN_PAGES_FOR_SYSPTE_BOOST
)
1794 // Double the amount of system PTEs
1796 MmNumberOfSystemPtes
<<= 1;
1800 DPRINT("System PTE count has been tuned to %d (%d bytes)\n",
1801 MmNumberOfSystemPtes
, MmNumberOfSystemPtes
* PAGE_SIZE
);
1803 /* Initialize the platform-specific parts */
1804 MiInitMachineDependent(LoaderBlock
);
1807 // Sync us up with ReactOS Mm
1809 MiSyncARM3WithROS(MmNonPagedSystemStart
, (PVOID
)((ULONG_PTR
)MmNonPagedPoolEnd
- 1));
1810 MiSyncARM3WithROS(MmPfnDatabase
, (PVOID
)((ULONG_PTR
)MmNonPagedPoolStart
+ MmSizeOfNonPagedPoolInBytes
- 1));
1811 MiSyncARM3WithROS((PVOID
)HYPER_SPACE
, (PVOID
)(HYPER_SPACE
+ PAGE_SIZE
- 1));
1814 // Build the physical memory block
1816 MmPhysicalMemoryBlock
= MmInitializeMemoryLimits(LoaderBlock
,
1820 // Allocate enough buffer for the PFN bitmap
1821 // Align it up to a 32-bit boundary
1823 Bitmap
= ExAllocatePoolWithTag(NonPagedPool
,
1824 (((MmHighestPhysicalPage
+ 1) + 31) / 32) * 4,
1831 KeBugCheckEx(INSTALL_MORE_MEMORY
,
1832 MmNumberOfPhysicalPages
,
1833 MmLowestPhysicalPage
,
1834 MmHighestPhysicalPage
,
1839 // Initialize it and clear all the bits to begin with
1841 RtlInitializeBitMap(&MiPfnBitMap
,
1843 MmHighestPhysicalPage
+ 1);
1844 RtlClearAllBits(&MiPfnBitMap
);
1847 // Loop physical memory runs
1849 for (i
= 0; i
< MmPhysicalMemoryBlock
->NumberOfRuns
; i
++)
1854 Run
= &MmPhysicalMemoryBlock
->Run
[i
];
1855 DPRINT("PHYSICAL RAM [0x%08p to 0x%08p]\n",
1856 Run
->BasePage
<< PAGE_SHIFT
,
1857 (Run
->BasePage
+ Run
->PageCount
) << PAGE_SHIFT
);
1860 // Make sure it has pages inside it
1865 // Set the bits in the PFN bitmap
1867 RtlSetBits(&MiPfnBitMap
, Run
->BasePage
, Run
->PageCount
);
1871 /* Look for large page cache entries that need caching */
1872 MiSyncCachedRanges();
1874 /* Loop for HAL Heap I/O device mappings that need coherency tracking */
1875 MiAddHalIoMappings();
1877 /* Set the initial resident page count */
1878 MmResidentAvailablePages
= MmAvailablePages
- 32;
1880 /* Initialize large page structures on PAE/x64, and MmProcessList on x86 */
1881 MiInitializeLargePageSupport();
1883 /* Check if the registry says any drivers should be loaded with large pages */
1884 MiInitializeDriverLargePageList();
1886 /* Relocate the boot drivers into system PTE space and fixup their PFNs */
1887 MiReloadBootLoadedDrivers(LoaderBlock
);
1889 /* FIXME: Call out into Driver Verifier for initialization */
1891 /* Check how many pages the system has */
1892 if (MmNumberOfPhysicalPages
<= (13 * _1MB
))
1894 /* Set small system */
1895 MmSystemSize
= MmSmallSystem
;
1897 else if (MmNumberOfPhysicalPages
<= (19 * _1MB
))
1899 /* Set small system and add 100 pages for the cache */
1900 MmSystemSize
= MmSmallSystem
;
1901 MmSystemCacheWsMinimum
+= 100;
1905 /* Set medium system and add 400 pages for the cache */
1906 MmSystemSize
= MmMediumSystem
;
1907 MmSystemCacheWsMinimum
+= 400;
1910 /* Check for less than 24MB */
1911 if (MmNumberOfPhysicalPages
< ((24 * _1MB
) / PAGE_SIZE
))
1913 /* No more than 32 pages */
1914 MmSystemCacheWsMinimum
= 32;
1917 /* Check for more than 32MB */
1918 if (MmNumberOfPhysicalPages
>= ((32 * _1MB
) / PAGE_SIZE
))
1920 /* Check for product type being "Wi" for WinNT */
1921 if (MmProductType
== '\0i\0W')
1923 /* Then this is a large system */
1924 MmSystemSize
= MmLargeSystem
;
1928 /* For servers, we need 64MB to consider this as being large */
1929 if (MmNumberOfPhysicalPages
>= ((64 * _1MB
) / PAGE_SIZE
))
1931 /* Set it as large */
1932 MmSystemSize
= MmLargeSystem
;
1937 /* Check for more than 33 MB */
1938 if (MmNumberOfPhysicalPages
> ((33 * _1MB
) / PAGE_SIZE
))
1940 /* Add another 500 pages to the cache */
1941 MmSystemCacheWsMinimum
+= 500;
1944 /* Now setup the shared user data fields */
1945 ASSERT(SharedUserData
->NumberOfPhysicalPages
== 0);
1946 SharedUserData
->NumberOfPhysicalPages
= MmNumberOfPhysicalPages
;
1947 SharedUserData
->LargePageMinimum
= 0;
1949 /* Check for workstation (Wi for WinNT) */
1950 if (MmProductType
== '\0i\0W')
1952 /* Set Windows NT Workstation product type */
1953 SharedUserData
->NtProductType
= NtProductWinNt
;
1958 /* Check for LanMan server */
1959 if (MmProductType
== '\0a\0L')
1961 /* This is a domain controller */
1962 SharedUserData
->NtProductType
= NtProductLanManNt
;
1966 /* Otherwise it must be a normal server */
1967 SharedUserData
->NtProductType
= NtProductServer
;
1970 /* Set the product type, and make the system more aggressive with low memory */
1972 MmMinimumFreePages
= 81;
1975 /* Update working set tuning parameters */
1976 MiAdjustWorkingSetManagerParameters(!MmProductType
);
1978 /* Finetune the page count by removing working set and NP expansion */
1979 MmResidentAvailablePages
-= MiExpansionPoolPagesInitialCharge
;
1980 MmResidentAvailablePages
-= MmSystemCacheWsMinimum
;
1981 MmResidentAvailableAtInit
= MmResidentAvailablePages
;
1982 if (MmResidentAvailablePages
<= 0)
1984 /* This should not happen */
1985 DPRINT1("System cache working set too big\n");
1989 /* Size up paged pool and build the shadow system page directory */
1992 /* Debugger physical memory support is now ready to be used */
1993 MiDbgReadyForPhysical
= TRUE
;
1995 /* Initialize the loaded module list */
1996 MiInitializeLoadedModuleList(LoaderBlock
);
2000 // Always return success for now
2002 return STATUS_SUCCESS
;