2 * PROJECT: ReactOS Kernel
3 * LICENSE: BSD - See COPYING.ARM in the top level directory
4 * FILE: ntoskrnl/mm/ARM3/mminit.c
5 * PURPOSE: ARM Memory Manager Initialization
6 * PROGRAMMERS: ReactOS Portable Systems Group
9 /* INCLUDES *******************************************************************/
16 #define MODULE_INVOLVED_IN_ARM3
19 /* GLOBALS ********************************************************************/
22 // These are all registry-configurable, but by default, the memory manager will
23 // figure out the most appropriate values.
25 ULONG MmMaximumNonPagedPoolPercent
;
26 SIZE_T MmSizeOfNonPagedPoolInBytes
;
27 SIZE_T MmMaximumNonPagedPoolInBytes
;
29 /* Some of the same values, in pages */
30 PFN_NUMBER MmMaximumNonPagedPoolInPages
;
33 // These numbers describe the discrete equation components of the nonpaged
34 // pool sizing algorithm.
36 // They are described on http://support.microsoft.com/default.aspx/kb/126402/ja
37 // along with the algorithm that uses them, which is implemented later below.
39 SIZE_T MmMinimumNonPagedPoolSize
= 256 * 1024;
40 ULONG MmMinAdditionNonPagedPoolPerMb
= 32 * 1024;
41 SIZE_T MmDefaultMaximumNonPagedPool
= 1024 * 1024;
42 ULONG MmMaxAdditionNonPagedPoolPerMb
= 400 * 1024;
45 // The memory layout (and especially variable names) of the NT kernel mode
46 // components can be a bit hard to twig, especially when it comes to the non
49 // There are really two components to the non-paged pool:
51 // - The initial nonpaged pool, sized dynamically up to a maximum.
52 // - The expansion nonpaged pool, sized dynamically up to a maximum.
54 // The initial nonpaged pool is physically continuous for performance, and
55 // immediately follows the PFN database, typically sharing the same PDE. It is
56 // a very small resource (32MB on a 1GB system), and capped at 128MB.
58 // Right now we call this the "ARM³ Nonpaged Pool" and it begins somewhere after
59 // the PFN database (which starts at 0xB0000000).
61 // The expansion nonpaged pool, on the other hand, can grow much bigger (400MB
62 // for a 1GB system). On ARM³ however, it is currently capped at 128MB.
64 // The address where the initial nonpaged pool starts is aptly named
65 // MmNonPagedPoolStart, and it describes a range of MmSizeOfNonPagedPoolInBytes
68 // Expansion nonpaged pool starts at an address described by the variable called
69 // MmNonPagedPoolExpansionStart, and it goes on for MmMaximumNonPagedPoolInBytes
70 // minus MmSizeOfNonPagedPoolInBytes bytes, always reaching MmNonPagedPoolEnd
71 // (because of the way it's calculated) at 0xFFBE0000.
73 // Initial nonpaged pool is allocated and mapped early-on during boot, but what
74 // about the expansion nonpaged pool? It is instead composed of special pages
75 // which belong to what are called System PTEs. These PTEs are the matter of a
76 // later discussion, but they are also considered part of the "nonpaged" OS, due
77 // to the fact that they are never paged out -- once an address is described by
78 // a System PTE, it is always valid, until the System PTE is torn down.
80 // System PTEs are actually composed of two "spaces", the system space proper,
81 // and the nonpaged pool expansion space. The latter, as we've already seen,
82 // begins at MmNonPagedPoolExpansionStart. Based on the number of System PTEs
83 // that the system will support, the remaining address space below this address
84 // is used to hold the system space PTEs. This address, in turn, is held in the
85 // variable named MmNonPagedSystemStart, which itself is never allowed to go
86 // below 0xEB000000 (thus creating an upper bound on the number of System PTEs).
88 // This means that 330MB are reserved for total nonpaged system VA, on top of
89 // whatever the initial nonpaged pool allocation is.
91 // The following URLs, valid as of April 23rd, 2008, support this evidence:
93 // http://www.cs.miami.edu/~burt/journal/NT/memory.html
94 // http://www.ditii.com/2007/09/28/windows-memory-management-x86-virtual-address-space/
96 PVOID MmNonPagedSystemStart
;
97 PVOID MmNonPagedPoolStart
;
98 PVOID MmNonPagedPoolExpansionStart
;
99 PVOID MmNonPagedPoolEnd
= MI_NONPAGED_POOL_END
;
102 // This is where paged pool starts by default
104 PVOID MmPagedPoolStart
= MI_PAGED_POOL_START
;
105 PVOID MmPagedPoolEnd
;
108 // And this is its default size
110 SIZE_T MmSizeOfPagedPoolInBytes
= MI_MIN_INIT_PAGED_POOLSIZE
;
111 PFN_NUMBER MmSizeOfPagedPoolInPages
= MI_MIN_INIT_PAGED_POOLSIZE
/ PAGE_SIZE
;
114 // Session space starts at 0xBFFFFFFF and grows downwards
115 // By default, it includes an 8MB image area where we map win32k and video card
116 // drivers, followed by a 4MB area containing the session's working set. This is
117 // then followed by a 20MB mapped view area and finally by the session's paged
118 // pool, by default 16MB.
120 // On a normal system, this results in session space occupying the region from
121 // 0xBD000000 to 0xC0000000
123 // See miarm.h for the defines that determine the sizing of this region. On an
124 // NT system, some of these can be configured through the registry, but we don't
127 PVOID MiSessionSpaceEnd
; // 0xC0000000
128 PVOID MiSessionImageEnd
; // 0xC0000000
129 PVOID MiSessionImageStart
; // 0xBF800000
130 PVOID MiSessionViewStart
; // 0xBE000000
131 PVOID MiSessionPoolEnd
; // 0xBE000000
132 PVOID MiSessionPoolStart
; // 0xBD000000
133 PVOID MmSessionBase
; // 0xBD000000
134 SIZE_T MmSessionSize
;
135 SIZE_T MmSessionViewSize
;
136 SIZE_T MmSessionPoolSize
;
137 SIZE_T MmSessionImageSize
;
140 * These are the PTE addresses of the boundaries carved out above
142 PMMPTE MiSessionImagePteStart
;
143 PMMPTE MiSessionImagePteEnd
;
144 PMMPTE MiSessionBasePte
;
145 PMMPTE MiSessionLastPte
;
148 // The system view space, on the other hand, is where sections that are memory
149 // mapped into "system space" end up.
151 // By default, it is a 16MB region.
153 PVOID MiSystemViewStart
;
154 SIZE_T MmSystemViewSize
;
156 #if (_MI_PAGING_LEVELS == 2)
158 // A copy of the system page directory (the page directory associated with the
159 // System process) is kept (double-mapped) by the manager in order to lazily
160 // map paged pool PDEs into external processes when they fault on a paged pool
163 PFN_NUMBER MmSystemPageDirectory
[PD_COUNT
];
164 PMMPTE MmSystemPagePtes
;
168 // The system cache starts right after hyperspace. The first few pages are for
169 // keeping track of the system working set list.
171 // This should be 0xC0C00000 -- the cache itself starts at 0xC1000000
173 PMMWSL MmSystemCacheWorkingSetList
= MI_SYSTEM_CACHE_WS_START
;
176 // Windows NT seems to choose between 7000, 11000 and 50000
177 // On systems with more than 32MB, this number is then doubled, and further
178 // aligned up to a PDE boundary (4MB).
180 ULONG_PTR MmNumberOfSystemPtes
;
183 // This is how many pages the PFN database will take up
184 // In Windows, this includes the Quark Color Table, but not in ARM³
186 PFN_NUMBER MxPfnAllocation
;
189 // Unlike the old ReactOS Memory Manager, ARM³ (and Windows) does not keep track
190 // of pages that are not actually valid physical memory, such as ACPI reserved
191 // regions, BIOS address ranges, or holes in physical memory address space which
192 // could indicate device-mapped I/O memory.
194 // In fact, the lack of a PFN entry for a page usually indicates that this is
195 // I/O space instead.
197 // A bitmap, called the PFN bitmap, keeps track of all page frames by assigning
198 // a bit to each. If the bit is set, then the page is valid physical RAM.
200 RTL_BITMAP MiPfnBitMap
;
203 // This structure describes the different pieces of RAM-backed address space
205 PPHYSICAL_MEMORY_DESCRIPTOR MmPhysicalMemoryBlock
;
208 // This is where we keep track of the most basic physical layout markers
210 PFN_NUMBER MmNumberOfPhysicalPages
, MmHighestPhysicalPage
, MmLowestPhysicalPage
= -1;
213 // The total number of pages mapped by the boot loader, which include the kernel
214 // HAL, boot drivers, registry, NLS files and other loader data structures is
215 // kept track of here. This depends on "LoaderPagesSpanned" being correct when
216 // coming from the loader.
218 // This number is later aligned up to a PDE boundary.
220 SIZE_T MmBootImageSize
;
223 // These three variables keep track of the core separation of address space that
224 // exists between kernel mode and user mode.
226 ULONG_PTR MmUserProbeAddress
;
227 PVOID MmHighestUserAddress
;
228 PVOID MmSystemRangeStart
;
230 /* And these store the respective highest PTE/PDE address */
231 PMMPTE MiHighestUserPte
;
232 PMMPDE MiHighestUserPde
;
233 #if (_MI_PAGING_LEVELS >= 3)
234 /* We need the highest PPE and PXE addresses */
237 /* These variables define the system cache address space */
238 PVOID MmSystemCacheStart
;
239 PVOID MmSystemCacheEnd
;
240 MMSUPPORT MmSystemCacheWs
;
243 // This is where hyperspace ends (followed by the system cache working set)
245 PVOID MmHyperSpaceEnd
;
248 // Page coloring algorithm data
250 ULONG MmSecondaryColors
;
251 ULONG MmSecondaryColorMask
;
254 // Actual (registry-configurable) size of a GUI thread's stack
256 ULONG MmLargeStackSize
= KERNEL_LARGE_STACK_SIZE
;
259 // Before we have a PFN database, memory comes straight from our physical memory
260 // blocks, which is nice because it's guaranteed contiguous and also because once
261 // we take a page from here, the system doesn't see it anymore.
262 // However, once the fun is over, those pages must be re-integrated back into
263 // PFN society life, and that requires us keeping a copy of the original layout
264 // so that we can parse it later.
266 PMEMORY_ALLOCATION_DESCRIPTOR MxFreeDescriptor
;
267 MEMORY_ALLOCATION_DESCRIPTOR MxOldFreeDescriptor
;
270 * For each page's worth bytes of L2 cache in a given set/way line, the zero and
271 * free lists are organized in what is called a "color".
273 * This array points to the two lists, so it can be thought of as a multi-dimensional
274 * array of MmFreePagesByColor[2][MmSecondaryColors]. Since the number is dynamic,
275 * we describe the array in pointer form instead.
277 * On a final note, the color tables themselves are right after the PFN database.
279 C_ASSERT(FreePageList
== 1);
280 PMMCOLOR_TABLES MmFreePagesByColor
[FreePageList
+ 1];
282 /* An event used in Phase 0 before the rest of the system is ready to go */
285 /* All the events used for memory threshold notifications */
286 PKEVENT MiLowMemoryEvent
;
287 PKEVENT MiHighMemoryEvent
;
288 PKEVENT MiLowPagedPoolEvent
;
289 PKEVENT MiHighPagedPoolEvent
;
290 PKEVENT MiLowNonPagedPoolEvent
;
291 PKEVENT MiHighNonPagedPoolEvent
;
293 /* The actual thresholds themselves, in page numbers */
294 PFN_NUMBER MmLowMemoryThreshold
;
295 PFN_NUMBER MmHighMemoryThreshold
;
296 PFN_NUMBER MiLowPagedPoolThreshold
;
297 PFN_NUMBER MiHighPagedPoolThreshold
;
298 PFN_NUMBER MiLowNonPagedPoolThreshold
;
299 PFN_NUMBER MiHighNonPagedPoolThreshold
;
302 * This number determines how many free pages must exist, at minimum, until we
303 * start trimming working sets and flushing modified pages to obtain more free
306 * This number changes if the system detects that this is a server product
308 PFN_NUMBER MmMinimumFreePages
= 26;
311 * This number indicates how many pages we consider to be a low limit of having
312 * "plenty" of free memory.
314 * It is doubled on systems that have more than 63MB of memory
316 PFN_NUMBER MmPlentyFreePages
= 400;
318 /* These values store the type of system this is (small, med, large) and if server */
320 MM_SYSTEMSIZE MmSystemSize
;
323 * These values store the cache working set minimums and maximums, in pages
325 * The minimum value is boosted on systems with more than 24MB of RAM, and cut
326 * down to only 32 pages on embedded (<24MB RAM) systems.
328 * An extra boost of 2MB is given on systems with more than 33MB of RAM.
330 PFN_NUMBER MmSystemCacheWsMinimum
= 288;
331 PFN_NUMBER MmSystemCacheWsMaximum
= 350;
333 /* FIXME: Move to cache/working set code later */
334 BOOLEAN MmLargeSystemCache
;
337 * This value determines in how many fragments/chunks the subsection prototype
338 * PTEs should be allocated when mapping a section object. It is configurable in
339 * the registry through the MapAllocationFragment parameter.
341 * The default is 64KB on systems with more than 1GB of RAM, 32KB on systems with
342 * more than 256MB of RAM, and 16KB on systems with less than 256MB of RAM.
344 * The maximum it can be set to is 2MB, and the minimum is 4KB.
346 SIZE_T MmAllocationFragment
;
349 * These two values track how much virtual memory can be committed, and when
350 * expansion should happen.
352 // FIXME: They should be moved elsewhere since it's not an "init" setting?
353 SIZE_T MmTotalCommitLimit
;
354 SIZE_T MmTotalCommitLimitMaximum
;
356 /* Internal setting used for debugging memory descriptors */
357 BOOLEAN MiDbgEnableMdDump
=
364 /* PRIVATE FUNCTIONS **********************************************************/
368 MxGetNextPage(IN PFN_NUMBER PageCount
)
372 /* Make sure we have enough pages */
373 if (PageCount
> MxFreeDescriptor
->PageCount
)
375 /* Crash the system */
376 KeBugCheckEx(INSTALL_MORE_MEMORY
,
377 MmNumberOfPhysicalPages
,
378 MxFreeDescriptor
->PageCount
,
379 MxOldFreeDescriptor
.PageCount
,
383 /* Use our lowest usable free pages */
384 Pfn
= MxFreeDescriptor
->BasePage
;
385 MxFreeDescriptor
->BasePage
+= PageCount
;
386 MxFreeDescriptor
->PageCount
-= PageCount
;
392 MiComputeColorInformation(VOID
)
394 ULONG L2Associativity
;
396 /* Check if no setting was provided already */
397 if (!MmSecondaryColors
)
399 /* Get L2 cache information */
400 L2Associativity
= KeGetPcr()->SecondLevelCacheAssociativity
;
402 /* The number of colors is the number of cache bytes by set/way */
403 MmSecondaryColors
= KeGetPcr()->SecondLevelCacheSize
;
404 if (L2Associativity
) MmSecondaryColors
/= L2Associativity
;
407 /* Now convert cache bytes into pages */
408 MmSecondaryColors
>>= PAGE_SHIFT
;
409 if (!MmSecondaryColors
)
411 /* If there was no cache data from the KPCR, use the default colors */
412 MmSecondaryColors
= MI_SECONDARY_COLORS
;
416 /* Otherwise, make sure there aren't too many colors */
417 if (MmSecondaryColors
> MI_MAX_SECONDARY_COLORS
)
419 /* Set the maximum */
420 MmSecondaryColors
= MI_MAX_SECONDARY_COLORS
;
423 /* Make sure there aren't too little colors */
424 if (MmSecondaryColors
< MI_MIN_SECONDARY_COLORS
)
426 /* Set the default */
427 MmSecondaryColors
= MI_SECONDARY_COLORS
;
430 /* Finally make sure the colors are a power of two */
431 if (MmSecondaryColors
& (MmSecondaryColors
- 1))
433 /* Set the default */
434 MmSecondaryColors
= MI_SECONDARY_COLORS
;
438 /* Compute the mask and store it */
439 MmSecondaryColorMask
= MmSecondaryColors
- 1;
440 KeGetCurrentPrcb()->SecondaryColorMask
= MmSecondaryColorMask
;
445 MiInitializeColorTables(VOID
)
448 PMMPTE PointerPte
, LastPte
;
449 MMPTE TempPte
= ValidKernelPte
;
451 /* The color table starts after the ARM3 PFN database */
452 MmFreePagesByColor
[0] = (PMMCOLOR_TABLES
)&MmPfnDatabase
[MmHighestPhysicalPage
+ 1];
454 /* Loop the PTEs. We have two color tables for each secondary color */
455 PointerPte
= MiAddressToPte(&MmFreePagesByColor
[0][0]);
456 LastPte
= MiAddressToPte((ULONG_PTR
)MmFreePagesByColor
[0] +
457 (2 * MmSecondaryColors
* sizeof(MMCOLOR_TABLES
))
459 while (PointerPte
<= LastPte
)
461 /* Check for valid PTE */
462 if (PointerPte
->u
.Hard
.Valid
== 0)
464 /* Get a page and map it */
465 TempPte
.u
.Hard
.PageFrameNumber
= MxGetNextPage(1);
466 MI_WRITE_VALID_PTE(PointerPte
, TempPte
);
468 /* Zero out the page */
469 RtlZeroMemory(MiPteToAddress(PointerPte
), PAGE_SIZE
);
476 /* Now set the address of the next list, right after this one */
477 MmFreePagesByColor
[1] = &MmFreePagesByColor
[0][MmSecondaryColors
];
479 /* Now loop the lists to set them up */
480 for (i
= 0; i
< MmSecondaryColors
; i
++)
482 /* Set both free and zero lists for each color */
483 MmFreePagesByColor
[ZeroedPageList
][i
].Flink
= 0xFFFFFFFF;
484 MmFreePagesByColor
[ZeroedPageList
][i
].Blink
= (PVOID
)0xFFFFFFFF;
485 MmFreePagesByColor
[ZeroedPageList
][i
].Count
= 0;
486 MmFreePagesByColor
[FreePageList
][i
].Flink
= 0xFFFFFFFF;
487 MmFreePagesByColor
[FreePageList
][i
].Blink
= (PVOID
)0xFFFFFFFF;
488 MmFreePagesByColor
[FreePageList
][i
].Count
= 0;
494 MiIsRegularMemory(IN PLOADER_PARAMETER_BLOCK LoaderBlock
,
497 PLIST_ENTRY NextEntry
;
498 PMEMORY_ALLOCATION_DESCRIPTOR MdBlock
;
500 /* Loop the memory descriptors */
501 NextEntry
= LoaderBlock
->MemoryDescriptorListHead
.Flink
;
502 while (NextEntry
!= &LoaderBlock
->MemoryDescriptorListHead
)
504 /* Get the memory descriptor */
505 MdBlock
= CONTAINING_RECORD(NextEntry
,
506 MEMORY_ALLOCATION_DESCRIPTOR
,
509 /* Check if this PFN could be part of the block */
510 if (Pfn
>= (MdBlock
->BasePage
))
512 /* Check if it really is part of the block */
513 if (Pfn
< (MdBlock
->BasePage
+ MdBlock
->PageCount
))
515 /* Check if the block is actually memory we don't map */
516 if ((MdBlock
->MemoryType
== LoaderFirmwarePermanent
) ||
517 (MdBlock
->MemoryType
== LoaderBBTMemory
) ||
518 (MdBlock
->MemoryType
== LoaderSpecialMemory
))
520 /* We don't need PFN database entries for this memory */
524 /* This is memory we want to map */
530 /* Blocks are ordered, so if it's not here, it doesn't exist */
534 /* Get to the next descriptor */
535 NextEntry
= MdBlock
->ListEntry
.Flink
;
538 /* Check if this PFN is actually from our free memory descriptor */
539 if ((Pfn
>= MxOldFreeDescriptor
.BasePage
) &&
540 (Pfn
< MxOldFreeDescriptor
.BasePage
+ MxOldFreeDescriptor
.PageCount
))
542 /* We use these pages for initial mappings, so we do want to count them */
546 /* Otherwise this isn't memory that we describe or care about */
552 MiMapPfnDatabase(IN PLOADER_PARAMETER_BLOCK LoaderBlock
)
554 ULONG FreePage
, FreePageCount
, PagesLeft
, BasePage
, PageCount
;
555 PLIST_ENTRY NextEntry
;
556 PMEMORY_ALLOCATION_DESCRIPTOR MdBlock
;
557 PMMPTE PointerPte
, LastPte
;
558 MMPTE TempPte
= ValidKernelPte
;
560 /* Get current page data, since we won't be using MxGetNextPage as it would corrupt our state */
561 FreePage
= MxFreeDescriptor
->BasePage
;
562 FreePageCount
= MxFreeDescriptor
->PageCount
;
565 /* Loop the memory descriptors */
566 NextEntry
= LoaderBlock
->MemoryDescriptorListHead
.Flink
;
567 while (NextEntry
!= &LoaderBlock
->MemoryDescriptorListHead
)
569 /* Get the descriptor */
570 MdBlock
= CONTAINING_RECORD(NextEntry
,
571 MEMORY_ALLOCATION_DESCRIPTOR
,
573 if ((MdBlock
->MemoryType
== LoaderFirmwarePermanent
) ||
574 (MdBlock
->MemoryType
== LoaderBBTMemory
) ||
575 (MdBlock
->MemoryType
== LoaderSpecialMemory
))
577 /* These pages are not part of the PFN database */
578 NextEntry
= MdBlock
->ListEntry
.Flink
;
582 /* Next, check if this is our special free descriptor we've found */
583 if (MdBlock
== MxFreeDescriptor
)
585 /* Use the real numbers instead */
586 BasePage
= MxOldFreeDescriptor
.BasePage
;
587 PageCount
= MxOldFreeDescriptor
.PageCount
;
591 /* Use the descriptor's numbers */
592 BasePage
= MdBlock
->BasePage
;
593 PageCount
= MdBlock
->PageCount
;
596 /* Get the PTEs for this range */
597 PointerPte
= MiAddressToPte(&MmPfnDatabase
[BasePage
]);
598 LastPte
= MiAddressToPte(((ULONG_PTR
)&MmPfnDatabase
[BasePage
+ PageCount
]) - 1);
599 DPRINT("MD Type: %lx Base: %lx Count: %lx\n", MdBlock
->MemoryType
, BasePage
, PageCount
);
602 while (PointerPte
<= LastPte
)
604 /* We'll only touch PTEs that aren't already valid */
605 if (PointerPte
->u
.Hard
.Valid
== 0)
607 /* Use the next free page */
608 TempPte
.u
.Hard
.PageFrameNumber
= FreePage
;
609 ASSERT(FreePageCount
!= 0);
611 /* Consume free pages */
617 KeBugCheckEx(INSTALL_MORE_MEMORY
,
618 MmNumberOfPhysicalPages
,
620 MxOldFreeDescriptor
.PageCount
,
624 /* Write out this PTE */
626 MI_WRITE_VALID_PTE(PointerPte
, TempPte
);
629 RtlZeroMemory(MiPteToAddress(PointerPte
), PAGE_SIZE
);
636 /* Do the next address range */
637 NextEntry
= MdBlock
->ListEntry
.Flink
;
640 /* Now update the free descriptors to consume the pages we used up during the PFN allocation loop */
641 MxFreeDescriptor
->BasePage
= FreePage
;
642 MxFreeDescriptor
->PageCount
= FreePageCount
;
647 MiBuildPfnDatabaseFromPages(IN PLOADER_PARAMETER_BLOCK LoaderBlock
)
652 PFN_NUMBER PageFrameIndex
, StartupPdIndex
, PtePageIndex
;
654 ULONG_PTR BaseAddress
= 0;
656 /* PFN of the startup page directory */
657 StartupPdIndex
= PFN_FROM_PTE(MiAddressToPde(PDE_BASE
));
659 /* Start with the first PDE and scan them all */
660 PointerPde
= MiAddressToPde(NULL
);
661 Count
= PD_COUNT
* PDE_COUNT
;
662 for (i
= 0; i
< Count
; i
++)
664 /* Check for valid PDE */
665 if (PointerPde
->u
.Hard
.Valid
== 1)
667 /* Get the PFN from it */
668 PageFrameIndex
= PFN_FROM_PTE(PointerPde
);
670 /* Do we want a PFN entry for this page? */
671 if (MiIsRegularMemory(LoaderBlock
, PageFrameIndex
))
673 /* Yes we do, set it up */
674 Pfn1
= MiGetPfnEntry(PageFrameIndex
);
675 Pfn1
->u4
.PteFrame
= StartupPdIndex
;
676 Pfn1
->PteAddress
= PointerPde
;
677 Pfn1
->u2
.ShareCount
++;
678 Pfn1
->u3
.e2
.ReferenceCount
= 1;
679 Pfn1
->u3
.e1
.PageLocation
= ActiveAndValid
;
680 Pfn1
->u3
.e1
.CacheAttribute
= MiNonCached
;
688 /* Now get the PTE and scan the pages */
689 PointerPte
= MiAddressToPte(BaseAddress
);
690 for (j
= 0; j
< PTE_COUNT
; j
++)
692 /* Check for a valid PTE */
693 if (PointerPte
->u
.Hard
.Valid
== 1)
695 /* Increase the shared count of the PFN entry for the PDE */
696 ASSERT(Pfn1
!= NULL
);
697 Pfn1
->u2
.ShareCount
++;
699 /* Now check if the PTE is valid memory too */
700 PtePageIndex
= PFN_FROM_PTE(PointerPte
);
701 if (MiIsRegularMemory(LoaderBlock
, PtePageIndex
))
704 * Only add pages above the end of system code or pages
705 * that are part of nonpaged pool
707 if ((BaseAddress
>= 0xA0000000) ||
708 ((BaseAddress
>= (ULONG_PTR
)MmNonPagedPoolStart
) &&
709 (BaseAddress
< (ULONG_PTR
)MmNonPagedPoolStart
+
710 MmSizeOfNonPagedPoolInBytes
)))
712 /* Get the PFN entry and make sure it too is valid */
713 Pfn2
= MiGetPfnEntry(PtePageIndex
);
714 if ((MmIsAddressValid(Pfn2
)) &&
715 (MmIsAddressValid(Pfn2
+ 1)))
717 /* Setup the PFN entry */
718 Pfn2
->u4
.PteFrame
= PageFrameIndex
;
719 Pfn2
->PteAddress
= PointerPte
;
720 Pfn2
->u2
.ShareCount
++;
721 Pfn2
->u3
.e2
.ReferenceCount
= 1;
722 Pfn2
->u3
.e1
.PageLocation
= ActiveAndValid
;
723 Pfn2
->u3
.e1
.CacheAttribute
= MiNonCached
;
731 BaseAddress
+= PAGE_SIZE
;
736 /* Next PDE mapped address */
737 BaseAddress
+= PDE_MAPPED_VA
;
747 MiBuildPfnDatabaseZeroPage(VOID
)
752 /* Grab the lowest page and check if it has no real references */
753 Pfn1
= MiGetPfnEntry(MmLowestPhysicalPage
);
754 if (!(MmLowestPhysicalPage
) && !(Pfn1
->u3
.e2
.ReferenceCount
))
756 /* Make it a bogus page to catch errors */
757 PointerPde
= MiAddressToPde(0xFFFFFFFF);
758 Pfn1
->u4
.PteFrame
= PFN_FROM_PTE(PointerPde
);
759 Pfn1
->PteAddress
= PointerPde
;
760 Pfn1
->u2
.ShareCount
++;
761 Pfn1
->u3
.e2
.ReferenceCount
= 0xFFF0;
762 Pfn1
->u3
.e1
.PageLocation
= ActiveAndValid
;
763 Pfn1
->u3
.e1
.CacheAttribute
= MiNonCached
;
769 MiBuildPfnDatabaseFromLoaderBlock(IN PLOADER_PARAMETER_BLOCK LoaderBlock
)
771 PLIST_ENTRY NextEntry
;
772 PFN_NUMBER PageCount
= 0;
773 PMEMORY_ALLOCATION_DESCRIPTOR MdBlock
;
774 PFN_NUMBER PageFrameIndex
;
780 /* Now loop through the descriptors */
781 NextEntry
= LoaderBlock
->MemoryDescriptorListHead
.Flink
;
782 while (NextEntry
!= &LoaderBlock
->MemoryDescriptorListHead
)
784 /* Get the current descriptor */
785 MdBlock
= CONTAINING_RECORD(NextEntry
,
786 MEMORY_ALLOCATION_DESCRIPTOR
,
790 PageCount
= MdBlock
->PageCount
;
791 PageFrameIndex
= MdBlock
->BasePage
;
793 /* Don't allow memory above what the PFN database is mapping */
794 if (PageFrameIndex
> MmHighestPhysicalPage
)
796 /* Since they are ordered, everything past here will be larger */
800 /* On the other hand, the end page might be higher up... */
801 if ((PageFrameIndex
+ PageCount
) > (MmHighestPhysicalPage
+ 1))
803 /* In which case we'll trim the descriptor to go as high as we can */
804 PageCount
= MmHighestPhysicalPage
+ 1 - PageFrameIndex
;
805 MdBlock
->PageCount
= PageCount
;
807 /* But if there's nothing left to trim, we got too high, so quit */
808 if (!PageCount
) break;
811 /* Now check the descriptor type */
812 switch (MdBlock
->MemoryType
)
814 /* Check for bad RAM */
817 DPRINT1("You either have specified /BURNMEMORY or damaged RAM modules.\n");
820 /* Check for free RAM */
822 case LoaderLoadedProgram
:
823 case LoaderFirmwareTemporary
:
824 case LoaderOsloaderStack
:
826 /* Get the last page of this descriptor. Note we loop backwards */
827 PageFrameIndex
+= PageCount
- 1;
828 Pfn1
= MiGetPfnEntry(PageFrameIndex
);
830 /* Lock the PFN Database */
831 OldIrql
= KeAcquireQueuedSpinLock(LockQueuePfnLock
);
834 /* If the page really has no references, mark it as free */
835 if (!Pfn1
->u3
.e2
.ReferenceCount
)
837 /* Add it to the free list */
838 Pfn1
->u3
.e1
.CacheAttribute
= MiNonCached
;
839 MiInsertPageInFreeList(PageFrameIndex
);
842 /* Go to the next page */
847 /* Release PFN database */
848 KeReleaseQueuedSpinLock(LockQueuePfnLock
, OldIrql
);
850 /* Done with this block */
853 /* Check for pages that are invisible to us */
854 case LoaderFirmwarePermanent
:
855 case LoaderSpecialMemory
:
856 case LoaderBBTMemory
:
863 /* Map these pages with the KSEG0 mapping that adds 0x80000000 */
864 PointerPte
= MiAddressToPte(KSEG0_BASE
+ (PageFrameIndex
<< PAGE_SHIFT
));
865 Pfn1
= MiGetPfnEntry(PageFrameIndex
);
868 /* Check if the page is really unused */
869 PointerPde
= MiAddressToPde(KSEG0_BASE
+ (PageFrameIndex
<< PAGE_SHIFT
));
870 if (!Pfn1
->u3
.e2
.ReferenceCount
)
872 /* Mark it as being in-use */
873 Pfn1
->u4
.PteFrame
= PFN_FROM_PTE(PointerPde
);
874 Pfn1
->PteAddress
= PointerPte
;
875 Pfn1
->u2
.ShareCount
++;
876 Pfn1
->u3
.e2
.ReferenceCount
= 1;
877 Pfn1
->u3
.e1
.PageLocation
= ActiveAndValid
;
878 Pfn1
->u3
.e1
.CacheAttribute
= MiNonCached
;
880 /* Check for RAM disk page */
881 if (MdBlock
->MemoryType
== LoaderXIPRom
)
883 /* Make it a pseudo-I/O ROM mapping */
885 Pfn1
->u2
.ShareCount
= 0;
886 Pfn1
->u3
.e2
.ReferenceCount
= 0;
887 Pfn1
->u3
.e1
.PageLocation
= 0;
889 Pfn1
->u4
.InPageError
= 0;
890 Pfn1
->u3
.e1
.PrototypePte
= 1;
894 /* Advance page structures */
902 /* Next descriptor entry */
903 NextEntry
= MdBlock
->ListEntry
.Flink
;
909 MiBuildPfnDatabaseSelf(VOID
)
911 PMMPTE PointerPte
, LastPte
;
914 /* Loop the PFN database page */
915 PointerPte
= MiAddressToPte(MiGetPfnEntry(MmLowestPhysicalPage
));
916 LastPte
= MiAddressToPte(MiGetPfnEntry(MmHighestPhysicalPage
));
917 while (PointerPte
<= LastPte
)
919 /* Make sure the page is valid */
920 if (PointerPte
->u
.Hard
.Valid
== 1)
922 /* Get the PFN entry and just mark it referenced */
923 Pfn1
= MiGetPfnEntry(PointerPte
->u
.Hard
.PageFrameNumber
);
924 Pfn1
->u2
.ShareCount
= 1;
925 Pfn1
->u3
.e2
.ReferenceCount
= 1;
935 MiInitializePfnDatabase(IN PLOADER_PARAMETER_BLOCK LoaderBlock
)
937 /* Scan memory and start setting up PFN entries */
938 MiBuildPfnDatabaseFromPages(LoaderBlock
);
940 /* Add the zero page */
941 MiBuildPfnDatabaseZeroPage();
943 /* Scan the loader block and build the rest of the PFN database */
944 MiBuildPfnDatabaseFromLoaderBlock(LoaderBlock
);
946 /* Finally add the pages for the PFN database itself */
947 MiBuildPfnDatabaseSelf();
952 MiAdjustWorkingSetManagerParameters(IN BOOLEAN Client
)
954 /* This function needs to do more work, for now, we tune page minimums */
956 /* Check for a system with around 64MB RAM or more */
957 if (MmNumberOfPhysicalPages
>= (63 * _1MB
) / PAGE_SIZE
)
959 /* Double the minimum amount of pages we consider for a "plenty free" scenario */
960 MmPlentyFreePages
*= 2;
966 MiNotifyMemoryEvents(VOID
)
968 /* Are we in a low-memory situation? */
969 if (MmAvailablePages
< MmLowMemoryThreshold
)
971 /* Clear high, set low */
972 if (KeReadStateEvent(MiHighMemoryEvent
)) KeClearEvent(MiHighMemoryEvent
);
973 if (!KeReadStateEvent(MiLowMemoryEvent
)) KeSetEvent(MiLowMemoryEvent
, 0, FALSE
);
975 else if (MmAvailablePages
< MmHighMemoryThreshold
)
977 /* We are in between, clear both */
978 if (KeReadStateEvent(MiHighMemoryEvent
)) KeClearEvent(MiHighMemoryEvent
);
979 if (KeReadStateEvent(MiLowMemoryEvent
)) KeClearEvent(MiLowMemoryEvent
);
983 /* Clear low, set high */
984 if (KeReadStateEvent(MiLowMemoryEvent
)) KeClearEvent(MiLowMemoryEvent
);
985 if (!KeReadStateEvent(MiHighMemoryEvent
)) KeSetEvent(MiHighMemoryEvent
, 0, FALSE
);
991 MiCreateMemoryEvent(IN PUNICODE_STRING Name
,
998 OBJECT_ATTRIBUTES ObjectAttributes
;
999 SECURITY_DESCRIPTOR SecurityDescriptor
;
1002 Status
= RtlCreateSecurityDescriptor(&SecurityDescriptor
,
1003 SECURITY_DESCRIPTOR_REVISION
);
1004 if (!NT_SUCCESS(Status
)) return Status
;
1006 /* One ACL with 3 ACEs, containing each one SID */
1007 DaclLength
= sizeof(ACL
) +
1008 3 * sizeof(ACCESS_ALLOWED_ACE
) +
1009 RtlLengthSid(SeLocalSystemSid
) +
1010 RtlLengthSid(SeAliasAdminsSid
) +
1011 RtlLengthSid(SeWorldSid
);
1013 /* Allocate space for the DACL */
1014 Dacl
= ExAllocatePoolWithTag(PagedPool
, DaclLength
, 'lcaD');
1015 if (!Dacl
) return STATUS_INSUFFICIENT_RESOURCES
;
1017 /* Setup the ACL inside it */
1018 Status
= RtlCreateAcl(Dacl
, DaclLength
, ACL_REVISION
);
1019 if (!NT_SUCCESS(Status
)) goto CleanUp
;
1021 /* Add query rights for everyone */
1022 Status
= RtlAddAccessAllowedAce(Dacl
,
1024 SYNCHRONIZE
| EVENT_QUERY_STATE
| READ_CONTROL
,
1026 if (!NT_SUCCESS(Status
)) goto CleanUp
;
1028 /* Full rights for the admin */
1029 Status
= RtlAddAccessAllowedAce(Dacl
,
1033 if (!NT_SUCCESS(Status
)) goto CleanUp
;
1035 /* As well as full rights for the system */
1036 Status
= RtlAddAccessAllowedAce(Dacl
,
1040 if (!NT_SUCCESS(Status
)) goto CleanUp
;
1042 /* Set this DACL inside the SD */
1043 Status
= RtlSetDaclSecurityDescriptor(&SecurityDescriptor
,
1047 if (!NT_SUCCESS(Status
)) goto CleanUp
;
1049 /* Setup the event attributes, making sure it's a permanent one */
1050 InitializeObjectAttributes(&ObjectAttributes
,
1052 OBJ_KERNEL_HANDLE
| OBJ_PERMANENT
,
1054 &SecurityDescriptor
);
1056 /* Create the event */
1057 Status
= ZwCreateEvent(&EventHandle
,
1066 /* Check if this is the success path */
1067 if (NT_SUCCESS(Status
))
1069 /* Add a reference to the object, then close the handle we had */
1070 Status
= ObReferenceObjectByHandle(EventHandle
,
1076 ZwClose (EventHandle
);
1085 MiInitializeMemoryEvents(VOID
)
1087 UNICODE_STRING LowString
= RTL_CONSTANT_STRING(L
"\\KernelObjects\\LowMemoryCondition");
1088 UNICODE_STRING HighString
= RTL_CONSTANT_STRING(L
"\\KernelObjects\\HighMemoryCondition");
1089 UNICODE_STRING LowPagedPoolString
= RTL_CONSTANT_STRING(L
"\\KernelObjects\\LowPagedPoolCondition");
1090 UNICODE_STRING HighPagedPoolString
= RTL_CONSTANT_STRING(L
"\\KernelObjects\\HighPagedPoolCondition");
1091 UNICODE_STRING LowNonPagedPoolString
= RTL_CONSTANT_STRING(L
"\\KernelObjects\\LowNonPagedPoolCondition");
1092 UNICODE_STRING HighNonPagedPoolString
= RTL_CONSTANT_STRING(L
"\\KernelObjects\\HighNonPagedPoolCondition");
1095 /* Check if we have a registry setting */
1096 if (MmLowMemoryThreshold
)
1098 /* Convert it to pages */
1099 MmLowMemoryThreshold
*= (_1MB
/ PAGE_SIZE
);
1103 /* The low memory threshold is hit when we don't consider that we have "plenty" of free pages anymore */
1104 MmLowMemoryThreshold
= MmPlentyFreePages
;
1106 /* More than one GB of memory? */
1107 if (MmNumberOfPhysicalPages
> 0x40000)
1109 /* Start at 32MB, and add another 16MB for each GB */
1110 MmLowMemoryThreshold
= (32 * _1MB
) / PAGE_SIZE
;
1111 MmLowMemoryThreshold
+= ((MmNumberOfPhysicalPages
- 0x40000) >> 7);
1113 else if (MmNumberOfPhysicalPages
> 0x8000)
1115 /* For systems with > 128MB RAM, add another 4MB for each 128MB */
1116 MmLowMemoryThreshold
+= ((MmNumberOfPhysicalPages
- 0x8000) >> 5);
1119 /* Don't let the minimum threshold go past 64MB */
1120 MmLowMemoryThreshold
= min(MmLowMemoryThreshold
, (64 * _1MB
) / PAGE_SIZE
);
1123 /* Check if we have a registry setting */
1124 if (MmHighMemoryThreshold
)
1126 /* Convert it into pages */
1127 MmHighMemoryThreshold
*= (_1MB
/ PAGE_SIZE
);
1131 /* Otherwise, the default is three times the low memory threshold */
1132 MmHighMemoryThreshold
= 3 * MmLowMemoryThreshold
;
1133 ASSERT(MmHighMemoryThreshold
> MmLowMemoryThreshold
);
1136 /* Make sure high threshold is actually higher than the low */
1137 MmHighMemoryThreshold
= max(MmHighMemoryThreshold
, MmLowMemoryThreshold
);
1139 /* Create the memory events for all the thresholds */
1140 Status
= MiCreateMemoryEvent(&LowString
, &MiLowMemoryEvent
);
1141 if (!NT_SUCCESS(Status
)) return FALSE
;
1142 Status
= MiCreateMemoryEvent(&HighString
, &MiHighMemoryEvent
);
1143 if (!NT_SUCCESS(Status
)) return FALSE
;
1144 Status
= MiCreateMemoryEvent(&LowPagedPoolString
, &MiLowPagedPoolEvent
);
1145 if (!NT_SUCCESS(Status
)) return FALSE
;
1146 Status
= MiCreateMemoryEvent(&HighPagedPoolString
, &MiHighPagedPoolEvent
);
1147 if (!NT_SUCCESS(Status
)) return FALSE
;
1148 Status
= MiCreateMemoryEvent(&LowNonPagedPoolString
, &MiLowNonPagedPoolEvent
);
1149 if (!NT_SUCCESS(Status
)) return FALSE
;
1150 Status
= MiCreateMemoryEvent(&HighNonPagedPoolString
, &MiHighNonPagedPoolEvent
);
1151 if (!NT_SUCCESS(Status
)) return FALSE
;
1153 /* Now setup the pool events */
1154 MiInitializePoolEvents();
1156 /* Set the initial event state */
1157 MiNotifyMemoryEvents();
1163 MiAddHalIoMappings(VOID
)
1168 ULONG i
, j
, PdeCount
;
1169 PFN_NUMBER PageFrameIndex
;
1171 /* HAL Heap address -- should be on a PDE boundary */
1172 BaseAddress
= (PVOID
)0xFFC00000;
1173 ASSERT(MiAddressToPteOffset(BaseAddress
) == 0);
1175 /* Check how many PDEs the heap has */
1176 PointerPde
= MiAddressToPde(BaseAddress
);
1177 PdeCount
= PDE_COUNT
- ADDR_TO_PDE_OFFSET(BaseAddress
);
1178 for (i
= 0; i
< PdeCount
; i
++)
1180 /* Does the HAL own this mapping? */
1181 if ((PointerPde
->u
.Hard
.Valid
== 1) &&
1182 (PointerPde
->u
.Hard
.LargePage
== 0))
1184 /* Get the PTE for it and scan each page */
1185 PointerPte
= MiAddressToPte(BaseAddress
);
1186 for (j
= 0 ; j
< PTE_COUNT
; j
++)
1188 /* Does the HAL own this page? */
1189 if (PointerPte
->u
.Hard
.Valid
== 1)
1191 /* Is the HAL using it for device or I/O mapped memory? */
1192 PageFrameIndex
= PFN_FROM_PTE(PointerPte
);
1193 if (!MiGetPfnEntry(PageFrameIndex
))
1195 /* FIXME: For PAT, we need to track I/O cache attributes for coherency */
1196 DPRINT1("HAL I/O Mapping at %p is unsafe\n", BaseAddress
);
1200 /* Move to the next page */
1201 BaseAddress
= (PVOID
)((ULONG_PTR
)BaseAddress
+ PAGE_SIZE
);
1207 /* Move to the next address */
1208 BaseAddress
= (PVOID
)((ULONG_PTR
)BaseAddress
+ PDE_MAPPED_VA
);
1211 /* Move to the next PDE */
1218 MmDumpArmPfnDatabase(VOID
)
1222 PCHAR Consumer
= "Unknown";
1224 ULONG ActivePages
= 0, FreePages
= 0, OtherPages
= 0;
1226 KeRaiseIrql(HIGH_LEVEL
, &OldIrql
);
1229 // Loop the PFN database
1231 for (i
= 0; i
<= MmHighestPhysicalPage
; i
++)
1233 Pfn1
= MiGetPfnEntry(i
);
1234 if (!Pfn1
) continue;
1237 // Get the page location
1239 switch (Pfn1
->u3
.e1
.PageLocation
)
1241 case ActiveAndValid
:
1243 Consumer
= "Active and Valid";
1249 Consumer
= "Free Page List";
1255 Consumer
= "Other (ASSERT!)";
1261 // Pretty-print the page
1263 DbgPrint("0x%08p:\t%20s\t(%02d.%02d) [%08p-%08p])\n",
1266 Pfn1
->u3
.e2
.ReferenceCount
,
1267 Pfn1
->u2
.ShareCount
,
1272 DbgPrint("Active: %d pages\t[%d KB]\n", ActivePages
, (ActivePages
<< PAGE_SHIFT
) / 1024);
1273 DbgPrint("Free: %d pages\t[%d KB]\n", FreePages
, (FreePages
<< PAGE_SHIFT
) / 1024);
1274 DbgPrint("Other: %d pages\t[%d KB]\n", OtherPages
, (OtherPages
<< PAGE_SHIFT
) / 1024);
1276 KeLowerIrql(OldIrql
);
1281 MiPagesInLoaderBlock(IN PLOADER_PARAMETER_BLOCK LoaderBlock
,
1282 IN PBOOLEAN IncludeType
)
1284 PLIST_ENTRY NextEntry
;
1285 PFN_NUMBER PageCount
= 0;
1286 PMEMORY_ALLOCATION_DESCRIPTOR MdBlock
;
1289 // Now loop through the descriptors
1291 NextEntry
= LoaderBlock
->MemoryDescriptorListHead
.Flink
;
1292 while (NextEntry
!= &LoaderBlock
->MemoryDescriptorListHead
)
1295 // Grab each one, and check if it's one we should include
1297 MdBlock
= CONTAINING_RECORD(NextEntry
,
1298 MEMORY_ALLOCATION_DESCRIPTOR
,
1300 if ((MdBlock
->MemoryType
< LoaderMaximum
) &&
1301 (IncludeType
[MdBlock
->MemoryType
]))
1304 // Add this to our running total
1306 PageCount
+= MdBlock
->PageCount
;
1310 // Try the next descriptor
1312 NextEntry
= MdBlock
->ListEntry
.Flink
;
1321 PPHYSICAL_MEMORY_DESCRIPTOR
1323 MmInitializeMemoryLimits(IN PLOADER_PARAMETER_BLOCK LoaderBlock
,
1324 IN PBOOLEAN IncludeType
)
1326 PLIST_ENTRY NextEntry
;
1327 ULONG Run
= 0, InitialRuns
= 0;
1328 PFN_NUMBER NextPage
= -1, PageCount
= 0;
1329 PPHYSICAL_MEMORY_DESCRIPTOR Buffer
, NewBuffer
;
1330 PMEMORY_ALLOCATION_DESCRIPTOR MdBlock
;
1333 // Scan the memory descriptors
1335 NextEntry
= LoaderBlock
->MemoryDescriptorListHead
.Flink
;
1336 while (NextEntry
!= &LoaderBlock
->MemoryDescriptorListHead
)
1339 // For each one, increase the memory allocation estimate
1342 NextEntry
= NextEntry
->Flink
;
1346 // Allocate the maximum we'll ever need
1348 Buffer
= ExAllocatePoolWithTag(NonPagedPool
,
1349 sizeof(PHYSICAL_MEMORY_DESCRIPTOR
) +
1350 sizeof(PHYSICAL_MEMORY_RUN
) *
1353 if (!Buffer
) return NULL
;
1356 // For now that's how many runs we have
1358 Buffer
->NumberOfRuns
= InitialRuns
;
1361 // Now loop through the descriptors again
1363 NextEntry
= LoaderBlock
->MemoryDescriptorListHead
.Flink
;
1364 while (NextEntry
!= &LoaderBlock
->MemoryDescriptorListHead
)
1367 // Grab each one, and check if it's one we should include
1369 MdBlock
= CONTAINING_RECORD(NextEntry
,
1370 MEMORY_ALLOCATION_DESCRIPTOR
,
1372 if ((MdBlock
->MemoryType
< LoaderMaximum
) &&
1373 (IncludeType
[MdBlock
->MemoryType
]))
1376 // Add this to our running total
1378 PageCount
+= MdBlock
->PageCount
;
1381 // Check if the next page is described by the next descriptor
1383 if (MdBlock
->BasePage
== NextPage
)
1386 // Combine it into the same physical run
1388 ASSERT(MdBlock
->PageCount
!= 0);
1389 Buffer
->Run
[Run
- 1].PageCount
+= MdBlock
->PageCount
;
1390 NextPage
+= MdBlock
->PageCount
;
1395 // Otherwise just duplicate the descriptor's contents
1397 Buffer
->Run
[Run
].BasePage
= MdBlock
->BasePage
;
1398 Buffer
->Run
[Run
].PageCount
= MdBlock
->PageCount
;
1399 NextPage
= Buffer
->Run
[Run
].BasePage
+ Buffer
->Run
[Run
].PageCount
;
1402 // And in this case, increase the number of runs
1409 // Try the next descriptor
1411 NextEntry
= MdBlock
->ListEntry
.Flink
;
1415 // We should not have been able to go past our initial estimate
1417 ASSERT(Run
<= Buffer
->NumberOfRuns
);
1420 // Our guess was probably exaggerated...
1422 if (InitialRuns
> Run
)
1425 // Allocate a more accurately sized buffer
1427 NewBuffer
= ExAllocatePoolWithTag(NonPagedPool
,
1428 sizeof(PHYSICAL_MEMORY_DESCRIPTOR
) +
1429 sizeof(PHYSICAL_MEMORY_RUN
) *
1435 // Copy the old buffer into the new, then free it
1437 RtlCopyMemory(NewBuffer
->Run
,
1439 sizeof(PHYSICAL_MEMORY_RUN
) * Run
);
1443 // Now use the new buffer
1450 // Write the final numbers, and return it
1452 Buffer
->NumberOfRuns
= Run
;
1453 Buffer
->NumberOfPages
= PageCount
;
1459 MiBuildPagedPool(VOID
)
1461 PMMPTE PointerPte
, PointerPde
;
1462 MMPTE TempPte
= ValidKernelPte
;
1463 PFN_NUMBER PageFrameIndex
;
1465 ULONG Size
, BitMapSize
;
1466 #if (_MI_PAGING_LEVELS == 2)
1468 // Get the page frame number for the system page directory
1470 PointerPte
= MiAddressToPte(PDE_BASE
);
1471 ASSERT(PD_COUNT
== 1);
1472 MmSystemPageDirectory
[0] = PFN_FROM_PTE(PointerPte
);
1475 // Allocate a system PTE which will hold a copy of the page directory
1477 PointerPte
= MiReserveSystemPtes(1, SystemPteSpace
);
1479 MmSystemPagePtes
= MiPteToAddress(PointerPte
);
1482 // Make this system PTE point to the system page directory.
1483 // It is now essentially double-mapped. This will be used later for lazy
1484 // evaluation of PDEs accross process switches, similarly to how the Global
1485 // page directory array in the old ReactOS Mm is used (but in a less hacky
1488 TempPte
= ValidKernelPte
;
1489 ASSERT(PD_COUNT
== 1);
1490 TempPte
.u
.Hard
.PageFrameNumber
= MmSystemPageDirectory
[0];
1491 MI_WRITE_VALID_PTE(PointerPte
, TempPte
);
1494 // Let's get back to paged pool work: size it up.
1495 // By default, it should be twice as big as nonpaged pool.
1497 MmSizeOfPagedPoolInBytes
= 2 * MmMaximumNonPagedPoolInBytes
;
1498 if (MmSizeOfPagedPoolInBytes
> ((ULONG_PTR
)MmNonPagedSystemStart
-
1499 (ULONG_PTR
)MmPagedPoolStart
))
1502 // On the other hand, we have limited VA space, so make sure that the VA
1503 // for paged pool doesn't overflow into nonpaged pool VA. Otherwise, set
1504 // whatever maximum is possible.
1506 MmSizeOfPagedPoolInBytes
= (ULONG_PTR
)MmNonPagedSystemStart
-
1507 (ULONG_PTR
)MmPagedPoolStart
;
1511 // Get the size in pages and make sure paged pool is at least 32MB.
1513 Size
= MmSizeOfPagedPoolInBytes
;
1514 if (Size
< MI_MIN_INIT_PAGED_POOLSIZE
) Size
= MI_MIN_INIT_PAGED_POOLSIZE
;
1515 Size
= BYTES_TO_PAGES(Size
);
1518 // Now check how many PTEs will be required for these many pages.
1520 Size
= (Size
+ (1024 - 1)) / 1024;
1523 // Recompute the page-aligned size of the paged pool, in bytes and pages.
1525 MmSizeOfPagedPoolInBytes
= Size
* PAGE_SIZE
* 1024;
1526 MmSizeOfPagedPoolInPages
= MmSizeOfPagedPoolInBytes
>> PAGE_SHIFT
;
1529 // Let's be really sure this doesn't overflow into nonpaged system VA
1531 ASSERT((MmSizeOfPagedPoolInBytes
+ (ULONG_PTR
)MmPagedPoolStart
) <=
1532 (ULONG_PTR
)MmNonPagedSystemStart
);
1535 // This is where paged pool ends
1537 MmPagedPoolEnd
= (PVOID
)(((ULONG_PTR
)MmPagedPoolStart
+
1538 MmSizeOfPagedPoolInBytes
) - 1);
1541 // So now get the PDE for paged pool and zero it out
1543 PointerPde
= MiAddressToPde(MmPagedPoolStart
);
1545 #if (_MI_PAGING_LEVELS >= 3)
1546 /* On these systems, there's no double-mapping, so instead, the PPE and PXEs
1547 * are setup to span the entire paged pool area, so there's no need for the
1552 RtlZeroMemory(PointerPde
,
1553 (1 + MiAddressToPde(MmPagedPoolEnd
) - PointerPde
) * sizeof(MMPTE
));
1556 // Next, get the first and last PTE
1558 PointerPte
= MiAddressToPte(MmPagedPoolStart
);
1559 MmPagedPoolInfo
.FirstPteForPagedPool
= PointerPte
;
1560 MmPagedPoolInfo
.LastPteForPagedPool
= MiAddressToPte(MmPagedPoolEnd
);
1563 // Lock the PFN database
1565 OldIrql
= KeAcquireQueuedSpinLock(LockQueuePfnLock
);
1567 /* Allocate a page and map the first paged pool PDE */
1568 PageFrameIndex
= MiRemoveZeroPage(0);
1569 TempPte
.u
.Hard
.PageFrameNumber
= PageFrameIndex
;
1570 MI_WRITE_VALID_PTE(PointerPde
, TempPte
);
1571 #if (_MI_PAGING_LEVELS >= 3)
1572 /* Use the PPE of MmPagedPoolStart that was setup above */
1573 // Bla = PFN_FROM_PTE(PpeAddress(MmPagedPool...));
1576 /* Do it this way */
1577 // Bla = MmSystemPageDirectory[(PointerPde - (PMMPTE)PDE_BASE) / PDE_COUNT]
1579 /* Initialize the PFN entry for it */
1580 MiInitializePfnForOtherProcess(PageFrameIndex
,
1582 MmSystemPageDirectory
[(PointerPde
- (PMMPTE
)PDE_BASE
) / PDE_COUNT
]);
1586 // Release the PFN database lock
1588 KeReleaseQueuedSpinLock(LockQueuePfnLock
, OldIrql
);
1591 // We only have one PDE mapped for now... at fault time, additional PDEs
1592 // will be allocated to handle paged pool growth. This is where they'll have
1595 MmPagedPoolInfo
.NextPdeForPagedPoolExpansion
= PointerPde
+ 1;
1598 // We keep track of each page via a bit, so check how big the bitmap will
1599 // have to be (make sure to align our page count such that it fits nicely
1600 // into a 4-byte aligned bitmap.
1602 // We'll also allocate the bitmap header itself part of the same buffer.
1605 ASSERT(Size
== MmSizeOfPagedPoolInPages
);
1607 Size
= sizeof(RTL_BITMAP
) + (((Size
+ 31) / 32) * sizeof(ULONG
));
1610 // Allocate the allocation bitmap, which tells us which regions have not yet
1611 // been mapped into memory
1613 MmPagedPoolInfo
.PagedPoolAllocationMap
= ExAllocatePoolWithTag(NonPagedPool
,
1616 ASSERT(MmPagedPoolInfo
.PagedPoolAllocationMap
);
1619 // Initialize it such that at first, only the first page's worth of PTEs is
1620 // marked as allocated (incidentially, the first PDE we allocated earlier).
1622 RtlInitializeBitMap(MmPagedPoolInfo
.PagedPoolAllocationMap
,
1623 (PULONG
)(MmPagedPoolInfo
.PagedPoolAllocationMap
+ 1),
1625 RtlSetAllBits(MmPagedPoolInfo
.PagedPoolAllocationMap
);
1626 RtlClearBits(MmPagedPoolInfo
.PagedPoolAllocationMap
, 0, 1024);
1629 // We have a second bitmap, which keeps track of where allocations end.
1630 // Given the allocation bitmap and a base address, we can therefore figure
1631 // out which page is the last page of that allocation, and thus how big the
1632 // entire allocation is.
1634 MmPagedPoolInfo
.EndOfPagedPoolBitmap
= ExAllocatePoolWithTag(NonPagedPool
,
1637 ASSERT(MmPagedPoolInfo
.EndOfPagedPoolBitmap
);
1638 RtlInitializeBitMap(MmPagedPoolInfo
.EndOfPagedPoolBitmap
,
1639 (PULONG
)(MmPagedPoolInfo
.EndOfPagedPoolBitmap
+ 1),
1643 // Since no allocations have been made yet, there are no bits set as the end
1645 RtlClearAllBits(MmPagedPoolInfo
.EndOfPagedPoolBitmap
);
1648 // Initialize paged pool.
1650 InitializePool(PagedPool
, 0);
1652 /* Default low threshold of 30MB or one fifth of paged pool */
1653 MiLowPagedPoolThreshold
= (30 * _1MB
) >> PAGE_SHIFT
;
1654 MiLowPagedPoolThreshold
= min(MiLowPagedPoolThreshold
, Size
/ 5);
1656 /* Default high threshold of 60MB or 25% */
1657 MiHighPagedPoolThreshold
= (60 * _1MB
) >> PAGE_SHIFT
;
1658 MiHighPagedPoolThreshold
= min(MiHighPagedPoolThreshold
, (Size
* 2) / 5);
1659 ASSERT(MiLowPagedPoolThreshold
< MiHighPagedPoolThreshold
);
1661 /* Setup the global session space */
1662 MiInitializeSystemSpaceMap(NULL
);
1667 MiDbgDumpMemoryDescriptors(VOID
)
1669 PLIST_ENTRY NextEntry
;
1670 PMEMORY_ALLOCATION_DESCRIPTOR Md
;
1671 ULONG TotalPages
= 0;
1680 "FirmwareTemporary ",
1681 "FirmwarePermanent ",
1688 "ConsoleOutDriver ",
1690 "StartupKernelStack",
1691 "StartupPanicStack ",
1703 DPRINT1("Base\t\tLength\t\tType\n");
1704 for (NextEntry
= KeLoaderBlock
->MemoryDescriptorListHead
.Flink
;
1705 NextEntry
!= &KeLoaderBlock
->MemoryDescriptorListHead
;
1706 NextEntry
= NextEntry
->Flink
)
1708 Md
= CONTAINING_RECORD(NextEntry
, MEMORY_ALLOCATION_DESCRIPTOR
, ListEntry
);
1709 DPRINT1("%08lX\t%08lX\t%s\n", Md
->BasePage
, Md
->PageCount
, MemType
[Md
->MemoryType
]);
1710 TotalPages
+= Md
->PageCount
;
1713 DPRINT1("Total: %08lX (%d MB)\n", TotalPages
, (TotalPages
* PAGE_SIZE
) / 1024 / 1024);
1718 MmArmInitSystem(IN ULONG Phase
,
1719 IN PLOADER_PARAMETER_BLOCK LoaderBlock
)
1722 BOOLEAN IncludeType
[LoaderMaximum
];
1724 PPHYSICAL_MEMORY_RUN Run
;
1725 PFN_NUMBER PageCount
;
1727 /* Dump memory descriptors */
1728 if (MiDbgEnableMdDump
) MiDbgDumpMemoryDescriptors();
1731 // Instantiate memory that we don't consider RAM/usable
1732 // We use the same exclusions that Windows does, in order to try to be
1733 // compatible with WinLDR-style booting
1735 for (i
= 0; i
< LoaderMaximum
; i
++) IncludeType
[i
] = TRUE
;
1736 IncludeType
[LoaderBad
] = FALSE
;
1737 IncludeType
[LoaderFirmwarePermanent
] = FALSE
;
1738 IncludeType
[LoaderSpecialMemory
] = FALSE
;
1739 IncludeType
[LoaderBBTMemory
] = FALSE
;
1742 /* Initialize the phase 0 temporary event */
1743 KeInitializeEvent(&MiTempEvent
, NotificationEvent
, FALSE
);
1745 /* Set all the events to use the temporary event for now */
1746 MiLowMemoryEvent
= &MiTempEvent
;
1747 MiHighMemoryEvent
= &MiTempEvent
;
1748 MiLowPagedPoolEvent
= &MiTempEvent
;
1749 MiHighPagedPoolEvent
= &MiTempEvent
;
1750 MiLowNonPagedPoolEvent
= &MiTempEvent
;
1751 MiHighNonPagedPoolEvent
= &MiTempEvent
;
1754 // Define the basic user vs. kernel address space separation
1756 MmSystemRangeStart
= (PVOID
)KSEG0_BASE
;
1757 MmUserProbeAddress
= (ULONG_PTR
)MmSystemRangeStart
- 0x10000;
1758 MmHighestUserAddress
= (PVOID
)(MmUserProbeAddress
- 1);
1760 /* Highest PTE and PDE based on the addresses above */
1761 MiHighestUserPte
= MiAddressToPte(MmHighestUserAddress
);
1762 MiHighestUserPde
= MiAddressToPde(MmHighestUserAddress
);
1763 #if (_MI_PAGING_LEVELS >= 3)
1764 /* We need the highest PPE and PXE addresses */
1768 // Get the size of the boot loader's image allocations and then round
1769 // that region up to a PDE size, so that any PDEs we might create for
1770 // whatever follows are separate from the PDEs that boot loader might've
1771 // already created (and later, we can blow all that away if we want to).
1773 MmBootImageSize
= KeLoaderBlock
->Extension
->LoaderPagesSpanned
;
1774 MmBootImageSize
*= PAGE_SIZE
;
1775 MmBootImageSize
= (MmBootImageSize
+ PDE_MAPPED_VA
- 1) & ~(PDE_MAPPED_VA
- 1);
1776 ASSERT((MmBootImageSize
% PDE_MAPPED_VA
) == 0);
1779 // Set the size of session view, pool, and image
1781 MmSessionSize
= MI_SESSION_SIZE
;
1782 MmSessionViewSize
= MI_SESSION_VIEW_SIZE
;
1783 MmSessionPoolSize
= MI_SESSION_POOL_SIZE
;
1784 MmSessionImageSize
= MI_SESSION_IMAGE_SIZE
;
1787 // Set the size of system view
1789 MmSystemViewSize
= MI_SYSTEM_VIEW_SIZE
;
1792 // This is where it all ends
1794 MiSessionImageEnd
= (PVOID
)PTE_BASE
;
1797 // This is where we will load Win32k.sys and the video driver
1799 MiSessionImageStart
= (PVOID
)((ULONG_PTR
)MiSessionImageEnd
-
1800 MmSessionImageSize
);
1803 // So the view starts right below the session working set (itself below
1806 MiSessionViewStart
= (PVOID
)((ULONG_PTR
)MiSessionImageEnd
-
1807 MmSessionImageSize
-
1808 MI_SESSION_WORKING_SET_SIZE
-
1812 // Session pool follows
1814 MiSessionPoolEnd
= MiSessionViewStart
;
1815 MiSessionPoolStart
= (PVOID
)((ULONG_PTR
)MiSessionPoolEnd
-
1819 // And it all begins here
1821 MmSessionBase
= MiSessionPoolStart
;
1824 // Sanity check that our math is correct
1826 ASSERT((ULONG_PTR
)MmSessionBase
+ MmSessionSize
== PTE_BASE
);
1829 // Session space ends wherever image session space ends
1831 MiSessionSpaceEnd
= MiSessionImageEnd
;
1834 // System view space ends at session space, so now that we know where
1835 // this is, we can compute the base address of system view space itself.
1837 MiSystemViewStart
= (PVOID
)((ULONG_PTR
)MmSessionBase
-
1840 /* Compute the PTE addresses for all the addresses we carved out */
1841 MiSessionImagePteStart
= MiAddressToPte(MiSessionImageStart
);
1842 MiSessionImagePteEnd
= MiAddressToPte(MiSessionImageEnd
);
1843 MiSessionBasePte
= MiAddressToPte(MmSessionBase
);
1844 MiSessionLastPte
= MiAddressToPte(MiSessionSpaceEnd
);
1846 /* Initialize the user mode image list */
1847 InitializeListHead(&MmLoadedUserImageList
);
1849 /* Initialize the paged pool mutex */
1850 KeInitializeGuardedMutex(&MmPagedPoolMutex
);
1852 /* Initialize the Loader Lock */
1853 KeInitializeMutant(&MmSystemLoadLock
, FALSE
);
1855 /* Set the zero page event */
1856 KeInitializeEvent(&MmZeroingPageEvent
, SynchronizationEvent
, FALSE
);
1857 MmZeroingPageThreadActive
= FALSE
;
1860 // Count physical pages on the system
1862 PageCount
= MiPagesInLoaderBlock(LoaderBlock
, IncludeType
);
1865 // Check if this is a machine with less than 19MB of RAM
1867 if (PageCount
< MI_MIN_PAGES_FOR_SYSPTE_TUNING
)
1870 // Use the very minimum of system PTEs
1872 MmNumberOfSystemPtes
= 7000;
1877 // Use the default, but check if we have more than 32MB of RAM
1879 MmNumberOfSystemPtes
= 11000;
1880 if (PageCount
> MI_MIN_PAGES_FOR_SYSPTE_BOOST
)
1883 // Double the amount of system PTEs
1885 MmNumberOfSystemPtes
<<= 1;
1889 DPRINT("System PTE count has been tuned to %d (%d bytes)\n",
1890 MmNumberOfSystemPtes
, MmNumberOfSystemPtes
* PAGE_SIZE
);
1892 /* Initialize the working set lock */
1893 ExInitializePushLock((PULONG_PTR
)&MmSystemCacheWs
.WorkingSetMutex
);
1895 /* Set commit limit */
1896 MmTotalCommitLimit
= 2 * _1GB
;
1897 MmTotalCommitLimitMaximum
= MmTotalCommitLimit
;
1899 /* Has the allocation fragment been setup? */
1900 if (!MmAllocationFragment
)
1902 /* Use the default value */
1903 MmAllocationFragment
= MI_ALLOCATION_FRAGMENT
;
1904 if (PageCount
< ((256 * _1MB
) / PAGE_SIZE
))
1906 /* On memory systems with less than 256MB, divide by 4 */
1907 MmAllocationFragment
= MI_ALLOCATION_FRAGMENT
/ 4;
1909 else if (PageCount
< (_1GB
/ PAGE_SIZE
))
1911 /* On systems with less than 1GB, divide by 2 */
1912 MmAllocationFragment
= MI_ALLOCATION_FRAGMENT
/ 2;
1917 /* Convert from 1KB fragments to pages */
1918 MmAllocationFragment
*= _1KB
;
1919 MmAllocationFragment
= ROUND_TO_PAGES(MmAllocationFragment
);
1921 /* Don't let it past the maximum */
1922 MmAllocationFragment
= min(MmAllocationFragment
,
1923 MI_MAX_ALLOCATION_FRAGMENT
);
1925 /* Don't let it too small either */
1926 MmAllocationFragment
= max(MmAllocationFragment
,
1927 MI_MIN_ALLOCATION_FRAGMENT
);
1930 /* Initialize the platform-specific parts */
1931 MiInitMachineDependent(LoaderBlock
);
1934 // Build the physical memory block
1936 MmPhysicalMemoryBlock
= MmInitializeMemoryLimits(LoaderBlock
,
1940 // Allocate enough buffer for the PFN bitmap
1941 // Align it up to a 32-bit boundary
1943 Bitmap
= ExAllocatePoolWithTag(NonPagedPool
,
1944 (((MmHighestPhysicalPage
+ 1) + 31) / 32) * 4,
1951 KeBugCheckEx(INSTALL_MORE_MEMORY
,
1952 MmNumberOfPhysicalPages
,
1953 MmLowestPhysicalPage
,
1954 MmHighestPhysicalPage
,
1959 // Initialize it and clear all the bits to begin with
1961 RtlInitializeBitMap(&MiPfnBitMap
,
1963 MmHighestPhysicalPage
+ 1);
1964 RtlClearAllBits(&MiPfnBitMap
);
1967 // Loop physical memory runs
1969 for (i
= 0; i
< MmPhysicalMemoryBlock
->NumberOfRuns
; i
++)
1974 Run
= &MmPhysicalMemoryBlock
->Run
[i
];
1975 DPRINT("PHYSICAL RAM [0x%08p to 0x%08p]\n",
1976 Run
->BasePage
<< PAGE_SHIFT
,
1977 (Run
->BasePage
+ Run
->PageCount
) << PAGE_SHIFT
);
1980 // Make sure it has pages inside it
1985 // Set the bits in the PFN bitmap
1987 RtlSetBits(&MiPfnBitMap
, Run
->BasePage
, Run
->PageCount
);
1991 /* Look for large page cache entries that need caching */
1992 MiSyncCachedRanges();
1994 /* Loop for HAL Heap I/O device mappings that need coherency tracking */
1995 MiAddHalIoMappings();
1997 /* Set the initial resident page count */
1998 MmResidentAvailablePages
= MmAvailablePages
- 32;
2000 /* Initialize large page structures on PAE/x64, and MmProcessList on x86 */
2001 MiInitializeLargePageSupport();
2003 /* Check if the registry says any drivers should be loaded with large pages */
2004 MiInitializeDriverLargePageList();
2006 /* Relocate the boot drivers into system PTE space and fixup their PFNs */
2007 MiReloadBootLoadedDrivers(LoaderBlock
);
2009 /* FIXME: Call out into Driver Verifier for initialization */
2011 /* Check how many pages the system has */
2012 if (MmNumberOfPhysicalPages
<= ((13 * _1MB
) / PAGE_SIZE
))
2014 /* Set small system */
2015 MmSystemSize
= MmSmallSystem
;
2017 else if (MmNumberOfPhysicalPages
<= ((19 * _1MB
) / PAGE_SIZE
))
2019 /* Set small system and add 100 pages for the cache */
2020 MmSystemSize
= MmSmallSystem
;
2021 MmSystemCacheWsMinimum
+= 100;
2025 /* Set medium system and add 400 pages for the cache */
2026 MmSystemSize
= MmMediumSystem
;
2027 MmSystemCacheWsMinimum
+= 400;
2030 /* Check for less than 24MB */
2031 if (MmNumberOfPhysicalPages
< ((24 * _1MB
) / PAGE_SIZE
))
2033 /* No more than 32 pages */
2034 MmSystemCacheWsMinimum
= 32;
2037 /* Check for more than 32MB */
2038 if (MmNumberOfPhysicalPages
>= ((32 * _1MB
) / PAGE_SIZE
))
2040 /* Check for product type being "Wi" for WinNT */
2041 if (MmProductType
== '\0i\0W')
2043 /* Then this is a large system */
2044 MmSystemSize
= MmLargeSystem
;
2048 /* For servers, we need 64MB to consider this as being large */
2049 if (MmNumberOfPhysicalPages
>= ((64 * _1MB
) / PAGE_SIZE
))
2051 /* Set it as large */
2052 MmSystemSize
= MmLargeSystem
;
2057 /* Check for more than 33 MB */
2058 if (MmNumberOfPhysicalPages
> ((33 * _1MB
) / PAGE_SIZE
))
2060 /* Add another 500 pages to the cache */
2061 MmSystemCacheWsMinimum
+= 500;
2064 /* Now setup the shared user data fields */
2065 ASSERT(SharedUserData
->NumberOfPhysicalPages
== 0);
2066 SharedUserData
->NumberOfPhysicalPages
= MmNumberOfPhysicalPages
;
2067 SharedUserData
->LargePageMinimum
= 0;
2069 /* Check for workstation (Wi for WinNT) */
2070 if (MmProductType
== '\0i\0W')
2072 /* Set Windows NT Workstation product type */
2073 SharedUserData
->NtProductType
= NtProductWinNt
;
2078 /* Check for LanMan server */
2079 if (MmProductType
== '\0a\0L')
2081 /* This is a domain controller */
2082 SharedUserData
->NtProductType
= NtProductLanManNt
;
2086 /* Otherwise it must be a normal server */
2087 SharedUserData
->NtProductType
= NtProductServer
;
2090 /* Set the product type, and make the system more aggressive with low memory */
2092 MmMinimumFreePages
= 81;
2095 /* Update working set tuning parameters */
2096 MiAdjustWorkingSetManagerParameters(!MmProductType
);
2098 /* Finetune the page count by removing working set and NP expansion */
2099 MmResidentAvailablePages
-= MiExpansionPoolPagesInitialCharge
;
2100 MmResidentAvailablePages
-= MmSystemCacheWsMinimum
;
2101 MmResidentAvailableAtInit
= MmResidentAvailablePages
;
2102 if (MmResidentAvailablePages
<= 0)
2104 /* This should not happen */
2105 DPRINT1("System cache working set too big\n");
2109 /* Initialize the system cache */
2110 //MiInitializeSystemCache(MmSystemCacheWsMinimum, MmAvailablePages);
2112 /* Update the commit limit */
2113 MmTotalCommitLimit
= MmAvailablePages
;
2114 if (MmTotalCommitLimit
> 1024) MmTotalCommitLimit
-= 1024;
2115 MmTotalCommitLimitMaximum
= MmTotalCommitLimit
;
2117 /* Size up paged pool and build the shadow system page directory */
2120 /* Debugger physical memory support is now ready to be used */
2121 MmDebugPte
= MiAddressToPte(MiDebugMapping
);
2123 /* Initialize the loaded module list */
2124 MiInitializeLoadedModuleList(LoaderBlock
);
2128 // Always return success for now