2 * PROJECT: ReactOS Kernel
3 * LICENSE: BSD - See COPYING.ARM in the top level directory
4 * FILE: ntoskrnl/mm/ARM3/pagfault.c
5 * PURPOSE: ARM Memory Manager Page Fault Handling
6 * PROGRAMMERS: ReactOS Portable Systems Group
9 /* INCLUDES *******************************************************************/
15 #line 15 "ARMĀ³::PAGFAULT"
16 #define MODULE_INVOLVED_IN_ARM3
17 #include "../ARM3/miarm.h"
19 /* GLOBALS ********************************************************************/
21 /* PRIVATE FUNCTIONS **********************************************************/
25 MiCheckPdeForPagedPool(IN PVOID Address
)
28 NTSTATUS Status
= STATUS_SUCCESS
;
30 /* No session support in ReactOS yet */
31 ASSERT(MI_IS_SESSION_ADDRESS(Address
) == FALSE
);
32 ASSERT(MI_IS_SESSION_PTE(Address
) == FALSE
);
35 // Check if this is a fault while trying to access the page table itself
37 if ((Address
>= (PVOID
)MiAddressToPte(MmSystemRangeStart
)) &&
38 (Address
< (PVOID
)PTE_TOP
))
41 // Send a hint to the page fault handler that this is only a valid fault
42 // if we already detected this was access within the page table range
44 PointerPde
= (PMMPDE
)MiAddressToPte(Address
);
45 Status
= STATUS_WAIT_1
;
47 else if (Address
< MmSystemRangeStart
)
50 // This is totally illegal
52 return STATUS_ACCESS_VIOLATION
;
57 // Get the PDE for the address
59 PointerPde
= MiAddressToPde(Address
);
63 // Check if it's not valid
65 if (PointerPde
->u
.Hard
.Valid
== 0)
67 /* This seems to be making the assumption that one PDE is one page long */
68 ASSERT(PAGE_SIZE
== (PD_COUNT
* (sizeof(MMPTE
) * PDE_COUNT
)));
71 // Copy it from our double-mapped system page directory
73 InterlockedExchangePte(PointerPde
,
74 MmSystemPagePtes
[((ULONG_PTR
)PointerPde
&
76 sizeof(MMPTE
)].u
.Long
);
87 MiResolveDemandZeroFault(IN PVOID Address
,
92 PFN_NUMBER PageFrameNumber
;
94 DPRINT("ARM3 Demand Zero Page Fault Handler for address: %p in process: %p\n",
98 /* Must currently only be called by paging path, for system addresses only */
99 ASSERT(OldIrql
== MM_NOIRQL
);
100 ASSERT(Process
== NULL
);
103 // Lock the PFN database
105 OldIrql
= KeAcquireQueuedSpinLock(LockQueuePfnLock
);
106 ASSERT(PointerPte
->u
.Hard
.Valid
== 0);
111 PageFrameNumber
= MmAllocPage(MC_PPOOL
);
112 DPRINT("New pool page: %lx\n", PageFrameNumber
);
117 KeReleaseQueuedSpinLock(LockQueuePfnLock
, OldIrql
);
120 // Increment demand zero faults
122 InterlockedIncrement(&KeGetCurrentPrcb()->MmDemandZeroCount
);
124 /* Shouldn't see faults for user PTEs yet */
125 ASSERT(PointerPte
> MiHighestUserPte
);
130 TempPte
= ValidKernelPte
;
131 TempPte
.u
.Hard
.PageFrameNumber
= PageFrameNumber
;
132 ASSERT(TempPte
.u
.Hard
.Valid
== 1);
133 ASSERT(PointerPte
->u
.Hard
.Valid
== 0);
134 *PointerPte
= TempPte
;
135 ASSERT(PointerPte
->u
.Hard
.Valid
== 1);
140 DPRINT("Paged pool page has now been paged in\n");
141 return STATUS_PAGE_FAULT_DEMAND_ZERO
;
146 MiDispatchFault(IN BOOLEAN StoreInstruction
,
148 IN PMMPTE PointerPte
,
149 IN PMMPTE PrototypePte
,
150 IN BOOLEAN Recursive
,
151 IN PEPROCESS Process
,
152 IN PVOID TrapInformation
,
158 DPRINT("ARM3 Page Fault Dispatcher for address: %p in process: %p\n",
163 // Make sure APCs are off and we're not at dispatch
165 OldIrql
= KeGetCurrentIrql ();
166 ASSERT(OldIrql
<= APC_LEVEL
);
167 ASSERT(KeAreAllApcsDisabled () == TRUE
);
170 // Grab a copy of the PTE
172 TempPte
= *PointerPte
;
175 ASSERT(PrototypePte
== NULL
);
178 // The PTE must be invalid, but not totally blank
180 ASSERT(TempPte
.u
.Hard
.Valid
== 0);
181 ASSERT(TempPte
.u
.Long
!= 0);
184 // No prototype, transition or page file software PTEs in ARM3 yet
186 ASSERT(TempPte
.u
.Soft
.Prototype
== 0);
187 ASSERT(TempPte
.u
.Soft
.Transition
== 0);
188 ASSERT(TempPte
.u
.Soft
.PageFileHigh
== 0);
191 // If we got this far, the PTE can only be a demand zero PTE, which is what
192 // we want. Go handle it!
194 Status
= MiResolveDemandZeroFault(Address
,
198 ASSERT(KeAreAllApcsDisabled () == TRUE
);
199 if (NT_SUCCESS(Status
))
202 // Make sure we're returning in a sane state and pass the status down
204 ASSERT(OldIrql
== KeGetCurrentIrql ());
205 ASSERT(KeGetCurrentIrql() <= APC_LEVEL
);
210 // Generate an access fault
212 return STATUS_ACCESS_VIOLATION
;
217 MmArmAccessFault(IN BOOLEAN StoreInstruction
,
219 IN KPROCESSOR_MODE Mode
,
220 IN PVOID TrapInformation
)
222 KIRQL OldIrql
= KeGetCurrentIrql(), LockIrql
;
226 PETHREAD CurrentThread
;
228 DPRINT("ARM3 FAULT AT: %p\n", Address
);
231 // Get the PTE and PDE
233 PointerPte
= MiAddressToPte(Address
);
234 PointerPde
= MiAddressToPde(Address
);
237 // Check for dispatch-level snafu
239 if (OldIrql
> APC_LEVEL
)
242 // There are some special cases where this is okay, but not in ARM3 yet
244 DbgPrint("MM:***PAGE FAULT AT IRQL > 1 Va %p, IRQL %lx\n",
247 ASSERT(OldIrql
<= APC_LEVEL
);
251 // Check for kernel fault
253 if (Address
>= MmSystemRangeStart
)
256 // What are you even DOING here?
258 if (Mode
== UserMode
) return STATUS_ACCESS_VIOLATION
;
263 if (!PointerPde
->u
.Hard
.Valid
== 0)
268 DPRINT("Invalid PDE\n");
271 // Handle mapping in "Special" PDE directoreis
273 MiCheckPdeForPagedPool(Address
);
276 // Now we SHOULD be good
278 if (PointerPde
->u
.Hard
.Valid
== 0)
281 // FIXFIX: Do the S-LIST hack
287 KeBugCheckEx(PAGE_FAULT_IN_NONPAGED_AREA
,
290 (ULONG_PTR
)TrapInformation
,
296 // The PDE is valid, so read the PTE
298 TempPte
= *PointerPte
;
299 if (TempPte
.u
.Hard
.Valid
== 1)
302 // Only two things can go wrong here:
303 // Executing NX page (we couldn't care less)
304 // Writing to a read-only page (the stuff ARM3 works with is write,
305 // so again, moot point).
307 if (StoreInstruction
)
309 DPRINT1("Should NEVER happen on ARM3!!!\n");
310 return STATUS_ACCESS_VIOLATION
;
314 // Otherwise, the PDE was probably invalid, and all is good now
316 return STATUS_SUCCESS
;
320 // Check for a fault on the page table or hyperspace itself
322 if ((Address
>= (PVOID
)PTE_BASE
) && (Address
<= MmHyperSpaceEnd
))
325 // This might happen...not sure yet
327 DPRINT1("FAULT ON PAGE TABLES: %p %lx %lx!\n", Address
, *PointerPte
, *PointerPde
);
330 // Map in the page table
332 if (MiCheckPdeForPagedPool(Address
) == STATUS_WAIT_1
)
334 DPRINT1("PAGE TABLES FAULTED IN!\n");
335 return STATUS_SUCCESS
;
339 // Otherwise the page table doesn't actually exist
341 DPRINT1("FAILING\n");
342 return STATUS_ACCESS_VIOLATION
;
346 // Now we must raise to APC_LEVEL and mark the thread as owner
347 // We don't actually implement a working set pushlock, so this is only
348 // for internal consistency (and blocking APCs)
350 KeRaiseIrql(APC_LEVEL
, &LockIrql
);
351 CurrentThread
= PsGetCurrentThread();
352 KeEnterGuardedRegion();
353 ASSERT((CurrentThread
->OwnsSystemWorkingSetExclusive
== 0) &&
354 (CurrentThread
->OwnsSystemWorkingSetShared
== 0));
355 CurrentThread
->OwnsSystemWorkingSetExclusive
= 1;
358 // Re-read PTE now that the IRQL has been raised
360 TempPte
= *PointerPte
;
361 if (TempPte
.u
.Hard
.Valid
== 1)
364 // Only two things can go wrong here:
365 // Executing NX page (we couldn't care less)
366 // Writing to a read-only page (the stuff ARM3 works with is write,
367 // so again, moot point.
369 if (StoreInstruction
)
371 DPRINT1("Should NEVER happen on ARM3!!!\n");
372 return STATUS_ACCESS_VIOLATION
;
376 // Otherwise, the PDE was probably invalid, and all is good now
378 return STATUS_SUCCESS
;
382 // We don't implement prototype PTEs
384 ASSERT(TempPte
.u
.Soft
.Prototype
== 0);
387 // We don't implement transition PTEs
389 ASSERT(TempPte
.u
.Soft
.Transition
== 0);
392 // Now do the real fault handling
394 Status
= MiDispatchFault(StoreInstruction
,
406 ASSERT(KeAreAllApcsDisabled() == TRUE
);
407 CurrentThread
->OwnsSystemWorkingSetExclusive
= 0;
408 KeLeaveGuardedRegion();
409 KeLowerIrql(LockIrql
);
414 DPRINT("Fault resolved with status: %lx\n", Status
);
421 DPRINT1("WARNING: USER MODE FAULT IN ARM3???\n");
422 return STATUS_ACCESS_VIOLATION
;