f2aa6f114be3ea2d5add43ea62aca93785875bd0
[reactos.git] / reactos / boot / armllb / hw / versatile / hwuart.c
1 /*
2 * PROJECT: ReactOS Boot Loader
3 * LICENSE: BSD - See COPYING.ARM in the top level directory
4 * FILE: boot/armllb/hw/versatile/hwuart.c
5 * PURPOSE: LLB UART Initialization Routines for Versatile
6 * PROGRAMMERS: ReactOS Portable Systems Group
7 */
8
9 #include "precomp.h"
10
11 //
12 // UART Registers
13 //
14 #define UART_PL01x_DR (LlbHwVersaUartBase + 0x00)
15 #define UART_PL01x_RSR (LlbHwVersaUartBase + 0x04)
16 #define UART_PL01x_ECR (LlbHwVersaUartBase + 0x04)
17 #define UART_PL01x_FR (LlbHwVersaUartBase + 0x18)
18 #define UART_PL011_IBRD (LlbHwVersaUartBase + 0x24)
19 #define UART_PL011_FBRD (LlbHwVersaUartBase + 0x28)
20 #define UART_PL011_LCRH (LlbHwVersaUartBase + 0x2C)
21 #define UART_PL011_CR (LlbHwVersaUartBase + 0x30)
22 #define UART_PL011_IMSC (LlbHwVersaUartBase + 0x38)
23
24 //
25 // LCR Values
26 //
27 #define UART_PL011_LCRH_WLEN_8 0x60
28 #define UART_PL011_LCRH_FEN 0x10
29
30 //
31 // FCR Values
32 //
33 #define UART_PL011_CR_UARTEN 0x01
34 #define UART_PL011_CR_TXE 0x100
35 #define UART_PL011_CR_RXE 0x200
36
37 //
38 // LSR Values
39 //
40 #define UART_PL01x_FR_RXFE 0x10
41 #define UART_PL01x_FR_TXFF 0x20
42
43 static const ULONG LlbHwVersaUartBase = 0x101F1000;
44
45 /* FUNCTIONS ******************************************************************/
46
47 VOID
48 LlbHwVersaUartInitialize(VOID)
49 {
50 ULONG Divider, Remainder, Fraction, ClockRate, Baudrate;
51
52 /* Query peripheral rate, hardcore baudrate */
53 ClockRate = LlbHwGetPClk();
54 Baudrate = 115200;
55
56 /* Calculate baudrate clock divider and remainder */
57 Divider = ClockRate / (16 * Baudrate);
58 Remainder = ClockRate % (16 * Baudrate);
59
60 /* Calculate the fractional part */
61 Fraction = (8 * Remainder / Baudrate) >> 1;
62 Fraction += (8 * Remainder / Baudrate) & 1;
63
64 /* Disable interrupts */
65 WRITE_REGISTER_ULONG(UART_PL011_CR, 0);
66
67 /* Set the baud rate to 115200 bps */
68 WRITE_REGISTER_ULONG(UART_PL011_IBRD, Divider);
69 WRITE_REGISTER_ULONG(UART_PL011_FBRD, Fraction);
70
71 /* Set 8 bits for data, 1 stop bit, no parity, FIFO enabled */
72 WRITE_REGISTER_ULONG(UART_PL011_LCRH,
73 UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN);
74
75 /* Clear and enable FIFO */
76 WRITE_REGISTER_ULONG(UART_PL011_CR,
77 UART_PL011_CR_UARTEN |
78 UART_PL011_CR_TXE |
79 UART_PL011_CR_RXE);
80 }
81
82 VOID
83 NTAPI
84 LlbHwUartSendChar(IN CHAR Char)
85 {
86 /* Send the character */
87 WRITE_REGISTER_ULONG(UART_PL01x_DR, Char);
88 }
89
90 BOOLEAN
91 NTAPI
92 LlbHwUartTxReady(VOID)
93 {
94 /* TX output buffer is ready? */
95 return (READ_REGISTER_ULONG(UART_PL01x_FR) & UART_PL01x_FR_TXFF);
96 }
97
98 ULONG
99 NTAPI
100 LlbHwGetUartBase(IN ULONG Port)
101 {
102 if (Port == 0)
103 {
104 return 0x101F1000;
105 }
106 else if (Port == 1)
107 {
108 return 0x101F2000;
109 }
110
111 return 0;
112 }
113
114 /* EOF */