reactos/boot/freeldr/freeldr/arch/arm/ferouart.c

   1 /*
   2  * PROJECT:         ReactOS Boot Loader
   3  * LICENSE:         BSD - See COPYING.ARM in the top level directory
   4  * FILE:            boot/freeldr/arch/arm/ferouart.c
   5  * PURPOSE:         Implements code for Feroceon boards using the 16550 UART
   6  * PROGRAMMERS:     ReactOS Portable Systems Group
   7  */
   8
   9 /* INCLUDES *******************************************************************/
  10
  11 #include <freeldr.h>
  12
  13 /* GLOBALS ********************************************************************/
  14
  15 //
  16 // UART Registers
  17 //
  18 #define UART0_RBR   (ArmBoardBlock->UartRegisterBase + 0x00)
  19 #define UART0_THR   UART0_RBR
  20 #define UART0_IER   (ArmBoardBlock->UartRegisterBase + 0x04)
  21 #define UART0_FCR   (ArmBoardBlock->UartRegisterBase + 0x08)
  22 #define UART0_LCR   (ArmBoardBlock->UartRegisterBase + 0x0C)
  23 #define UART0_MCR   (ArmBoardBlock->UartRegisterBase + 0x10)
  24 #define UART0_LSR   (ArmBoardBlock->UartRegisterBase + 0x14)
  25 #define UART0_MSR   (ArmBoardBlock->UartRegisterBase + 0x18)
  26 #define UART0_SCR   (ArmBoardBlock->UartRegisterBase + 0x1C)
  27
  28 //
  29 // When we enable the divisor latch
  30 //
  31 #define UART0_DLL   UART0_RBR
  32 #define UART0_DLM   UART0_IER
  33
  34 //
  35 // FCR Values
  36 //
  37 #define FCR_FIFO_EN 0x01
  38 #define FCR_RXSR    0x02
  39 #define FCR_TXSR    0x04
  40
  41 //
  42 // LCR Values
  43 //
  44 #define LCR_WLS_8   0x03
  45 #define LCR_1_STB   0x00
  46 #define LCR_DIVL_EN 0x80
  47 #define LCR_NO_PAR  0x00
  48
  49 //
  50 // LSR Values
  51 //
  52 #define LSR_DR      0x01
  53 #define LSR_THRE    0x20
  54
  55 /* FUNCTIONS ******************************************************************/
  56
  57 VOID
  58 ArmFeroSerialInit(IN ULONG Baudrate)
  59 {
  60     ULONG BaudClock;
  61
  62     //
  63     // Calculate baudrate clock divider to set the baud rate
  64     //
  65     BaudClock = (ArmBoardBlock->ClockRate / 16) / Baudrate;
  66
  67     //
  68     // Disable interrupts
  69     //
  70     WRITE_REGISTER_UCHAR(UART0_IER, 0);
  71
  72     //
  73     // Set the baud rate to 115200 bps
  74     //
  75     WRITE_REGISTER_UCHAR(UART0_LCR, LCR_DIVL_EN);
  76     WRITE_REGISTER_UCHAR(UART0_DLL, BaudClock);
  77     WRITE_REGISTER_UCHAR(UART0_DLM, (BaudClock >> 8) & 0xFF);
  78
  79     //
  80     // Set 8 bits for data, 1 stop bit, no parity
  81     //
  82     WRITE_REGISTER_UCHAR(UART0_LCR, LCR_WLS_8 | LCR_1_STB | LCR_NO_PAR);
  83
  84     //
  85     // Clear and enable FIFO
  86     //
  87     WRITE_REGISTER_UCHAR(UART0_FCR, FCR_FIFO_EN | FCR_RXSR | FCR_TXSR);
  88 }
  89
  90 VOID
  91 ArmFeroPutChar(IN INT Char)
  92 {
  93     //
  94     // Properly support new-lines
  95     //
  96     if (Char == '\n') ArmFeroPutChar('\r');
  97
  98     //
  99     // Wait for ready
 100     //
 101     while ((READ_REGISTER_UCHAR(UART0_LSR) & LSR_THRE) == 0);
 102
 103     //
 104     // Send the character
 105     //
 106     WRITE_REGISTER_UCHAR(UART0_THR, Char);
 107 }
 108
 109 INT
 110 ArmFeroGetCh(VOID)
 111 {
 112     //
 113     // Wait for ready
 114     //
 115     while ((READ_REGISTER_UCHAR(UART0_LSR) & LSR_DR) == 0);
 116
 117     //
 118     // Read the character
 119     //
 120     return READ_REGISTER_UCHAR(UART0_RBR);
 121 }
 122
 123 BOOLEAN
 124 ArmFeroKbHit(VOID)
 125 {
 126     //
 127     // Return if something is ready
 128     //
 129     return ((READ_REGISTER_UCHAR(UART0_LSR) & LSR_DR) != 0);
 130 }