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[reactos.git] / reactos / boot / freeldr / freeldr / math / i386.h
1 /* Definitions of target machine for GNU compiler for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
4
5 This file is part of GNU CC.
6
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
24
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
27
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
30
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
36
37 /* Stubs for half-pic support if not OSF/1 reference platform. */
38
39 #ifndef HALF_PIC_P
40 #define HALF_PIC_P() 0
41 #define HALF_PIC_NUMBER_PTRS 0
42 #define HALF_PIC_NUMBER_REFS 0
43 #define HALF_PIC_ENCODE(DECL)
44 #define HALF_PIC_DECLARE(NAME)
45 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it")
46 #define HALF_PIC_ADDRESS_P(X) 0
47 #define HALF_PIC_PTR(X) (X)
48 #define HALF_PIC_FINISH(STREAM)
49 #endif
50
51 /* Define the specific costs for a given cpu */
52
53 struct processor_costs {
54 const int add; /* cost of an add instruction */
55 const int lea; /* cost of a lea instruction */
56 const int shift_var; /* variable shift costs */
57 const int shift_const; /* constant shift costs */
58 const int mult_init; /* cost of starting a multiply */
59 const int mult_bit; /* cost of multiply per each bit set */
60 const int divide; /* cost of a divide/mod */
61 int movsx; /* The cost of movsx operation. */
62 int movzx; /* The cost of movzx operation. */
63 const int large_insn; /* insns larger than this cost more */
64 const int move_ratio; /* The threshold of number of scalar
65 memory-to-memory move insns. */
66 const int movzbl_load; /* cost of loading using movzbl */
67 const int int_load[3]; /* cost of loading integer registers
68 in QImode, HImode and SImode relative
69 to reg-reg move (2). */
70 const int int_store[3]; /* cost of storing integer register
71 in QImode, HImode and SImode */
72 const int fp_move; /* cost of reg,reg fld/fst */
73 const int fp_load[3]; /* cost of loading FP register
74 in SFmode, DFmode and XFmode */
75 const int fp_store[3]; /* cost of storing FP register
76 in SFmode, DFmode and XFmode */
77 const int mmx_move; /* cost of moving MMX register. */
78 const int mmx_load[2]; /* cost of loading MMX register
79 in SImode and DImode */
80 const int mmx_store[2]; /* cost of storing MMX register
81 in SImode and DImode */
82 const int sse_move; /* cost of moving SSE register. */
83 const int sse_load[3]; /* cost of loading SSE register
84 in SImode, DImode and TImode*/
85 const int sse_store[3]; /* cost of storing SSE register
86 in SImode, DImode and TImode*/
87 const int mmxsse_to_integer; /* cost of moving mmxsse register to
88 integer and vice versa. */
89 const int prefetch_block; /* bytes moved to cache for prefetch. */
90 const int simultaneous_prefetches; /* number of parallel prefetch
91 operations. */
92 };
93
94 extern const struct processor_costs *ix86_cost;
95
96 /* Run-time compilation parameters selecting different hardware subsets. */
97
98 extern int target_flags;
99
100 /* Macros used in the machine description to test the flags. */
101
102 /* configure can arrange to make this 2, to force a 486. */
103
104 #ifndef TARGET_CPU_DEFAULT
105 #define TARGET_CPU_DEFAULT 0
106 #endif
107
108 /* Masks for the -m switches */
109 #define MASK_80387 0x00000001 /* Hardware floating point */
110 #define MASK_RTD 0x00000002 /* Use ret that pops args */
111 #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */
112 #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */
113 #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */
114 #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */
115 #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */
116 #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */
117 #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */
118 #define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */
119 #define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */
120 #define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */
121 #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */
122 #define MASK_ACCUMULATE_OUTGOING_ARGS_SET 0x00002000
123 #define MASK_MMX 0x00004000 /* Support MMX regs/builtins */
124 #define MASK_MMX_SET 0x00008000
125 #define MASK_SSE 0x00010000 /* Support SSE regs/builtins */
126 #define MASK_SSE_SET 0x00020000
127 #define MASK_SSE2 0x00040000 /* Support SSE2 regs/builtins */
128 #define MASK_SSE2_SET 0x00080000
129 #define MASK_3DNOW 0x00100000 /* Support 3Dnow builtins */
130 #define MASK_3DNOW_SET 0x00200000
131 #define MASK_3DNOW_A 0x00400000 /* Support Athlon 3Dnow builtins */
132 #define MASK_3DNOW_A_SET 0x00800000
133 #define MASK_128BIT_LONG_DOUBLE 0x01000000 /* long double size is 128bit */
134 #define MASK_64BIT 0x02000000 /* Produce 64bit code */
135 /* ... overlap with subtarget options starts by 0x04000000. */
136 #define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */
137
138 /* Use the floating point instructions */
139 #define TARGET_80387 (target_flags & MASK_80387)
140
141 /* Compile using ret insn that pops args.
142 This will not work unless you use prototypes at least
143 for all functions that can take varying numbers of args. */
144 #define TARGET_RTD (target_flags & MASK_RTD)
145
146 /* Align doubles to a two word boundary. This breaks compatibility with
147 the published ABI's for structures containing doubles, but produces
148 faster code on the pentium. */
149 #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
150
151 /* Use push instructions to save outgoing args. */
152 #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
153
154 /* Accumulate stack adjustments to prologue/epilogue. */
155 #define TARGET_ACCUMULATE_OUTGOING_ARGS \
156 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
157
158 /* Put uninitialized locals into bss, not data.
159 Meaningful only on svr3. */
160 #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
161
162 /* Use IEEE floating point comparisons. These handle correctly the cases
163 where the result of a comparison is unordered. Normally SIGFPE is
164 generated in such cases, in which case this isn't needed. */
165 #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
166
167 /* Functions that return a floating point value may return that value
168 in the 387 FPU or in 386 integer registers. If set, this flag causes
169 the 387 to be used, which is compatible with most calling conventions. */
170 #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
171
172 /* Long double is 128bit instead of 96bit, even when only 80bits are used.
173 This mode wastes cache, but avoid misaligned data accesses and simplifies
174 address calculations. */
175 #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE)
176
177 /* Disable generation of FP sin, cos and sqrt operations for 387.
178 This is because FreeBSD lacks these in the math-emulator-code */
179 #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
180
181 /* Don't create frame pointers for leaf functions */
182 #define TARGET_OMIT_LEAF_FRAME_POINTER \
183 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
184
185 /* Debug GO_IF_LEGITIMATE_ADDRESS */
186 #define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0)
187
188 /* Debug FUNCTION_ARG macros */
189 #define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0)
190
191 /* 64bit Sledgehammer mode */
192 #ifdef TARGET_BI_ARCH
193 #define TARGET_64BIT (target_flags & MASK_64BIT)
194 #else
195 #ifdef TARGET_64BIT_DEFAULT
196 #define TARGET_64BIT 1
197 #else
198 #define TARGET_64BIT 0
199 #endif
200 #endif
201
202 #define TARGET_386 (ix86_cpu == PROCESSOR_I386)
203 #define TARGET_486 (ix86_cpu == PROCESSOR_I486)
204 #define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM)
205 #define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO)
206 #define TARGET_K6 (ix86_cpu == PROCESSOR_K6)
207 #define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON)
208 #define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4)
209
210 #define CPUMASK (1 << ix86_cpu)
211 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
212 extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
213 extern const int x86_branch_hints, x86_unroll_strlen;
214 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
215 extern const int x86_use_loop, x86_use_fiop, x86_use_mov0;
216 extern const int x86_use_cltd, x86_read_modify_write;
217 extern const int x86_read_modify, x86_split_long_moves;
218 extern const int x86_promote_QImode, x86_single_stringop;
219 extern const int x86_himode_math, x86_qimode_math, x86_promote_qi_regs;
220 extern const int x86_promote_hi_regs, x86_integer_DFmode_moves;
221 extern const int x86_add_esp_4, x86_add_esp_8, x86_sub_esp_4, x86_sub_esp_8;
222 extern const int x86_partial_reg_dependency, x86_memory_mismatch_stall;
223 extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
224 extern const int x86_epilogue_using_move, x86_decompose_lea;
225 extern const int x86_arch_always_fancy_math_387;
226 extern int x86_prefetch_sse;
227
228 #define TARGET_USE_LEAVE (x86_use_leave & CPUMASK)
229 #define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK)
230 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK)
231 #define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK)
232 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK)
233 /* For sane SSE instruction set generation we need fcomi instruction. It is
234 safe to enable all CMOVE instructions. */
235 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
236 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK)
237 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK)
238 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK)
239 #define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT)
240 #define TARGET_MOVX (x86_movx & CPUMASK)
241 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK)
242 #define TARGET_USE_LOOP (x86_use_loop & CPUMASK)
243 #define TARGET_USE_FIOP (x86_use_fiop & CPUMASK)
244 #define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK)
245 #define TARGET_USE_CLTD (x86_use_cltd & CPUMASK)
246 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK)
247 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK)
248 #define TARGET_READ_MODIFY (x86_read_modify & CPUMASK)
249 #define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK)
250 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK)
251 #define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK)
252 #define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK)
253 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK)
254 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK)
255 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK)
256 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK)
257 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK)
258 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK)
259 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK)
260 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK)
261 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK)
262 #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK)
263 #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK)
264 #define TARGET_DECOMPOSE_LEA (x86_decompose_lea & CPUMASK)
265 #define TARGET_PREFETCH_SSE (x86_prefetch_sse)
266
267 #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
268
269 #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
270 #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
271
272 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
273
274 #define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0)
275 #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
276 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
277 #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
278 && (ix86_fpmath & FPMATH_387))
279 #define TARGET_MMX ((target_flags & MASK_MMX) != 0)
280 #define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0)
281 #define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0)
282
283 #define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE))
284
285 /* WARNING: Do not mark empty strings for translation, as calling
286 gettext on an empty string does NOT return an empty
287 string. */
288
289
290 #define TARGET_SWITCHES \
291 { { "80387", MASK_80387, N_("Use hardware fp") }, \
292 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
293 { "hard-float", MASK_80387, N_("Use hardware fp") }, \
294 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
295 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
296 { "386", 0, "" /*Deprecated.*/}, \
297 { "486", 0, "" /*Deprecated.*/}, \
298 { "pentium", 0, "" /*Deprecated.*/}, \
299 { "pentiumpro", 0, "" /*Deprecated.*/}, \
300 { "intel-syntax", 0, "" /*Deprecated.*/}, \
301 { "no-intel-syntax", 0, "" /*Deprecated.*/}, \
302 { "rtd", MASK_RTD, \
303 N_("Alternate calling convention") }, \
304 { "no-rtd", -MASK_RTD, \
305 N_("Use normal calling convention") }, \
306 { "align-double", MASK_ALIGN_DOUBLE, \
307 N_("Align some doubles on dword boundary") }, \
308 { "no-align-double", -MASK_ALIGN_DOUBLE, \
309 N_("Align doubles on word boundary") }, \
310 { "svr3-shlib", MASK_SVR3_SHLIB, \
311 N_("Uninitialized locals in .bss") }, \
312 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \
313 N_("Uninitialized locals in .data") }, \
314 { "ieee-fp", MASK_IEEE_FP, \
315 N_("Use IEEE math for fp comparisons") }, \
316 { "no-ieee-fp", -MASK_IEEE_FP, \
317 N_("Do not use IEEE math for fp comparisons") }, \
318 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \
319 N_("Return values of functions in FPU registers") }, \
320 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
321 N_("Do not return values of functions in FPU registers")}, \
322 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
323 N_("Do not generate sin, cos, sqrt for FPU") }, \
324 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
325 N_("Generate sin, cos, sqrt for FPU")}, \
326 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
327 N_("Omit the frame pointer in leaf functions") }, \
328 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
329 { "stack-arg-probe", MASK_STACK_PROBE, \
330 N_("Enable stack probing") }, \
331 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
332 { "windows", 0, 0 /* undocumented */ }, \
333 { "dll", 0, 0 /* undocumented */ }, \
334 { "align-stringops", -MASK_NO_ALIGN_STROPS, \
335 N_("Align destination of the string operations") }, \
336 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \
337 N_("Do not align destination of the string operations") }, \
338 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
339 N_("Inline all known string operations") }, \
340 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
341 N_("Do not inline all known string operations") }, \
342 { "push-args", -MASK_NO_PUSH_ARGS, \
343 N_("Use push instructions to save outgoing arguments") }, \
344 { "no-push-args", MASK_NO_PUSH_ARGS, \
345 N_("Do not use push instructions to save outgoing arguments") }, \
346 { "accumulate-outgoing-args", (MASK_ACCUMULATE_OUTGOING_ARGS \
347 | MASK_ACCUMULATE_OUTGOING_ARGS_SET), \
348 N_("Use push instructions to save outgoing arguments") }, \
349 { "no-accumulate-outgoing-args",MASK_ACCUMULATE_OUTGOING_ARGS_SET, \
350 N_("Do not use push instructions to save outgoing arguments") }, \
351 { "mmx", MASK_MMX | MASK_MMX_SET, \
352 N_("Support MMX built-in functions") }, \
353 { "no-mmx", -MASK_MMX, \
354 N_("Do not support MMX built-in functions") }, \
355 { "no-mmx", MASK_MMX_SET, "" }, \
356 { "3dnow", MASK_3DNOW | MASK_3DNOW_SET, \
357 N_("Support 3DNow! built-in functions") }, \
358 { "no-3dnow", -MASK_3DNOW, "" }, \
359 { "no-3dnow", MASK_3DNOW_SET, \
360 N_("Do not support 3DNow! built-in functions") }, \
361 { "sse", MASK_SSE | MASK_SSE_SET, \
362 N_("Support MMX and SSE built-in functions and code generation") }, \
363 { "no-sse", -MASK_SSE, "" }, \
364 { "no-sse", MASK_SSE_SET, \
365 N_("Do not support MMX and SSE built-in functions and code generation") },\
366 { "sse2", MASK_SSE2 | MASK_SSE2_SET, \
367 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \
368 { "no-sse2", -MASK_SSE2, "" }, \
369 { "no-sse2", MASK_SSE2_SET, \
370 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \
371 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
372 N_("sizeof(long double) is 16") }, \
373 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
374 N_("sizeof(long double) is 12") }, \
375 { "64", MASK_64BIT, \
376 N_("Generate 64bit x86-64 code") }, \
377 { "32", -MASK_64BIT, \
378 N_("Generate 32bit i386 code") }, \
379 { "red-zone", -MASK_NO_RED_ZONE, \
380 N_("Use red-zone in the x86-64 code") }, \
381 { "no-red-zone", MASK_NO_RED_ZONE, \
382 N_("Do not use red-zone in the x86-64 code") }, \
383 SUBTARGET_SWITCHES \
384 { "", TARGET_DEFAULT, 0 }}
385
386 #ifdef TARGET_64BIT_DEFAULT
387 #define TARGET_DEFAULT (MASK_64BIT | TARGET_SUBTARGET_DEFAULT)
388 #else
389 #define TARGET_DEFAULT TARGET_SUBTARGET_DEFAULT
390 #endif
391
392 /* Which processor to schedule for. The cpu attribute defines a list that
393 mirrors this list, so changes to i386.md must be made at the same time. */
394
395 enum processor_type
396 {
397 PROCESSOR_I386, /* 80386 */
398 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */
399 PROCESSOR_PENTIUM,
400 PROCESSOR_PENTIUMPRO,
401 PROCESSOR_K6,
402 PROCESSOR_ATHLON,
403 PROCESSOR_PENTIUM4,
404 PROCESSOR_max
405 };
406 enum fpmath_unit
407 {
408 FPMATH_387 = 1,
409 FPMATH_SSE = 2
410 };
411
412 extern enum processor_type ix86_cpu;
413 extern enum fpmath_unit ix86_fpmath;
414
415 extern int ix86_arch;
416
417 /* This macro is similar to `TARGET_SWITCHES' but defines names of
418 command options that have values. Its definition is an
419 initializer with a subgrouping for each command option.
420
421 Each subgrouping contains a string constant, that defines the
422 fixed part of the option name, and the address of a variable. The
423 variable, type `char *', is set to the variable part of the given
424 option if the fixed part matches. The actual option name is made
425 by appending `-m' to the specified name. */
426 #define TARGET_OPTIONS \
427 { { "cpu=", &ix86_cpu_string, \
428 N_("Schedule code for given CPU")}, \
429 { "fpmath=", &ix86_fpmath_string, \
430 N_("Generate floating point mathematics using given instruction set")},\
431 { "arch=", &ix86_arch_string, \
432 N_("Generate code for given CPU")}, \
433 { "regparm=", &ix86_regparm_string, \
434 N_("Number of registers used to pass integer arguments") }, \
435 { "align-loops=", &ix86_align_loops_string, \
436 N_("Loop code aligned to this power of 2") }, \
437 { "align-jumps=", &ix86_align_jumps_string, \
438 N_("Jump targets are aligned to this power of 2") }, \
439 { "align-functions=", &ix86_align_funcs_string, \
440 N_("Function starts are aligned to this power of 2") }, \
441 { "preferred-stack-boundary=", \
442 &ix86_preferred_stack_boundary_string, \
443 N_("Attempt to keep stack aligned to this power of 2") }, \
444 { "branch-cost=", &ix86_branch_cost_string, \
445 N_("Branches are this expensive (1-5, arbitrary units)") }, \
446 { "cmodel=", &ix86_cmodel_string, \
447 N_("Use given x86-64 code model") }, \
448 { "debug-arg", &ix86_debug_arg_string, \
449 "" /* Undocumented. */ }, \
450 { "debug-addr", &ix86_debug_addr_string, \
451 "" /* Undocumented. */ }, \
452 { "asm=", &ix86_asm_string, \
453 N_("Use given assembler dialect") }, \
454 SUBTARGET_OPTIONS \
455 }
456
457 /* Sometimes certain combinations of command options do not make
458 sense on a particular target machine. You can define a macro
459 `OVERRIDE_OPTIONS' to take account of this. This macro, if
460 defined, is executed once just after all the command options have
461 been parsed.
462
463 Don't use this macro to turn on various extra optimizations for
464 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
465
466 #define OVERRIDE_OPTIONS override_options ()
467
468 /* These are meant to be redefined in the host dependent files */
469 #define SUBTARGET_SWITCHES
470 #define SUBTARGET_OPTIONS
471
472 /* Define this to change the optimizations performed by default. */
473 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
474 optimization_options ((LEVEL), (SIZE))
475
476 /* Specs for the compiler proper */
477
478 #ifndef CC1_CPU_SPEC
479 #define CC1_CPU_SPEC "\
480 %{!mcpu*: \
481 %{m386:-mcpu=i386 \
482 %n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \
483 %{m486:-mcpu=i486 \
484 %n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \
485 %{mpentium:-mcpu=pentium \
486 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \
487 %{mpentiumpro:-mcpu=pentiumpro \
488 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}} \
489 %{mintel-syntax:-masm=intel \
490 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
491 %{mno-intel-syntax:-masm=att \
492 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
493 #endif
494 \f
495 #define TARGET_CPU_DEFAULT_i386 0
496 #define TARGET_CPU_DEFAULT_i486 1
497 #define TARGET_CPU_DEFAULT_pentium 2
498 #define TARGET_CPU_DEFAULT_pentium_mmx 3
499 #define TARGET_CPU_DEFAULT_pentiumpro 4
500 #define TARGET_CPU_DEFAULT_pentium2 5
501 #define TARGET_CPU_DEFAULT_pentium3 6
502 #define TARGET_CPU_DEFAULT_pentium4 7
503 #define TARGET_CPU_DEFAULT_k6 8
504 #define TARGET_CPU_DEFAULT_k6_2 9
505 #define TARGET_CPU_DEFAULT_k6_3 10
506 #define TARGET_CPU_DEFAULT_athlon 11
507 #define TARGET_CPU_DEFAULT_athlon_sse 12
508
509 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
510 "pentiumpro", "pentium2", "pentium3", \
511 "pentium4", "k6", "k6-2", "k6-3",\
512 "athlon", "athlon-4"}
513 #ifndef CPP_CPU_DEFAULT_SPEC
514 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_i486
515 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i486__"
516 #endif
517 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium
518 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__"
519 #endif
520 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium_mmx
521 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__"
522 #endif
523 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentiumpro
524 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__"
525 #endif
526 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium2
527 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\
528 -D__tune_pentium2__"
529 #endif
530 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium3
531 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\
532 -D__tune_pentium2__ -D__tune_pentium3__"
533 #endif
534 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium4
535 #define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium4__"
536 #endif
537 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6
538 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__"
539 #endif
540 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_2
541 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_2__"
542 #endif
543 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_3
544 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_3__"
545 #endif
546 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon
547 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__"
548 #endif
549 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon_sse
550 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__ -D__tune_athlon_sse__"
551 #endif
552 #ifndef CPP_CPU_DEFAULT_SPEC
553 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__"
554 #endif
555 #endif /* CPP_CPU_DEFAULT_SPEC */
556
557 #ifdef TARGET_BI_ARCH
558 #define NO_BUILTIN_SIZE_TYPE
559 #define NO_BUILTIN_PTRDIFF_TYPE
560 #endif
561
562 #ifdef NO_BUILTIN_SIZE_TYPE
563 #define CPP_CPU32_SIZE_TYPE_SPEC \
564 " -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int"
565 #define CPP_CPU64_SIZE_TYPE_SPEC \
566 " -D__SIZE_TYPE__=unsigned\\ long\\ int -D__PTRDIFF_TYPE__=long\\ int"
567 #else
568 #define CPP_CPU32_SIZE_TYPE_SPEC ""
569 #define CPP_CPU64_SIZE_TYPE_SPEC ""
570 #endif
571
572 #define CPP_CPU32_SPEC \
573 "-Acpu=i386 -Amachine=i386 %{!ansi:%{!std=c*:%{!std=i*:-Di386}}} -D__i386 \
574 -D__i386__ %(cpp_cpu32sizet)"
575
576 #define CPP_CPU64_SPEC \
577 "-Acpu=x86_64 -Amachine=x86_64 -D__x86_64 -D__x86_64__ %(cpp_cpu64sizet)"
578
579 #define CPP_CPUCOMMON_SPEC "\
580 %{march=i386:%{!mcpu*:-D__tune_i386__ }}\
581 %{march=i486:-D__i486 -D__i486__ %{!mcpu*:-D__tune_i486__ }}\
582 %{march=pentium|march=i586:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
583 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ }}\
584 %{march=pentium-mmx:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
585 -D__pentium__mmx__ \
586 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__}}\
587 %{march=pentiumpro|march=i686:-D__i686 -D__i686__ \
588 -D__pentiumpro -D__pentiumpro__ \
589 %{!mcpu*:-D__tune_i686__ -D__tune_pentiumpro__ }}\
590 %{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\
591 %{march=k6-2:-D__k6 -D__k6__ -D__k6_2__ \
592 %{!mcpu*:-D__tune_k6__ -D__tune_k6_2__ }}\
593 %{march=k6-3:-D__k6 -D__k6__ -D__k6_3__ \
594 %{!mcpu*:-D__tune_k6__ -D__tune_k6_3__ }}\
595 %{march=athlon|march=athlon-tbird:-D__athlon -D__athlon__ \
596 %{!mcpu*:-D__tune_athlon__ }}\
597 %{march=athlon-4|march=athlon-xp|march=athlon-mp:-D__athlon -D__athlon__ \
598 -D__athlon_sse__ \
599 %{!mcpu*:-D__tune_athlon__ -D__tune_athlon_sse__ }}\
600 %{march=pentium4:-D__pentium4 -D__pentium4__ %{!mcpu*:-D__tune_pentium4__ }}\
601 %{m386|mcpu=i386:-D__tune_i386__ }\
602 %{m486|mcpu=i486:-D__tune_i486__ }\
603 %{mpentium|mcpu=pentium|mcpu=i586|mcpu=pentium-mmx:-D__tune_i586__ -D__tune_pentium__ }\
604 %{mpentiumpro|mcpu=pentiumpro|mcpu=i686|cpu=pentium2|cpu=pentium3:-D__tune_i686__ \
605 -D__tune_pentiumpro__ }\
606 %{mcpu=k6|mcpu=k6-2|mcpu=k6-3:-D__tune_k6__ }\
607 %{mcpu=athlon|mcpu=athlon-tbird|mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\
608 -D__tune_athlon__ }\
609 %{mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\
610 -D__tune_athlon_sse__ }\
611 %{mcpu=pentium4:-D__tune_pentium4__ }\
612 %{march=athlon-tbird|march=athlon-xp|march=athlon-mp|march=pentium3|march=pentium4:\
613 -D__SSE__ }\
614 %{march=pentium-mmx|march=k6|march=k6-2|march=k6-3\
615 |march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
616 |march=athlon-mp|march=pentium2|march=pentium3|march=pentium4: -D__MMX__ }\
617 %{march=k6-2|march=k6-3\
618 |march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
619 |march=athlon-mp: -D__3dNOW__ }\
620 %{march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
621 |march=athlon-mp: -D__3dNOW_A__ }\
622 %{march=pentium4: -D__SSE2__ }\
623 %{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}"
624
625 #ifndef CPP_CPU_SPEC
626 #ifdef TARGET_BI_ARCH
627 #ifdef TARGET_64BIT_DEFAULT
628 #define CPP_CPU_SPEC "%{m32:%(cpp_cpu32)}%{!m32:%(cpp_cpu64)} %(cpp_cpucommon)"
629 #else
630 #define CPP_CPU_SPEC "%{m64:%(cpp_cpu64)}%{!m64:%(cpp_cpu32)} %(cpp_cpucommon)"
631 #endif
632 #else
633 #ifdef TARGET_64BIT_DEFAULT
634 #define CPP_CPU_SPEC "%(cpp_cpu64) %(cpp_cpucommon)"
635 #else
636 #define CPP_CPU_SPEC "%(cpp_cpu32) %(cpp_cpucommon)"
637 #endif
638 #endif
639 #endif
640
641 #ifndef CC1_SPEC
642 #define CC1_SPEC "%(cc1_cpu) "
643 #endif
644
645 /* This macro defines names of additional specifications to put in the
646 specs that can be used in various specifications like CC1_SPEC. Its
647 definition is an initializer with a subgrouping for each command option.
648
649 Each subgrouping contains a string constant, that defines the
650 specification name, and a string constant that used by the GNU CC driver
651 program.
652
653 Do not define this macro if it does not need to do anything. */
654
655 #ifndef SUBTARGET_EXTRA_SPECS
656 #define SUBTARGET_EXTRA_SPECS
657 #endif
658
659 #define EXTRA_SPECS \
660 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
661 { "cpp_cpu", CPP_CPU_SPEC }, \
662 { "cpp_cpu32", CPP_CPU32_SPEC }, \
663 { "cpp_cpu64", CPP_CPU64_SPEC }, \
664 { "cpp_cpu32sizet", CPP_CPU32_SIZE_TYPE_SPEC }, \
665 { "cpp_cpu64sizet", CPP_CPU64_SIZE_TYPE_SPEC }, \
666 { "cpp_cpucommon", CPP_CPUCOMMON_SPEC }, \
667 { "cc1_cpu", CC1_CPU_SPEC }, \
668 SUBTARGET_EXTRA_SPECS
669 \f
670 /* target machine storage layout */
671
672 /* Define for XFmode or TFmode extended real floating point support.
673 This will automatically cause REAL_ARITHMETIC to be defined.
674
675 The XFmode is specified by i386 ABI, while TFmode may be faster
676 due to alignment and simplifications in the address calculations.
677 */
678 #define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96)
679 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
680 #ifdef __x86_64__
681 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
682 #else
683 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96
684 #endif
685 /* Tell real.c that this is the 80-bit Intel extended float format
686 packaged in a 128-bit or 96bit entity. */
687 #define INTEL_EXTENDED_IEEE_FORMAT 1
688
689
690 #define SHORT_TYPE_SIZE 16
691 #define INT_TYPE_SIZE 32
692 #define FLOAT_TYPE_SIZE 32
693 #define LONG_TYPE_SIZE BITS_PER_WORD
694 #define MAX_WCHAR_TYPE_SIZE 32
695 #define DOUBLE_TYPE_SIZE 64
696 #define LONG_LONG_TYPE_SIZE 64
697
698 #if defined (TARGET_BI_ARCH) || defined (TARGET_64BIT_DEFAULT)
699 #define MAX_BITS_PER_WORD 64
700 #define MAX_LONG_TYPE_SIZE 64
701 #else
702 #define MAX_BITS_PER_WORD 32
703 #define MAX_LONG_TYPE_SIZE 32
704 #endif
705
706 /* Define if you don't want extended real, but do want to use the
707 software floating point emulator for REAL_ARITHMETIC and
708 decimal <-> binary conversion. */
709 /* #define REAL_ARITHMETIC */
710
711 /* Define this if most significant byte of a word is the lowest numbered. */
712 /* That is true on the 80386. */
713
714 #define BITS_BIG_ENDIAN 0
715
716 /* Define this if most significant byte of a word is the lowest numbered. */
717 /* That is not true on the 80386. */
718 #define BYTES_BIG_ENDIAN 0
719
720 /* Define this if most significant word of a multiword number is the lowest
721 numbered. */
722 /* Not true for 80386 */
723 #define WORDS_BIG_ENDIAN 0
724
725 /* number of bits in an addressable storage unit */
726 #define BITS_PER_UNIT 8
727
728 /* Width in bits of a "word", which is the contents of a machine register.
729 Note that this is not necessarily the width of data type `int';
730 if using 16-bit ints on a 80386, this would still be 32.
731 But on a machine with 16-bit registers, this would be 16. */
732 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
733
734 /* Width of a word, in units (bytes). */
735 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
736 #define MIN_UNITS_PER_WORD 4
737
738 /* Width in bits of a pointer.
739 See also the macro `Pmode' defined below. */
740 #define POINTER_SIZE BITS_PER_WORD
741
742 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
743 #define PARM_BOUNDARY BITS_PER_WORD
744
745 /* Boundary (in *bits*) on which stack pointer should be aligned. */
746 #define STACK_BOUNDARY BITS_PER_WORD
747
748 /* Boundary (in *bits*) on which the stack pointer preferrs to be
749 aligned; the compiler cannot rely on having this alignment. */
750 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
751
752 /* As of July 2001, many runtimes to not align the stack properly when
753 entering main. This causes expand_main_function to forcably align
754 the stack, which results in aligned frames for functions called from
755 main, though it does nothing for the alignment of main itself. */
756 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
757 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
758
759 /* Allocation boundary for the code of a function. */
760 #define FUNCTION_BOUNDARY 16
761
762 /* Alignment of field after `int : 0' in a structure. */
763
764 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
765
766 /* Minimum size in bits of the largest boundary to which any
767 and all fundamental data types supported by the hardware
768 might need to be aligned. No data type wants to be aligned
769 rounder than this.
770
771 Pentium+ preferrs DFmode values to be aligned to 64 bit boundary
772 and Pentium Pro XFmode values at 128 bit boundaries. */
773
774 #define BIGGEST_ALIGNMENT 128
775
776 /* Decide whether a variable of mode MODE must be 128 bit aligned. */
777 #define ALIGN_MODE_128(MODE) \
778 ((MODE) == XFmode || (MODE) == TFmode || ((MODE) == TImode) \
779 || (MODE) == V4SFmode || (MODE) == V4SImode)
780
781 /* The published ABIs say that doubles should be aligned on word
782 boundaries, so lower the aligment for structure fields unless
783 -malign-double is set. */
784 /* BIGGEST_FIELD_ALIGNMENT is also used in libobjc, where it must be
785 constant. Use the smaller value in that context. */
786 #ifndef IN_TARGET_LIBS
787 #define BIGGEST_FIELD_ALIGNMENT (TARGET_64BIT ? 128 : (TARGET_ALIGN_DOUBLE ? 64 : 32))
788 #else
789 #define BIGGEST_FIELD_ALIGNMENT 32
790 #endif
791
792 /* If defined, a C expression to compute the alignment given to a
793 constant that is being placed in memory. EXP is the constant
794 and ALIGN is the alignment that the object would ordinarily have.
795 The value of this macro is used instead of that alignment to align
796 the object.
797
798 If this macro is not defined, then ALIGN is used.
799
800 The typical use of this macro is to increase alignment for string
801 constants to be word aligned so that `strcpy' calls that copy
802 constants can be done inline. */
803
804 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
805
806 /* If defined, a C expression to compute the alignment for a static
807 variable. TYPE is the data type, and ALIGN is the alignment that
808 the object would ordinarily have. The value of this macro is used
809 instead of that alignment to align the object.
810
811 If this macro is not defined, then ALIGN is used.
812
813 One use of this macro is to increase alignment of medium-size
814 data to make it all fit in fewer cache lines. Another is to
815 cause character arrays to be word-aligned so that `strcpy' calls
816 that copy constants to character arrays can be done inline. */
817
818 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
819
820 /* If defined, a C expression to compute the alignment for a local
821 variable. TYPE is the data type, and ALIGN is the alignment that
822 the object would ordinarily have. The value of this macro is used
823 instead of that alignment to align the object.
824
825 If this macro is not defined, then ALIGN is used.
826
827 One use of this macro is to increase alignment of medium-size
828 data to make it all fit in fewer cache lines. */
829
830 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
831
832 /* If defined, a C expression that gives the alignment boundary, in
833 bits, of an argument with the specified mode and type. If it is
834 not defined, `PARM_BOUNDARY' is used for all arguments. */
835
836 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
837 ix86_function_arg_boundary ((MODE), (TYPE))
838
839 /* Set this non-zero if move instructions will actually fail to work
840 when given unaligned data. */
841 #define STRICT_ALIGNMENT 0
842
843 /* If bit field type is int, don't let it cross an int,
844 and give entire struct the alignment of an int. */
845 /* Required on the 386 since it doesn't have bitfield insns. */
846 #define PCC_BITFIELD_TYPE_MATTERS 1
847 \f
848 /* Standard register usage. */
849
850 /* This processor has special stack-like registers. See reg-stack.c
851 for details. */
852
853 #define STACK_REGS
854 #define IS_STACK_MODE(MODE) \
855 ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode \
856 || (MODE) == TFmode)
857
858 /* Number of actual hardware registers.
859 The hardware registers are assigned numbers for the compiler
860 from 0 to just below FIRST_PSEUDO_REGISTER.
861 All registers that the compiler knows about must be given numbers,
862 even those that are not normally considered general registers.
863
864 In the 80386 we give the 8 general purpose registers the numbers 0-7.
865 We number the floating point registers 8-15.
866 Note that registers 0-7 can be accessed as a short or int,
867 while only 0-3 may be used with byte `mov' instructions.
868
869 Reg 16 does not correspond to any hardware register, but instead
870 appears in the RTL as an argument pointer prior to reload, and is
871 eliminated during reloading in favor of either the stack or frame
872 pointer. */
873
874 #define FIRST_PSEUDO_REGISTER 53
875
876 /* Number of hardware registers that go into the DWARF-2 unwind info.
877 If not defined, equals FIRST_PSEUDO_REGISTER. */
878
879 #define DWARF_FRAME_REGISTERS 17
880
881 /* 1 for registers that have pervasive standard uses
882 and are not available for the register allocator.
883 On the 80386, the stack pointer is such, as is the arg pointer.
884
885 The value is an mask - bit 1 is set for fixed registers
886 for 32bit target, while 2 is set for fixed registers for 64bit.
887 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
888 */
889 #define FIXED_REGISTERS \
890 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
891 { 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \
892 /*arg,flags,fpsr,dir,frame*/ \
893 3, 3, 3, 3, 3, \
894 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
895 0, 0, 0, 0, 0, 0, 0, 0, \
896 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
897 0, 0, 0, 0, 0, 0, 0, 0, \
898 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
899 1, 1, 1, 1, 1, 1, 1, 1, \
900 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
901 1, 1, 1, 1, 1, 1, 1, 1}
902
903
904 /* 1 for registers not available across function calls.
905 These must include the FIXED_REGISTERS and also any
906 registers that can be used without being saved.
907 The latter must include the registers where values are returned
908 and the register where structure-value addresses are passed.
909 Aside from that, you can include as many other registers as you like.
910
911 The value is an mask - bit 1 is set for call used
912 for 32bit target, while 2 is set for call used for 64bit.
913 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
914 */
915 #define CALL_USED_REGISTERS \
916 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
917 { 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \
918 /*arg,flags,fpsr,dir,frame*/ \
919 3, 3, 3, 3, 3, \
920 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
921 3, 3, 3, 3, 3, 3, 3, 3, \
922 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
923 3, 3, 3, 3, 3, 3, 3, 3, \
924 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
925 3, 3, 3, 3, 1, 1, 1, 1, \
926 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
927 3, 3, 3, 3, 3, 3, 3, 3} \
928
929 /* Order in which to allocate registers. Each register must be
930 listed once, even those in FIXED_REGISTERS. List frame pointer
931 late and fixed registers last. Note that, in general, we prefer
932 registers listed in CALL_USED_REGISTERS, keeping the others
933 available for storage of persistent values.
934
935 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
936 so this is just empty initializer for array. */
937
938 #define REG_ALLOC_ORDER \
939 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
940 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
941 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
942 48, 49, 50, 51, 52 }
943
944 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
945 to be rearranged based on a particular function. When using sse math,
946 we want to allocase SSE before x87 registers and vice vera. */
947
948 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
949
950
951 /* Macro to conditionally modify fixed_regs/call_used_regs. */
952 #define CONDITIONAL_REGISTER_USAGE \
953 do { \
954 int i; \
955 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
956 { \
957 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \
958 call_used_regs[i] = (call_used_regs[i] \
959 & (TARGET_64BIT ? 2 : 1)) != 0; \
960 } \
961 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
962 { \
963 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
964 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
965 } \
966 if (! TARGET_MMX) \
967 { \
968 int i; \
969 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
970 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
971 fixed_regs[i] = call_used_regs[i] = 1; \
972 } \
973 if (! TARGET_SSE) \
974 { \
975 int i; \
976 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
977 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
978 fixed_regs[i] = call_used_regs[i] = 1; \
979 } \
980 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
981 { \
982 int i; \
983 HARD_REG_SET x; \
984 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
985 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
986 if (TEST_HARD_REG_BIT (x, i)) \
987 fixed_regs[i] = call_used_regs[i] = 1; \
988 } \
989 } while (0)
990
991 /* Return number of consecutive hard regs needed starting at reg REGNO
992 to hold something of mode MODE.
993 This is ordinarily the length in words of a value of mode MODE
994 but can be less for certain modes in special long registers.
995
996 Actually there are no two word move instructions for consecutive
997 registers. And only registers 0-3 may have mov byte instructions
998 applied to them.
999 */
1000
1001 #define HARD_REGNO_NREGS(REGNO, MODE) \
1002 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1003 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1004 : ((MODE) == TFmode \
1005 ? (TARGET_64BIT ? 2 : 3) \
1006 : (MODE) == TCmode \
1007 ? (TARGET_64BIT ? 4 : 6) \
1008 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
1009
1010 #define VALID_SSE_REG_MODE(MODE) \
1011 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1012 || (MODE) == SFmode \
1013 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE))))
1014
1015 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1016 ((MODE) == V2SFmode || (MODE) == SFmode)
1017
1018 #define VALID_MMX_REG_MODE(MODE) \
1019 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
1020 || (MODE) == V2SImode || (MODE) == SImode)
1021
1022 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1023 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \
1024 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \
1025 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0)
1026
1027 #define VALID_FP_MODE_P(MODE) \
1028 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
1029 || (!TARGET_64BIT && (MODE) == XFmode) \
1030 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == TCmode \
1031 || (!TARGET_64BIT && (MODE) == XCmode))
1032
1033 #define VALID_INT_MODE_P(MODE) \
1034 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1035 || (MODE) == DImode \
1036 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1037 || (MODE) == CDImode \
1038 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode)))
1039
1040 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1041
1042 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1043 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1044
1045 /* Value is 1 if it is a good idea to tie two pseudo registers
1046 when one has mode MODE1 and one has mode MODE2.
1047 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1048 for any hard reg, then this must be 0 for correct output. */
1049
1050 #define MODES_TIEABLE_P(MODE1, MODE2) \
1051 ((MODE1) == (MODE2) \
1052 || (((MODE1) == HImode || (MODE1) == SImode \
1053 || ((MODE1) == QImode \
1054 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1055 || ((MODE1) == DImode && TARGET_64BIT)) \
1056 && ((MODE2) == HImode || (MODE2) == SImode \
1057 || ((MODE1) == QImode \
1058 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1059 || ((MODE2) == DImode && TARGET_64BIT))))
1060
1061
1062 /* Specify the modes required to caller save a given hard regno.
1063 We do this on i386 to prevent flags from being saved at all.
1064
1065 Kill any attempts to combine saving of modes. */
1066
1067 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1068 (CC_REGNO_P (REGNO) ? VOIDmode \
1069 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1070 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \
1071 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1072 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1073 : (MODE))
1074 /* Specify the registers used for certain standard purposes.
1075 The values of these macros are register numbers. */
1076
1077 /* on the 386 the pc register is %eip, and is not usable as a general
1078 register. The ordinary mov instructions won't work */
1079 /* #define PC_REGNUM */
1080
1081 /* Register to use for pushing function arguments. */
1082 #define STACK_POINTER_REGNUM 7
1083
1084 /* Base register for access to local variables of the function. */
1085 #define HARD_FRAME_POINTER_REGNUM 6
1086
1087 /* Base register for access to local variables of the function. */
1088 #define FRAME_POINTER_REGNUM 20
1089
1090 /* First floating point reg */
1091 #define FIRST_FLOAT_REG 8
1092
1093 /* First & last stack-like regs */
1094 #define FIRST_STACK_REG FIRST_FLOAT_REG
1095 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1096
1097 #define FLAGS_REG 17
1098 #define FPSR_REG 18
1099 #define DIRFLAG_REG 19
1100
1101 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1102 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1103
1104 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1105 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1106
1107 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1108 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1109
1110 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1111 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1112
1113 /* Value should be nonzero if functions must have frame pointers.
1114 Zero means the frame pointer need not be set up (and parms
1115 may be accessed via the stack pointer) in functions that seem suitable.
1116 This is computed in `reload', in reload1.c. */
1117 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1118
1119 /* Override this in other tm.h files to cope with various OS losage
1120 requiring a frame pointer. */
1121 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1122 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1123 #endif
1124
1125 /* Make sure we can access arbitrary call frames. */
1126 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1127
1128 /* Base register for access to arguments of the function. */
1129 #define ARG_POINTER_REGNUM 16
1130
1131 /* Register in which static-chain is passed to a function.
1132 We do use ECX as static chain register for 32 bit ABI. On the
1133 64bit ABI, ECX is an argument register, so we use R10 instead. */
1134 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1135
1136 /* Register to hold the addressing base for position independent
1137 code access to data items. We don't use PIC pointer for 64bit
1138 mode. Define the regnum to dummy value to prevent gcc from
1139 pessimizing code dealing with EBX. */
1140 #define PIC_OFFSET_TABLE_REGNUM \
1141 (TARGET_64BIT || !flag_pic ? INVALID_REGNUM : 3)
1142
1143 /* Register in which address to store a structure value
1144 arrives in the function. On the 386, the prologue
1145 copies this from the stack to register %eax. */
1146 #define STRUCT_VALUE_INCOMING 0
1147
1148 /* Place in which caller passes the structure value address.
1149 0 means push the value on the stack like an argument. */
1150 #define STRUCT_VALUE 0
1151
1152 /* A C expression which can inhibit the returning of certain function
1153 values in registers, based on the type of value. A nonzero value
1154 says to return the function value in memory, just as large
1155 structures are always returned. Here TYPE will be a C expression
1156 of type `tree', representing the data type of the value.
1157
1158 Note that values of mode `BLKmode' must be explicitly handled by
1159 this macro. Also, the option `-fpcc-struct-return' takes effect
1160 regardless of this macro. On most systems, it is possible to
1161 leave the macro undefined; this causes a default definition to be
1162 used, whose value is the constant 1 for `BLKmode' values, and 0
1163 otherwise.
1164
1165 Do not use this macro to indicate that structures and unions
1166 should always be returned in memory. You should instead use
1167 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1168
1169 #define RETURN_IN_MEMORY(TYPE) \
1170 ix86_return_in_memory (TYPE)
1171
1172 \f
1173 /* Define the classes of registers for register constraints in the
1174 machine description. Also define ranges of constants.
1175
1176 One of the classes must always be named ALL_REGS and include all hard regs.
1177 If there is more than one class, another class must be named NO_REGS
1178 and contain no registers.
1179
1180 The name GENERAL_REGS must be the name of a class (or an alias for
1181 another name such as ALL_REGS). This is the class of registers
1182 that is allowed by "g" or "r" in a register constraint.
1183 Also, registers outside this class are allocated only when
1184 instructions express preferences for them.
1185
1186 The classes must be numbered in nondecreasing order; that is,
1187 a larger-numbered class must never be contained completely
1188 in a smaller-numbered class.
1189
1190 For any two classes, it is very desirable that there be another
1191 class that represents their union.
1192
1193 It might seem that class BREG is unnecessary, since no useful 386
1194 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1195 and the "b" register constraint is useful in asms for syscalls.
1196
1197 The flags and fpsr registers are in no class. */
1198
1199 enum reg_class
1200 {
1201 NO_REGS,
1202 AREG, DREG, CREG, BREG, SIREG, DIREG,
1203 AD_REGS, /* %eax/%edx for DImode */
1204 Q_REGS, /* %eax %ebx %ecx %edx */
1205 NON_Q_REGS, /* %esi %edi %ebp %esp */
1206 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1207 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1208 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1209 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
1210 FLOAT_REGS,
1211 SSE_REGS,
1212 MMX_REGS,
1213 FP_TOP_SSE_REGS,
1214 FP_SECOND_SSE_REGS,
1215 FLOAT_SSE_REGS,
1216 FLOAT_INT_REGS,
1217 INT_SSE_REGS,
1218 FLOAT_INT_SSE_REGS,
1219 ALL_REGS, LIM_REG_CLASSES
1220 };
1221
1222 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1223
1224 #define INTEGER_CLASS_P(CLASS) \
1225 reg_class_subset_p ((CLASS), GENERAL_REGS)
1226 #define FLOAT_CLASS_P(CLASS) \
1227 reg_class_subset_p ((CLASS), FLOAT_REGS)
1228 #define SSE_CLASS_P(CLASS) \
1229 reg_class_subset_p ((CLASS), SSE_REGS)
1230 #define MMX_CLASS_P(CLASS) \
1231 reg_class_subset_p ((CLASS), MMX_REGS)
1232 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1233 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1234 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1235 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1236 #define MAYBE_SSE_CLASS_P(CLASS) \
1237 reg_classes_intersect_p (SSE_REGS, (CLASS))
1238 #define MAYBE_MMX_CLASS_P(CLASS) \
1239 reg_classes_intersect_p (MMX_REGS, (CLASS))
1240
1241 #define Q_CLASS_P(CLASS) \
1242 reg_class_subset_p ((CLASS), Q_REGS)
1243
1244 /* Give names of register classes as strings for dump file. */
1245
1246 #define REG_CLASS_NAMES \
1247 { "NO_REGS", \
1248 "AREG", "DREG", "CREG", "BREG", \
1249 "SIREG", "DIREG", \
1250 "AD_REGS", \
1251 "Q_REGS", "NON_Q_REGS", \
1252 "INDEX_REGS", \
1253 "LEGACY_REGS", \
1254 "GENERAL_REGS", \
1255 "FP_TOP_REG", "FP_SECOND_REG", \
1256 "FLOAT_REGS", \
1257 "SSE_REGS", \
1258 "MMX_REGS", \
1259 "FP_TOP_SSE_REGS", \
1260 "FP_SECOND_SSE_REGS", \
1261 "FLOAT_SSE_REGS", \
1262 "FLOAT_INT_REGS", \
1263 "INT_SSE_REGS", \
1264 "FLOAT_INT_SSE_REGS", \
1265 "ALL_REGS" }
1266
1267 /* Define which registers fit in which classes.
1268 This is an initializer for a vector of HARD_REG_SET
1269 of length N_REG_CLASSES. */
1270
1271 #define REG_CLASS_CONTENTS \
1272 { { 0x00, 0x0 }, \
1273 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1274 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1275 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1276 { 0x03, 0x0 }, /* AD_REGS */ \
1277 { 0x0f, 0x0 }, /* Q_REGS */ \
1278 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1279 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1280 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1281 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1282 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1283 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1284 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1285 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1286 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1287 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1288 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1289 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1290 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1291 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1292 { 0xffffffff,0x1fffff } \
1293 }
1294
1295 /* The same information, inverted:
1296 Return the class number of the smallest class containing
1297 reg number REGNO. This could be a conditional expression
1298 or could index an array. */
1299
1300 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1301
1302 /* When defined, the compiler allows registers explicitly used in the
1303 rtl to be used as spill registers but prevents the compiler from
1304 extending the lifetime of these registers. */
1305
1306 #define SMALL_REGISTER_CLASSES 1
1307
1308 #define QI_REG_P(X) \
1309 (REG_P (X) && REGNO (X) < 4)
1310
1311 #define GENERAL_REGNO_P(N) \
1312 ((N) < 8 || REX_INT_REGNO_P (N))
1313
1314 #define GENERAL_REG_P(X) \
1315 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1316
1317 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1318
1319 #define NON_QI_REG_P(X) \
1320 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1321
1322 #define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG)
1323 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1324
1325 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1326 #define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG)
1327 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1328 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1329
1330 #define SSE_REGNO_P(N) \
1331 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \
1332 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG))
1333
1334 #define SSE_REGNO(N) \
1335 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1336 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1337
1338 #define SSE_FLOAT_MODE_P(MODE) \
1339 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1340
1341 #define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG)
1342 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1343
1344 #define STACK_REG_P(XOP) \
1345 (REG_P (XOP) && \
1346 REGNO (XOP) >= FIRST_STACK_REG && \
1347 REGNO (XOP) <= LAST_STACK_REG)
1348
1349 #define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP))
1350
1351 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1352
1353 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1354 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1355
1356 /* Indicate whether hard register numbered REG_NO should be converted
1357 to SSA form. */
1358 #define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \
1359 ((REG_NO) == FLAGS_REG || (REG_NO) == ARG_POINTER_REGNUM)
1360
1361 /* The class value for index registers, and the one for base regs. */
1362
1363 #define INDEX_REG_CLASS INDEX_REGS
1364 #define BASE_REG_CLASS GENERAL_REGS
1365
1366 /* Get reg_class from a letter such as appears in the machine description. */
1367
1368 #define REG_CLASS_FROM_LETTER(C) \
1369 ((C) == 'r' ? GENERAL_REGS : \
1370 (C) == 'R' ? LEGACY_REGS : \
1371 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
1372 (C) == 'Q' ? Q_REGS : \
1373 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1374 ? FLOAT_REGS \
1375 : NO_REGS) : \
1376 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1377 ? FP_TOP_REG \
1378 : NO_REGS) : \
1379 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1380 ? FP_SECOND_REG \
1381 : NO_REGS) : \
1382 (C) == 'a' ? AREG : \
1383 (C) == 'b' ? BREG : \
1384 (C) == 'c' ? CREG : \
1385 (C) == 'd' ? DREG : \
1386 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
1387 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
1388 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
1389 (C) == 'A' ? AD_REGS : \
1390 (C) == 'D' ? DIREG : \
1391 (C) == 'S' ? SIREG : NO_REGS)
1392
1393 /* The letters I, J, K, L and M in a register constraint string
1394 can be used to stand for particular ranges of immediate operands.
1395 This macro defines what the ranges are.
1396 C is the letter, and VALUE is a constant value.
1397 Return 1 if VALUE is in the range specified by C.
1398
1399 I is for non-DImode shifts.
1400 J is for DImode shifts.
1401 K is for signed imm8 operands.
1402 L is for andsi as zero-extending move.
1403 M is for shifts that can be executed by the "lea" opcode.
1404 N is for immedaite operands for out/in instructions (0-255)
1405 */
1406
1407 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1408 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
1409 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
1410 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
1411 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
1412 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
1413 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
1414 : 0)
1415
1416 /* Similar, but for floating constants, and defining letters G and H.
1417 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
1418 TARGET_387 isn't set, because the stack register converter may need to
1419 load 0.0 into the function value register. */
1420
1421 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1422 ((C) == 'G' ? standard_80387_constant_p (VALUE) \
1423 : ((C) == 'H' ? standard_sse_constant_p (VALUE) : 0))
1424
1425 /* A C expression that defines the optional machine-dependent
1426 constraint letters that can be used to segregate specific types of
1427 operands, usually memory references, for the target machine. Any
1428 letter that is not elsewhere defined and not matched by
1429 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not
1430 be defined.
1431
1432 If it is required for a particular target machine, it should
1433 return 1 if VALUE corresponds to the operand type represented by
1434 the constraint letter C. If C is not defined as an extra
1435 constraint, the value returned should be 0 regardless of VALUE. */
1436
1437 #define EXTRA_CONSTRAINT(VALUE, C) \
1438 ((C) == 'e' ? x86_64_sign_extended_value (VALUE) \
1439 : (C) == 'Z' ? x86_64_zero_extended_value (VALUE) \
1440 : 0)
1441
1442 /* Place additional restrictions on the register class to use when it
1443 is necessary to be able to hold a value of mode MODE in a reload
1444 register for which class CLASS would ordinarily be used. */
1445
1446 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1447 ((MODE) == QImode && !TARGET_64BIT \
1448 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1449 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1450 ? Q_REGS : (CLASS))
1451
1452 /* Given an rtx X being reloaded into a reg required to be
1453 in class CLASS, return the class of reg to actually use.
1454 In general this is just CLASS; but on some machines
1455 in some cases it is preferable to use a more restrictive class.
1456 On the 80386 series, we prevent floating constants from being
1457 reloaded into floating registers (since no move-insn can do that)
1458 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1459
1460 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1461 QImode must go into class Q_REGS.
1462 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1463 movdf to do mem-to-mem moves through integer regs. */
1464
1465 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1466 ix86_preferred_reload_class ((X), (CLASS))
1467
1468 /* If we are copying between general and FP registers, we need a memory
1469 location. The same is true for SSE and MMX registers. */
1470 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1471 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1472
1473 /* QImode spills from non-QI registers need a scratch. This does not
1474 happen often -- the only example so far requires an uninitialized
1475 pseudo. */
1476
1477 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1478 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1479 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1480 ? Q_REGS : NO_REGS)
1481
1482 /* Return the maximum number of consecutive registers
1483 needed to represent mode MODE in a register of class CLASS. */
1484 /* On the 80386, this is the size of MODE in words,
1485 except in the FP regs, where a single reg is always enough.
1486 The TFmodes are really just 80bit values, so we use only 3 registers
1487 to hold them, instead of 4, as the size would suggest.
1488 */
1489 #define CLASS_MAX_NREGS(CLASS, MODE) \
1490 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1491 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1492 : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \
1493 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1494
1495 /* A C expression whose value is nonzero if pseudos that have been
1496 assigned to registers of class CLASS would likely be spilled
1497 because registers of CLASS are needed for spill registers.
1498
1499 The default value of this macro returns 1 if CLASS has exactly one
1500 register and zero otherwise. On most machines, this default
1501 should be used. Only define this macro to some other expression
1502 if pseudo allocated by `local-alloc.c' end up in memory because
1503 their hard registers were needed for spill registers. If this
1504 macro returns nonzero for those classes, those pseudos will only
1505 be allocated by `global.c', which knows how to reallocate the
1506 pseudo to another register. If there would not be another
1507 register available for reallocation, you should not change the
1508 definition of this macro since the only effect of such a
1509 definition would be to slow down register allocation. */
1510
1511 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1512 (((CLASS) == AREG) \
1513 || ((CLASS) == DREG) \
1514 || ((CLASS) == CREG) \
1515 || ((CLASS) == BREG) \
1516 || ((CLASS) == AD_REGS) \
1517 || ((CLASS) == SIREG) \
1518 || ((CLASS) == DIREG))
1519
1520 /* A C statement that adds to CLOBBERS any hard regs the port wishes
1521 to automatically clobber for all asms.
1522
1523 We do this in the new i386 backend to maintain source compatibility
1524 with the old cc0-based compiler. */
1525
1526 #define MD_ASM_CLOBBERS(CLOBBERS) \
1527 do { \
1528 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), \
1529 (CLOBBERS)); \
1530 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), \
1531 (CLOBBERS)); \
1532 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), \
1533 (CLOBBERS)); \
1534 } while (0)
1535 \f
1536 /* Stack layout; function entry, exit and calling. */
1537
1538 /* Define this if pushing a word on the stack
1539 makes the stack pointer a smaller address. */
1540 #define STACK_GROWS_DOWNWARD
1541
1542 /* Define this if the nominal address of the stack frame
1543 is at the high-address end of the local variables;
1544 that is, each additional local variable allocated
1545 goes at a more negative offset in the frame. */
1546 #define FRAME_GROWS_DOWNWARD
1547
1548 /* Offset within stack frame to start allocating local variables at.
1549 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1550 first local allocated. Otherwise, it is the offset to the BEGINNING
1551 of the first local allocated. */
1552 #define STARTING_FRAME_OFFSET 0
1553
1554 /* If we generate an insn to push BYTES bytes,
1555 this says how many the stack pointer really advances by.
1556 On 386 pushw decrements by exactly 2 no matter what the position was.
1557 On the 386 there is no pushb; we use pushw instead, and this
1558 has the effect of rounding up to 2.
1559
1560 For 64bit ABI we round up to 8 bytes.
1561 */
1562
1563 #define PUSH_ROUNDING(BYTES) \
1564 (TARGET_64BIT \
1565 ? (((BYTES) + 7) & (-8)) \
1566 : (((BYTES) + 1) & (-2)))
1567
1568 /* If defined, the maximum amount of space required for outgoing arguments will
1569 be computed and placed into the variable
1570 `current_function_outgoing_args_size'. No space will be pushed onto the
1571 stack for each call; instead, the function prologue should increase the stack
1572 frame size by this amount. */
1573
1574 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1575
1576 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1577 instructions to pass outgoing arguments. */
1578
1579 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1580
1581 /* Offset of first parameter from the argument pointer register value. */
1582 #define FIRST_PARM_OFFSET(FNDECL) 0
1583
1584 /* Define this macro if functions should assume that stack space has been
1585 allocated for arguments even when their values are passed in registers.
1586
1587 The value of this macro is the size, in bytes, of the area reserved for
1588 arguments passed in registers for the function represented by FNDECL.
1589
1590 This space can be allocated by the caller, or be a part of the
1591 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1592 which. */
1593 #define REG_PARM_STACK_SPACE(FNDECL) 0
1594
1595 /* Define as a C expression that evaluates to nonzero if we do not know how
1596 to pass TYPE solely in registers. The file expr.h defines a
1597 definition that is usually appropriate, refer to expr.h for additional
1598 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be
1599 computed in the stack and then loaded into a register. */
1600 #define MUST_PASS_IN_STACK(MODE, TYPE) \
1601 ((TYPE) != 0 \
1602 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1603 || TREE_ADDRESSABLE (TYPE) \
1604 || ((MODE) == TImode) \
1605 || ((MODE) == BLKmode \
1606 && ! ((TYPE) != 0 \
1607 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
1608 && 0 == (int_size_in_bytes (TYPE) \
1609 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
1610 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
1611 == (BYTES_BIG_ENDIAN ? upward : downward)))))
1612
1613 /* Value is the number of bytes of arguments automatically
1614 popped when returning from a subroutine call.
1615 FUNDECL is the declaration node of the function (as a tree),
1616 FUNTYPE is the data type of the function (as a tree),
1617 or for a library call it is an identifier node for the subroutine name.
1618 SIZE is the number of bytes of arguments passed on the stack.
1619
1620 On the 80386, the RTD insn may be used to pop them if the number
1621 of args is fixed, but if the number is variable then the caller
1622 must pop them all. RTD can't be used for library calls now
1623 because the library is compiled with the Unix compiler.
1624 Use of RTD is a selectable option, since it is incompatible with
1625 standard Unix calling sequences. If the option is not selected,
1626 the caller must always pop the args.
1627
1628 The attribute stdcall is equivalent to RTD on a per module basis. */
1629
1630 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1631 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1632
1633 /* Define how to find the value returned by a function.
1634 VALTYPE is the data type of the value (as a tree).
1635 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1636 otherwise, FUNC is 0. */
1637 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1638 ix86_function_value (VALTYPE)
1639
1640 #define FUNCTION_VALUE_REGNO_P(N) \
1641 ix86_function_value_regno_p (N)
1642
1643 /* Define how to find the value returned by a library function
1644 assuming the value has mode MODE. */
1645
1646 #define LIBCALL_VALUE(MODE) \
1647 ix86_libcall_value (MODE)
1648
1649 /* Define the size of the result block used for communication between
1650 untyped_call and untyped_return. The block contains a DImode value
1651 followed by the block used by fnsave and frstor. */
1652
1653 #define APPLY_RESULT_SIZE (8+108)
1654
1655 /* 1 if N is a possible register number for function argument passing. */
1656 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1657
1658 /* Define a data type for recording info about an argument list
1659 during the scan of that argument list. This data type should
1660 hold all necessary information about the function itself
1661 and about the args processed so far, enough to enable macros
1662 such as FUNCTION_ARG to determine where the next arg should go. */
1663
1664 typedef struct ix86_args {
1665 int words; /* # words passed so far */
1666 int nregs; /* # registers available for passing */
1667 int regno; /* next available register number */
1668 int sse_words; /* # sse words passed so far */
1669 int sse_nregs; /* # sse registers available for passing */
1670 int sse_regno; /* next available sse register number */
1671 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
1672 } CUMULATIVE_ARGS;
1673
1674 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1675 for a call to a function whose data type is FNTYPE.
1676 For a library call, FNTYPE is 0. */
1677
1678 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1679 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME))
1680
1681 /* Update the data in CUM to advance over an argument
1682 of mode MODE and data type TYPE.
1683 (TYPE is null for libcalls where that information may not be available.) */
1684
1685 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1686 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1687
1688 /* Define where to put the arguments to a function.
1689 Value is zero to push the argument on the stack,
1690 or a hard register in which to store the argument.
1691
1692 MODE is the argument's machine mode.
1693 TYPE is the data type of the argument (as a tree).
1694 This is null for libcalls where that information may
1695 not be available.
1696 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1697 the preceding args and about the function being called.
1698 NAMED is nonzero if this argument is a named parameter
1699 (otherwise it is an extra parameter matching an ellipsis). */
1700
1701 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1702 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1703
1704 /* For an arg passed partly in registers and partly in memory,
1705 this is the number of registers used.
1706 For args passed entirely in registers or entirely in memory, zero. */
1707
1708 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1709
1710 /* If PIC, we cannot make sibling calls to global functions
1711 because the PLT requires %ebx live.
1712 If we are returning floats on the register stack, we cannot make
1713 sibling calls to functions that return floats. (The stack adjust
1714 instruction will wind up after the sibcall jump, and not be executed.) */
1715 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1716 ((DECL) \
1717 && (! flag_pic || ! TREE_PUBLIC (DECL)) \
1718 && (! TARGET_FLOAT_RETURNS_IN_80387 \
1719 || ! FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \
1720 || FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl))))))
1721
1722 /* Perform any needed actions needed for a function that is receiving a
1723 variable number of arguments.
1724
1725 CUM is as above.
1726
1727 MODE and TYPE are the mode and type of the current parameter.
1728
1729 PRETEND_SIZE is a variable that should be set to the amount of stack
1730 that must be pushed by the prolog to pretend that our caller pushed
1731 it.
1732
1733 Normally, this macro will push all remaining incoming registers on the
1734 stack and set PRETEND_SIZE to the length of the registers pushed. */
1735
1736 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1737 ix86_setup_incoming_varargs (&(CUM), (MODE), (TYPE), &(PRETEND_SIZE), \
1738 (NO_RTL))
1739
1740 /* Define the `__builtin_va_list' type for the ABI. */
1741 #define BUILD_VA_LIST_TYPE(VALIST) \
1742 ((VALIST) = ix86_build_va_list ())
1743
1744 /* Implement `va_start' for varargs and stdarg. */
1745 #define EXPAND_BUILTIN_VA_START(STDARG, VALIST, NEXTARG) \
1746 ix86_va_start ((STDARG), (VALIST), (NEXTARG))
1747
1748 /* Implement `va_arg'. */
1749 #define EXPAND_BUILTIN_VA_ARG(VALIST, TYPE) \
1750 ix86_va_arg ((VALIST), (TYPE))
1751
1752 /* This macro is invoked at the end of compilation. It is used here to
1753 output code for -fpic that will load the return address into %ebx. */
1754
1755 #undef ASM_FILE_END
1756 #define ASM_FILE_END(FILE) ix86_asm_file_end (FILE)
1757
1758 /* Output assembler code to FILE to increment profiler label # LABELNO
1759 for profiling a function entry. */
1760
1761 #define FUNCTION_PROFILER(FILE, LABELNO) \
1762 do { \
1763 if (flag_pic) \
1764 { \
1765 fprintf ((FILE), "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \
1766 LPREFIX, (LABELNO)); \
1767 fprintf ((FILE), "\tcall\t*_mcount@GOT(%%ebx)\n"); \
1768 } \
1769 else \
1770 { \
1771 fprintf ((FILE), "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \
1772 fprintf ((FILE), "\tcall\t_mcount\n"); \
1773 } \
1774 } while (0)
1775
1776 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1777 the stack pointer does not matter. The value is tested only in
1778 functions that have frame pointers.
1779 No definition is equivalent to always zero. */
1780 /* Note on the 386 it might be more efficient not to define this since
1781 we have to restore it ourselves from the frame pointer, in order to
1782 use pop */
1783
1784 #define EXIT_IGNORE_STACK 1
1785
1786 /* Output assembler code for a block containing the constant parts
1787 of a trampoline, leaving space for the variable parts. */
1788
1789 /* On the 386, the trampoline contains two instructions:
1790 mov #STATIC,ecx
1791 jmp FUNCTION
1792 The trampoline is generated entirely at runtime. The operand of JMP
1793 is the address of FUNCTION relative to the instruction following the
1794 JMP (which is 5 bytes long). */
1795
1796 /* Length in units of the trampoline for entering a nested function. */
1797
1798 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1799
1800 /* Emit RTL insns to initialize the variable parts of a trampoline.
1801 FNADDR is an RTX for the address of the function's pure code.
1802 CXT is an RTX for the static chain value for the function. */
1803
1804 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1805 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1806 \f
1807 /* Definitions for register eliminations.
1808
1809 This is an array of structures. Each structure initializes one pair
1810 of eliminable registers. The "from" register number is given first,
1811 followed by "to". Eliminations of the same "from" register are listed
1812 in order of preference.
1813
1814 There are two registers that can always be eliminated on the i386.
1815 The frame pointer and the arg pointer can be replaced by either the
1816 hard frame pointer or to the stack pointer, depending upon the
1817 circumstances. The hard frame pointer is not used before reload and
1818 so it is not eligible for elimination. */
1819
1820 #define ELIMINABLE_REGS \
1821 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1822 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1823 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1824 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1825
1826 /* Given FROM and TO register numbers, say whether this elimination is
1827 allowed. Frame pointer elimination is automatically handled.
1828
1829 All other eliminations are valid. */
1830
1831 #define CAN_ELIMINATE(FROM, TO) \
1832 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1833
1834 /* Define the offset between two registers, one to be eliminated, and the other
1835 its replacement, at the start of a routine. */
1836
1837 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1838 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1839 \f
1840 /* Addressing modes, and classification of registers for them. */
1841
1842 /* #define HAVE_POST_INCREMENT 0 */
1843 /* #define HAVE_POST_DECREMENT 0 */
1844
1845 /* #define HAVE_PRE_DECREMENT 0 */
1846 /* #define HAVE_PRE_INCREMENT 0 */
1847
1848 /* Macros to check register numbers against specific register classes. */
1849
1850 /* These assume that REGNO is a hard or pseudo reg number.
1851 They give nonzero only if REGNO is a hard reg of the suitable class
1852 or a pseudo reg currently allocated to a suitable hard reg.
1853 Since they use reg_renumber, they are safe only once reg_renumber
1854 has been allocated, which happens in local-alloc.c. */
1855
1856 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1857 ((REGNO) < STACK_POINTER_REGNUM \
1858 || (REGNO >= FIRST_REX_INT_REG \
1859 && (REGNO) <= LAST_REX_INT_REG) \
1860 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1861 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1862 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM)
1863
1864 #define REGNO_OK_FOR_BASE_P(REGNO) \
1865 ((REGNO) <= STACK_POINTER_REGNUM \
1866 || (REGNO) == ARG_POINTER_REGNUM \
1867 || (REGNO) == FRAME_POINTER_REGNUM \
1868 || (REGNO >= FIRST_REX_INT_REG \
1869 && (REGNO) <= LAST_REX_INT_REG) \
1870 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1871 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1872 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM)
1873
1874 #define REGNO_OK_FOR_SIREG_P(REGNO) \
1875 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4)
1876 #define REGNO_OK_FOR_DIREG_P(REGNO) \
1877 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5)
1878
1879 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1880 and check its validity for a certain class.
1881 We have two alternate definitions for each of them.
1882 The usual definition accepts all pseudo regs; the other rejects
1883 them unless they have been allocated suitable hard regs.
1884 The symbol REG_OK_STRICT causes the latter definition to be used.
1885
1886 Most source files want to accept pseudo regs in the hope that
1887 they will get allocated to the class that the insn wants them to be in.
1888 Source files for reload pass need to be strict.
1889 After reload, it makes no difference, since pseudo regs have
1890 been eliminated by then. */
1891
1892
1893 /* Non strict versions, pseudos are ok */
1894 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1895 (REGNO (X) < STACK_POINTER_REGNUM \
1896 || (REGNO (X) >= FIRST_REX_INT_REG \
1897 && REGNO (X) <= LAST_REX_INT_REG) \
1898 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1899
1900 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1901 (REGNO (X) <= STACK_POINTER_REGNUM \
1902 || REGNO (X) == ARG_POINTER_REGNUM \
1903 || REGNO (X) == FRAME_POINTER_REGNUM \
1904 || (REGNO (X) >= FIRST_REX_INT_REG \
1905 && REGNO (X) <= LAST_REX_INT_REG) \
1906 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1907
1908 /* Strict versions, hard registers only */
1909 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1910 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1911
1912 #ifndef REG_OK_STRICT
1913 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1914 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1915
1916 #else
1917 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1918 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1919 #endif
1920
1921 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1922 that is a valid memory address for an instruction.
1923 The MODE argument is the machine mode for the MEM expression
1924 that wants to use this address.
1925
1926 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1927 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1928
1929 See legitimize_pic_address in i386.c for details as to what
1930 constitutes a legitimate address when -fpic is used. */
1931
1932 #define MAX_REGS_PER_ADDRESS 2
1933
1934 #define CONSTANT_ADDRESS_P(X) \
1935 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1936 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1937 || GET_CODE (X) == CONST_DOUBLE)
1938
1939 /* Nonzero if the constant value X is a legitimate general operand.
1940 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1941
1942 #define LEGITIMATE_CONSTANT_P(X) 1
1943
1944 #ifdef REG_OK_STRICT
1945 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1946 do { \
1947 if (legitimate_address_p ((MODE), (X), 1)) \
1948 goto ADDR; \
1949 } while (0)
1950
1951 #else
1952 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1953 do { \
1954 if (legitimate_address_p ((MODE), (X), 0)) \
1955 goto ADDR; \
1956 } while (0)
1957
1958 #endif
1959
1960 /* If defined, a C expression to determine the base term of address X.
1961 This macro is used in only one place: `find_base_term' in alias.c.
1962
1963 It is always safe for this macro to not be defined. It exists so
1964 that alias analysis can understand machine-dependent addresses.
1965
1966 The typical use of this macro is to handle addresses containing
1967 a label_ref or symbol_ref within an UNSPEC. */
1968
1969 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1970
1971 /* Try machine-dependent ways of modifying an illegitimate address
1972 to be legitimate. If we find one, return the new, valid address.
1973 This macro is used in only one place: `memory_address' in explow.c.
1974
1975 OLDX is the address as it was before break_out_memory_refs was called.
1976 In some cases it is useful to look at this to decide what needs to be done.
1977
1978 MODE and WIN are passed so that this macro can use
1979 GO_IF_LEGITIMATE_ADDRESS.
1980
1981 It is always safe for this macro to do nothing. It exists to recognize
1982 opportunities to optimize the output.
1983
1984 For the 80386, we handle X+REG by loading X into a register R and
1985 using R+REG. R will go in a general reg and indexing will be used.
1986 However, if REG is a broken-out memory address or multiplication,
1987 nothing needs to be done because REG can certainly go in a general reg.
1988
1989 When -fpic is used, special handling is needed for symbolic references.
1990 See comments by legitimize_pic_address in i386.c for details. */
1991
1992 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1993 do { \
1994 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1995 if (memory_address_p ((MODE), (X))) \
1996 goto WIN; \
1997 } while (0)
1998
1999 #define REWRITE_ADDRESS(X) rewrite_address (X)
2000
2001 /* Nonzero if the constant value X is a legitimate general operand
2002 when generating PIC code. It is given that flag_pic is on and
2003 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
2004
2005 #define LEGITIMATE_PIC_OPERAND_P(X) \
2006 (! SYMBOLIC_CONST (X) \
2007 || legitimate_pic_address_disp_p (X))
2008
2009 #define SYMBOLIC_CONST(X) \
2010 (GET_CODE (X) == SYMBOL_REF \
2011 || GET_CODE (X) == LABEL_REF \
2012 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
2013
2014 /* Go to LABEL if ADDR (a legitimate address expression)
2015 has an effect that depends on the machine mode it is used for.
2016 On the 80386, only postdecrement and postincrement address depend thus
2017 (the amount of decrement or increment being the length of the operand). */
2018 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2019 do { \
2020 if (GET_CODE (ADDR) == POST_INC \
2021 || GET_CODE (ADDR) == POST_DEC) \
2022 goto LABEL; \
2023 } while (0)
2024 \f
2025 /* Codes for all the SSE/MMX builtins. */
2026 enum ix86_builtins
2027 {
2028 IX86_BUILTIN_ADDPS,
2029 IX86_BUILTIN_ADDSS,
2030 IX86_BUILTIN_DIVPS,
2031 IX86_BUILTIN_DIVSS,
2032 IX86_BUILTIN_MULPS,
2033 IX86_BUILTIN_MULSS,
2034 IX86_BUILTIN_SUBPS,
2035 IX86_BUILTIN_SUBSS,
2036
2037 IX86_BUILTIN_CMPEQPS,
2038 IX86_BUILTIN_CMPLTPS,
2039 IX86_BUILTIN_CMPLEPS,
2040 IX86_BUILTIN_CMPGTPS,
2041 IX86_BUILTIN_CMPGEPS,
2042 IX86_BUILTIN_CMPNEQPS,
2043 IX86_BUILTIN_CMPNLTPS,
2044 IX86_BUILTIN_CMPNLEPS,
2045 IX86_BUILTIN_CMPNGTPS,
2046 IX86_BUILTIN_CMPNGEPS,
2047 IX86_BUILTIN_CMPORDPS,
2048 IX86_BUILTIN_CMPUNORDPS,
2049 IX86_BUILTIN_CMPNEPS,
2050 IX86_BUILTIN_CMPEQSS,
2051 IX86_BUILTIN_CMPLTSS,
2052 IX86_BUILTIN_CMPLESS,
2053 IX86_BUILTIN_CMPGTSS,
2054 IX86_BUILTIN_CMPGESS,
2055 IX86_BUILTIN_CMPNEQSS,
2056 IX86_BUILTIN_CMPNLTSS,
2057 IX86_BUILTIN_CMPNLESS,
2058 IX86_BUILTIN_CMPNGTSS,
2059 IX86_BUILTIN_CMPNGESS,
2060 IX86_BUILTIN_CMPORDSS,
2061 IX86_BUILTIN_CMPUNORDSS,
2062 IX86_BUILTIN_CMPNESS,
2063
2064 IX86_BUILTIN_COMIEQSS,
2065 IX86_BUILTIN_COMILTSS,
2066 IX86_BUILTIN_COMILESS,
2067 IX86_BUILTIN_COMIGTSS,
2068 IX86_BUILTIN_COMIGESS,
2069 IX86_BUILTIN_COMINEQSS,
2070 IX86_BUILTIN_UCOMIEQSS,
2071 IX86_BUILTIN_UCOMILTSS,
2072 IX86_BUILTIN_UCOMILESS,
2073 IX86_BUILTIN_UCOMIGTSS,
2074 IX86_BUILTIN_UCOMIGESS,
2075 IX86_BUILTIN_UCOMINEQSS,
2076
2077 IX86_BUILTIN_CVTPI2PS,
2078 IX86_BUILTIN_CVTPS2PI,
2079 IX86_BUILTIN_CVTSI2SS,
2080 IX86_BUILTIN_CVTSS2SI,
2081 IX86_BUILTIN_CVTTPS2PI,
2082 IX86_BUILTIN_CVTTSS2SI,
2083
2084 IX86_BUILTIN_MAXPS,
2085 IX86_BUILTIN_MAXSS,
2086 IX86_BUILTIN_MINPS,
2087 IX86_BUILTIN_MINSS,
2088
2089 IX86_BUILTIN_LOADAPS,
2090 IX86_BUILTIN_LOADUPS,
2091 IX86_BUILTIN_STOREAPS,
2092 IX86_BUILTIN_STOREUPS,
2093 IX86_BUILTIN_LOADSS,
2094 IX86_BUILTIN_STORESS,
2095 IX86_BUILTIN_MOVSS,
2096
2097 IX86_BUILTIN_MOVHLPS,
2098 IX86_BUILTIN_MOVLHPS,
2099 IX86_BUILTIN_LOADHPS,
2100 IX86_BUILTIN_LOADLPS,
2101 IX86_BUILTIN_STOREHPS,
2102 IX86_BUILTIN_STORELPS,
2103
2104 IX86_BUILTIN_MASKMOVQ,
2105 IX86_BUILTIN_MOVMSKPS,
2106 IX86_BUILTIN_PMOVMSKB,
2107
2108 IX86_BUILTIN_MOVNTPS,
2109 IX86_BUILTIN_MOVNTQ,
2110
2111 IX86_BUILTIN_PACKSSWB,
2112 IX86_BUILTIN_PACKSSDW,
2113 IX86_BUILTIN_PACKUSWB,
2114
2115 IX86_BUILTIN_PADDB,
2116 IX86_BUILTIN_PADDW,
2117 IX86_BUILTIN_PADDD,
2118 IX86_BUILTIN_PADDSB,
2119 IX86_BUILTIN_PADDSW,
2120 IX86_BUILTIN_PADDUSB,
2121 IX86_BUILTIN_PADDUSW,
2122 IX86_BUILTIN_PSUBB,
2123 IX86_BUILTIN_PSUBW,
2124 IX86_BUILTIN_PSUBD,
2125 IX86_BUILTIN_PSUBSB,
2126 IX86_BUILTIN_PSUBSW,
2127 IX86_BUILTIN_PSUBUSB,
2128 IX86_BUILTIN_PSUBUSW,
2129
2130 IX86_BUILTIN_PAND,
2131 IX86_BUILTIN_PANDN,
2132 IX86_BUILTIN_POR,
2133 IX86_BUILTIN_PXOR,
2134
2135 IX86_BUILTIN_PAVGB,
2136 IX86_BUILTIN_PAVGW,
2137
2138 IX86_BUILTIN_PCMPEQB,
2139 IX86_BUILTIN_PCMPEQW,
2140 IX86_BUILTIN_PCMPEQD,
2141 IX86_BUILTIN_PCMPGTB,
2142 IX86_BUILTIN_PCMPGTW,
2143 IX86_BUILTIN_PCMPGTD,
2144
2145 IX86_BUILTIN_PEXTRW,
2146 IX86_BUILTIN_PINSRW,
2147
2148 IX86_BUILTIN_PMADDWD,
2149
2150 IX86_BUILTIN_PMAXSW,
2151 IX86_BUILTIN_PMAXUB,
2152 IX86_BUILTIN_PMINSW,
2153 IX86_BUILTIN_PMINUB,
2154
2155 IX86_BUILTIN_PMULHUW,
2156 IX86_BUILTIN_PMULHW,
2157 IX86_BUILTIN_PMULLW,
2158
2159 IX86_BUILTIN_PSADBW,
2160 IX86_BUILTIN_PSHUFW,
2161
2162 IX86_BUILTIN_PSLLW,
2163 IX86_BUILTIN_PSLLD,
2164 IX86_BUILTIN_PSLLQ,
2165 IX86_BUILTIN_PSRAW,
2166 IX86_BUILTIN_PSRAD,
2167 IX86_BUILTIN_PSRLW,
2168 IX86_BUILTIN_PSRLD,
2169 IX86_BUILTIN_PSRLQ,
2170 IX86_BUILTIN_PSLLWI,
2171 IX86_BUILTIN_PSLLDI,
2172 IX86_BUILTIN_PSLLQI,
2173 IX86_BUILTIN_PSRAWI,
2174 IX86_BUILTIN_PSRADI,
2175 IX86_BUILTIN_PSRLWI,
2176 IX86_BUILTIN_PSRLDI,
2177 IX86_BUILTIN_PSRLQI,
2178
2179 IX86_BUILTIN_PUNPCKHBW,
2180 IX86_BUILTIN_PUNPCKHWD,
2181 IX86_BUILTIN_PUNPCKHDQ,
2182 IX86_BUILTIN_PUNPCKLBW,
2183 IX86_BUILTIN_PUNPCKLWD,
2184 IX86_BUILTIN_PUNPCKLDQ,
2185
2186 IX86_BUILTIN_SHUFPS,
2187
2188 IX86_BUILTIN_RCPPS,
2189 IX86_BUILTIN_RCPSS,
2190 IX86_BUILTIN_RSQRTPS,
2191 IX86_BUILTIN_RSQRTSS,
2192 IX86_BUILTIN_SQRTPS,
2193 IX86_BUILTIN_SQRTSS,
2194
2195 IX86_BUILTIN_UNPCKHPS,
2196 IX86_BUILTIN_UNPCKLPS,
2197
2198 IX86_BUILTIN_ANDPS,
2199 IX86_BUILTIN_ANDNPS,
2200 IX86_BUILTIN_ORPS,
2201 IX86_BUILTIN_XORPS,
2202
2203 IX86_BUILTIN_EMMS,
2204 IX86_BUILTIN_LDMXCSR,
2205 IX86_BUILTIN_STMXCSR,
2206 IX86_BUILTIN_SFENCE,
2207
2208 /* 3DNow! Original */
2209 IX86_BUILTIN_FEMMS,
2210 IX86_BUILTIN_PAVGUSB,
2211 IX86_BUILTIN_PF2ID,
2212 IX86_BUILTIN_PFACC,
2213 IX86_BUILTIN_PFADD,
2214 IX86_BUILTIN_PFCMPEQ,
2215 IX86_BUILTIN_PFCMPGE,
2216 IX86_BUILTIN_PFCMPGT,
2217 IX86_BUILTIN_PFMAX,
2218 IX86_BUILTIN_PFMIN,
2219 IX86_BUILTIN_PFMUL,
2220 IX86_BUILTIN_PFRCP,
2221 IX86_BUILTIN_PFRCPIT1,
2222 IX86_BUILTIN_PFRCPIT2,
2223 IX86_BUILTIN_PFRSQIT1,
2224 IX86_BUILTIN_PFRSQRT,
2225 IX86_BUILTIN_PFSUB,
2226 IX86_BUILTIN_PFSUBR,
2227 IX86_BUILTIN_PI2FD,
2228 IX86_BUILTIN_PMULHRW,
2229
2230 /* 3DNow! Athlon Extensions */
2231 IX86_BUILTIN_PF2IW,
2232 IX86_BUILTIN_PFNACC,
2233 IX86_BUILTIN_PFPNACC,
2234 IX86_BUILTIN_PI2FW,
2235 IX86_BUILTIN_PSWAPDSI,
2236 IX86_BUILTIN_PSWAPDSF,
2237
2238 IX86_BUILTIN_SSE_ZERO,
2239 IX86_BUILTIN_MMX_ZERO,
2240
2241 IX86_BUILTIN_MAX
2242 };
2243 \f
2244 /* Define this macro if references to a symbol must be treated
2245 differently depending on something about the variable or
2246 function named by the symbol (such as what section it is in).
2247
2248 On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol
2249 so that we may access it directly in the GOT. */
2250
2251 #define ENCODE_SECTION_INFO(DECL) \
2252 do { \
2253 if (flag_pic) \
2254 { \
2255 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2256 ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \
2257 \
2258 if (GET_CODE (rtl) == MEM) \
2259 { \
2260 if (TARGET_DEBUG_ADDR \
2261 && TREE_CODE_CLASS (TREE_CODE (DECL)) == 'd') \
2262 { \
2263 fprintf (stderr, "Encode %s, public = %d\n", \
2264 IDENTIFIER_POINTER (DECL_NAME (DECL)), \
2265 TREE_PUBLIC (DECL)); \
2266 } \
2267 \
2268 SYMBOL_REF_FLAG (XEXP (rtl, 0)) \
2269 = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2270 || ! TREE_PUBLIC (DECL)); \
2271 } \
2272 } \
2273 } while (0)
2274
2275 /* The `FINALIZE_PIC' macro serves as a hook to emit these special
2276 codes once the function is being compiled into assembly code, but
2277 not before. (It is not done before, because in the case of
2278 compiling an inline function, it would lead to multiple PIC
2279 prologues being included in functions which used inline functions
2280 and were compiled to assembly language.) */
2281
2282 #define FINALIZE_PIC \
2283 (current_function_uses_pic_offset_table |= current_function_profile)
2284
2285 \f
2286 /* Max number of args passed in registers. If this is more than 3, we will
2287 have problems with ebx (register #4), since it is a caller save register and
2288 is also used as the pic register in ELF. So for now, don't allow more than
2289 3 registers to be passed in registers. */
2290
2291 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
2292
2293 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : 0)
2294
2295 \f
2296 /* Specify the machine mode that this machine uses
2297 for the index in the tablejump instruction. */
2298 #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
2299
2300 /* Define as C expression which evaluates to nonzero if the tablejump
2301 instruction expects the table to contain offsets from the address of the
2302 table.
2303 Do not define this if the table should contain absolute addresses. */
2304 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2305
2306 /* Define this as 1 if `char' should by default be signed; else as 0. */
2307 #define DEFAULT_SIGNED_CHAR 1
2308
2309 /* Number of bytes moved into a data cache for a single prefetch operation. */
2310 #define PREFETCH_BLOCK ix86_cost->prefetch_block
2311
2312 /* Number of prefetch operations that can be done in parallel. */
2313 #define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
2314
2315 /* Max number of bytes we can move from memory to memory
2316 in one reasonably fast instruction. */
2317 #define MOVE_MAX 16
2318
2319 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
2320 move efficiently, as opposed to MOVE_MAX which is the maximum
2321 number of bytes we can move with a single instruction. */
2322 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
2323
2324 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2325 move-instruction pairs, we will do a movstr or libcall instead.
2326 Increasing the value will always make code faster, but eventually
2327 incurs high cost in increased code size.
2328
2329 If you don't define this, a reasonable default is used. */
2330
2331 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
2332
2333 /* Define if shifts truncate the shift count
2334 which implies one can omit a sign-extension or zero-extension
2335 of a shift count. */
2336 /* On i386, shifts do truncate the count. But bit opcodes don't. */
2337
2338 /* #define SHIFT_COUNT_TRUNCATED */
2339
2340 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2341 is done just by pretending it is already truncated. */
2342 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2343
2344 /* We assume that the store-condition-codes instructions store 0 for false
2345 and some other value for true. This is the value stored for true. */
2346
2347 #define STORE_FLAG_VALUE 1
2348
2349 /* When a prototype says `char' or `short', really pass an `int'.
2350 (The 386 can't easily push less than an int.) */
2351
2352 #define PROMOTE_PROTOTYPES (!TARGET_64BIT)
2353
2354 /* A macro to update M and UNSIGNEDP when an object whose type is
2355 TYPE and which has the specified mode and signedness is to be
2356 stored in a register. This macro is only called when TYPE is a
2357 scalar type.
2358
2359 On i386 it is sometimes useful to promote HImode and QImode
2360 quantities to SImode. The choice depends on target type. */
2361
2362 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2363 do { \
2364 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
2365 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
2366 (MODE) = SImode; \
2367 } while (0)
2368
2369 /* Specify the machine mode that pointers have.
2370 After generation of rtl, the compiler makes no further distinction
2371 between pointers and any other objects of this machine mode. */
2372 #define Pmode (TARGET_64BIT ? DImode : SImode)
2373
2374 /* A function address in a call instruction
2375 is a byte address (for indexing purposes)
2376 so give the MEM rtx a byte's mode. */
2377 #define FUNCTION_MODE QImode
2378 \f
2379 /* A part of a C `switch' statement that describes the relative costs
2380 of constant RTL expressions. It must contain `case' labels for
2381 expression codes `const_int', `const', `symbol_ref', `label_ref'
2382 and `const_double'. Each case must ultimately reach a `return'
2383 statement to return the relative cost of the use of that kind of
2384 constant value in an expression. The cost may depend on the
2385 precise value of the constant, which is available for examination
2386 in X, and the rtx code of the expression in which it is contained,
2387 found in OUTER_CODE.
2388
2389 CODE is the expression code--redundant, since it can be obtained
2390 with `GET_CODE (X)'. */
2391
2392 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
2393 case CONST_INT: \
2394 case CONST: \
2395 case LABEL_REF: \
2396 case SYMBOL_REF: \
2397 if (TARGET_64BIT && !x86_64_sign_extended_value (RTX)) \
2398 return 3; \
2399 if (TARGET_64BIT && !x86_64_zero_extended_value (RTX)) \
2400 return 2; \
2401 return flag_pic && SYMBOLIC_CONST (RTX) ? 1 : 0; \
2402 \
2403 case CONST_DOUBLE: \
2404 { \
2405 int code; \
2406 if (GET_MODE (RTX) == VOIDmode) \
2407 return 0; \
2408 \
2409 code = standard_80387_constant_p (RTX); \
2410 return code == 1 ? 1 : \
2411 code == 2 ? 2 : \
2412 3; \
2413 }
2414
2415 /* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */
2416 #define TOPLEVEL_COSTS_N_INSNS(N) \
2417 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0)
2418
2419 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
2420 This can be used, for example, to indicate how costly a multiply
2421 instruction is. In writing this macro, you can use the construct
2422 `COSTS_N_INSNS (N)' to specify a cost equal to N fast
2423 instructions. OUTER_CODE is the code of the expression in which X
2424 is contained.
2425
2426 This macro is optional; do not define it if the default cost
2427 assumptions are adequate for the target machine. */
2428
2429 #define RTX_COSTS(X, CODE, OUTER_CODE) \
2430 case ZERO_EXTEND: \
2431 /* The zero extensions is often completely free on x86_64, so make \
2432 it as cheap as possible. */ \
2433 if (TARGET_64BIT && GET_MODE (X) == DImode \
2434 && GET_MODE (XEXP (X, 0)) == SImode) \
2435 { \
2436 total = 1; goto egress_rtx_costs; \
2437 } \
2438 else \
2439 TOPLEVEL_COSTS_N_INSNS (TARGET_ZERO_EXTEND_WITH_AND ? \
2440 ix86_cost->add : ix86_cost->movzx); \
2441 break; \
2442 case SIGN_EXTEND: \
2443 TOPLEVEL_COSTS_N_INSNS (ix86_cost->movsx); \
2444 break; \
2445 case ASHIFT: \
2446 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2447 && (GET_MODE (XEXP (X, 0)) != DImode || TARGET_64BIT)) \
2448 { \
2449 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2450 if (value == 1) \
2451 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2452 if ((value == 2 || value == 3) \
2453 && !TARGET_DECOMPOSE_LEA \
2454 && ix86_cost->lea <= ix86_cost->shift_const) \
2455 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \
2456 } \
2457 /* fall through */ \
2458 \
2459 case ROTATE: \
2460 case ASHIFTRT: \
2461 case LSHIFTRT: \
2462 case ROTATERT: \
2463 if (!TARGET_64BIT && GET_MODE (XEXP (X, 0)) == DImode) \
2464 { \
2465 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2466 { \
2467 if (INTVAL (XEXP (X, 1)) > 32) \
2468 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \
2469 else \
2470 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \
2471 } \
2472 else \
2473 { \
2474 if (GET_CODE (XEXP (X, 1)) == AND) \
2475 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \
2476 else \
2477 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \
2478 } \
2479 } \
2480 else \
2481 { \
2482 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2483 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \
2484 else \
2485 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \
2486 } \
2487 break; \
2488 \
2489 case MULT: \
2490 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2491 { \
2492 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2493 int nbits = 0; \
2494 \
2495 while (value != 0) \
2496 { \
2497 nbits++; \
2498 value >>= 1; \
2499 } \
2500 \
2501 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2502 + nbits * ix86_cost->mult_bit); \
2503 } \
2504 else /* This is arbitrary */ \
2505 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2506 + 7 * ix86_cost->mult_bit); \
2507 \
2508 case DIV: \
2509 case UDIV: \
2510 case MOD: \
2511 case UMOD: \
2512 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \
2513 \
2514 case PLUS: \
2515 if (!TARGET_DECOMPOSE_LEA \
2516 && INTEGRAL_MODE_P (GET_MODE (X)) \
2517 && GET_MODE_BITSIZE (GET_MODE (X)) <= GET_MODE_BITSIZE (Pmode)) \
2518 { \
2519 if (GET_CODE (XEXP (X, 0)) == PLUS \
2520 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \
2521 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \
2522 && CONSTANT_P (XEXP (X, 1))) \
2523 { \
2524 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1));\
2525 if (val == 2 || val == 4 || val == 8) \
2526 { \
2527 return (COSTS_N_INSNS (ix86_cost->lea) \
2528 + rtx_cost (XEXP (XEXP (X, 0), 1), \
2529 (OUTER_CODE)) \
2530 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), \
2531 (OUTER_CODE)) \
2532 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2533 } \
2534 } \
2535 else if (GET_CODE (XEXP (X, 0)) == MULT \
2536 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
2537 { \
2538 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
2539 if (val == 2 || val == 4 || val == 8) \
2540 { \
2541 return (COSTS_N_INSNS (ix86_cost->lea) \
2542 + rtx_cost (XEXP (XEXP (X, 0), 0), \
2543 (OUTER_CODE)) \
2544 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2545 } \
2546 } \
2547 else if (GET_CODE (XEXP (X, 0)) == PLUS) \
2548 { \
2549 return (COSTS_N_INSNS (ix86_cost->lea) \
2550 + rtx_cost (XEXP (XEXP (X, 0), 0), (OUTER_CODE)) \
2551 + rtx_cost (XEXP (XEXP (X, 0), 1), (OUTER_CODE)) \
2552 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2553 } \
2554 } \
2555 \
2556 /* fall through */ \
2557 case AND: \
2558 case IOR: \
2559 case XOR: \
2560 case MINUS: \
2561 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2562 return (COSTS_N_INSNS (ix86_cost->add) * 2 \
2563 + (rtx_cost (XEXP (X, 0), (OUTER_CODE)) \
2564 << (GET_MODE (XEXP (X, 0)) != DImode)) \
2565 + (rtx_cost (XEXP (X, 1), (OUTER_CODE)) \
2566 << (GET_MODE (XEXP (X, 1)) != DImode))); \
2567 \
2568 /* fall through */ \
2569 case NEG: \
2570 case NOT: \
2571 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2572 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \
2573 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2574 \
2575 egress_rtx_costs: \
2576 break;
2577
2578
2579 /* An expression giving the cost of an addressing mode that contains
2580 ADDRESS. If not defined, the cost is computed from the ADDRESS
2581 expression and the `CONST_COSTS' values.
2582
2583 For most CISC machines, the default cost is a good approximation
2584 of the true cost of the addressing mode. However, on RISC
2585 machines, all instructions normally have the same length and
2586 execution time. Hence all addresses will have equal costs.
2587
2588 In cases where more than one form of an address is known, the form
2589 with the lowest cost will be used. If multiple forms have the
2590 same, lowest, cost, the one that is the most complex will be used.
2591
2592 For example, suppose an address that is equal to the sum of a
2593 register and a constant is used twice in the same basic block.
2594 When this macro is not defined, the address will be computed in a
2595 register and memory references will be indirect through that
2596 register. On machines where the cost of the addressing mode
2597 containing the sum is no higher than that of a simple indirect
2598 reference, this will produce an additional instruction and
2599 possibly require an additional register. Proper specification of
2600 this macro eliminates this overhead for such machines.
2601
2602 Similar use of this macro is made in strength reduction of loops.
2603
2604 ADDRESS need not be valid as an address. In such a case, the cost
2605 is not relevant and can be any value; invalid addresses need not be
2606 assigned a different cost.
2607
2608 On machines where an address involving more than one register is as
2609 cheap as an address computation involving only one register,
2610 defining `ADDRESS_COST' to reflect this can cause two registers to
2611 be live over a region of code where only one would have been if
2612 `ADDRESS_COST' were not defined in that manner. This effect should
2613 be considered in the definition of this macro. Equivalent costs
2614 should probably only be given to addresses with different numbers
2615 of registers on machines with lots of registers.
2616
2617 This macro will normally either not be defined or be defined as a
2618 constant.
2619
2620 For i386, it is better to use a complex address than let gcc copy
2621 the address into a reg and make a new pseudo. But not if the address
2622 requires to two regs - that would mean more pseudos with longer
2623 lifetimes. */
2624
2625 #define ADDRESS_COST(RTX) \
2626 ix86_address_cost (RTX)
2627
2628 /* A C expression for the cost of moving data from a register in class FROM to
2629 one in class TO. The classes are expressed using the enumeration values
2630 such as `GENERAL_REGS'. A value of 2 is the default; other values are
2631 interpreted relative to that.
2632
2633 It is not required that the cost always equal 2 when FROM is the same as TO;
2634 on some machines it is expensive to move between registers if they are not
2635 general registers. */
2636
2637 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2638 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
2639
2640 /* A C expression for the cost of moving data of mode M between a
2641 register and memory. A value of 2 is the default; this cost is
2642 relative to those in `REGISTER_MOVE_COST'.
2643
2644 If moving between registers and memory is more expensive than
2645 between two registers, you should define this macro to express the
2646 relative cost. */
2647
2648 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
2649 ix86_memory_move_cost ((MODE), (CLASS), (IN))
2650
2651 /* A C expression for the cost of a branch instruction. A value of 1
2652 is the default; other values are interpreted relative to that. */
2653
2654 #define BRANCH_COST ix86_branch_cost
2655
2656 /* Define this macro as a C expression which is nonzero if accessing
2657 less than a word of memory (i.e. a `char' or a `short') is no
2658 faster than accessing a word of memory, i.e., if such access
2659 require more than one instruction or if there is no difference in
2660 cost between byte and (aligned) word loads.
2661
2662 When this macro is not defined, the compiler will access a field by
2663 finding the smallest containing object; when it is defined, a
2664 fullword load will be used if alignment permits. Unless bytes
2665 accesses are faster than word accesses, using word accesses is
2666 preferable since it may eliminate subsequent memory access if
2667 subsequent accesses occur to other fields in the same word of the
2668 structure, but to different bytes. */
2669
2670 #define SLOW_BYTE_ACCESS 0
2671
2672 /* Nonzero if access to memory by shorts is slow and undesirable. */
2673 #define SLOW_SHORT_ACCESS 0
2674
2675 /* Define this macro to be the value 1 if unaligned accesses have a
2676 cost many times greater than aligned accesses, for example if they
2677 are emulated in a trap handler.
2678
2679 When this macro is non-zero, the compiler will act as if
2680 `STRICT_ALIGNMENT' were non-zero when generating code for block
2681 moves. This can cause significantly more instructions to be
2682 produced. Therefore, do not set this macro non-zero if unaligned
2683 accesses only add a cycle or two to the time for a memory access.
2684
2685 If the value of this macro is always zero, it need not be defined. */
2686
2687 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2688
2689 /* Define this macro to inhibit strength reduction of memory
2690 addresses. (On some machines, such strength reduction seems to do
2691 harm rather than good.) */
2692
2693 /* #define DONT_REDUCE_ADDR */
2694
2695 /* Define this macro if it is as good or better to call a constant
2696 function address than to call an address kept in a register.
2697
2698 Desirable on the 386 because a CALL with a constant address is
2699 faster than one with a register address. */
2700
2701 #define NO_FUNCTION_CSE
2702
2703 /* Define this macro if it is as good or better for a function to call
2704 itself with an explicit address than to call an address kept in a
2705 register. */
2706
2707 #define NO_RECURSIVE_FUNCTION_CSE
2708 \f
2709 /* Add any extra modes needed to represent the condition code.
2710
2711 For the i386, we need separate modes when floating-point
2712 equality comparisons are being done.
2713
2714 Add CCNO to indicate comparisons against zero that requires
2715 Overflow flag to be unset. Sign bit test is used instead and
2716 thus can be used to form "a&b>0" type of tests.
2717
2718 Add CCGC to indicate comparisons agains zero that allows
2719 unspecified garbage in the Carry flag. This mode is used
2720 by inc/dec instructions.
2721
2722 Add CCGOC to indicate comparisons agains zero that allows
2723 unspecified garbage in the Carry and Overflow flag. This
2724 mode is used to simulate comparisons of (a-b) and (a+b)
2725 against zero using sub/cmp/add operations.
2726
2727 Add CCZ to indicate that only the Zero flag is valid. */
2728
2729 #define EXTRA_CC_MODES \
2730 CC (CCGCmode, "CCGC") \
2731 CC (CCGOCmode, "CCGOC") \
2732 CC (CCNOmode, "CCNO") \
2733 CC (CCZmode, "CCZ") \
2734 CC (CCFPmode, "CCFP") \
2735 CC (CCFPUmode, "CCFPU")
2736
2737 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2738 return the mode to be used for the comparison.
2739
2740 For floating-point equality comparisons, CCFPEQmode should be used.
2741 VOIDmode should be used in all other cases.
2742
2743 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2744 possible, to allow for more combinations. */
2745
2746 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2747
2748 /* Return non-zero if MODE implies a floating point inequality can be
2749 reversed. */
2750
2751 #define REVERSIBLE_CC_MODE(MODE) 1
2752
2753 /* A C expression whose value is reversed condition code of the CODE for
2754 comparison done in CC_MODE mode. */
2755 #define REVERSE_CONDITION(CODE, MODE) \
2756 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \
2757 : reverse_condition_maybe_unordered (CODE))
2758
2759 \f
2760 /* Control the assembler format that we output, to the extent
2761 this does not vary between assemblers. */
2762
2763 /* How to refer to registers in assembler output.
2764 This sequence is indexed by compiler's hard-register-number (see above). */
2765
2766 /* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
2767 For non floating point regs, the following are the HImode names.
2768
2769 For float regs, the stack top is sometimes referred to as "%st(0)"
2770 instead of just "%st". PRINT_REG handles this with the "y" code. */
2771
2772 #undef HI_REGISTER_NAMES
2773 #define HI_REGISTER_NAMES \
2774 {"ax","dx","cx","bx","si","di","bp","sp", \
2775 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
2776 "flags","fpsr", "dirflag", "frame", \
2777 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2778 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
2779 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2780 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2781
2782 #define REGISTER_NAMES HI_REGISTER_NAMES
2783
2784 /* Table of additional register names to use in user input. */
2785
2786 #define ADDITIONAL_REGISTER_NAMES \
2787 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2788 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2789 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2790 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2791 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2792 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
2793 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \
2794 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} }
2795
2796 /* Note we are omitting these since currently I don't know how
2797 to get gcc to use these, since they want the same but different
2798 number as al, and ax.
2799 */
2800
2801 #define QI_REGISTER_NAMES \
2802 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2803
2804 /* These parallel the array above, and can be used to access bits 8:15
2805 of regs 0 through 3. */
2806
2807 #define QI_HIGH_REGISTER_NAMES \
2808 {"ah", "dh", "ch", "bh", }
2809
2810 /* How to renumber registers for dbx and gdb. */
2811
2812 #define DBX_REGISTER_NUMBER(N) \
2813 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2814
2815 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
2816 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER];
2817 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
2818
2819 /* Before the prologue, RA is at 0(%esp). */
2820 #define INCOMING_RETURN_ADDR_RTX \
2821 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2822
2823 /* After the prologue, RA is at -4(AP) in the current frame. */
2824 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2825 ((COUNT) == 0 \
2826 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2827 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2828
2829 /* PC is dbx register 8; let's use that column for RA. */
2830 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2831
2832 /* Before the prologue, the top of the frame is at 4(%esp). */
2833 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2834
2835 /* Describe how we implement __builtin_eh_return. */
2836 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2837 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2838
2839
2840 /* Select a format to encode pointers in exception handling data. CODE
2841 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2842 true if the symbol may be affected by dynamic relocations.
2843
2844 ??? All x86 object file formats are capable of representing this.
2845 After all, the relocation needed is the same as for the call insn.
2846 Whether or not a particular assembler allows us to enter such, I
2847 guess we'll have to see. */
2848 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2849 (flag_pic \
2850 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
2851 : DW_EH_PE_absptr)
2852
2853 /* This is how to output the definition of a user-level label named NAME,
2854 such as the label on a static function or variable NAME. */
2855
2856 #define ASM_OUTPUT_LABEL(FILE, NAME) \
2857 (assemble_name ((FILE), (NAME)), fputs (":\n", (FILE)))
2858
2859 /* Store in OUTPUT a string (made with alloca) containing
2860 an assembler-name for a local static variable named NAME.
2861 LABELNO is an integer which is different for each call. */
2862
2863 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2864 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2865 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2866
2867 /* This is how to output an insn to push a register on the stack.
2868 It need not be very fast code. */
2869
2870 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2871 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)])
2872
2873 /* This is how to output an insn to pop a register from the stack.
2874 It need not be very fast code. */
2875
2876 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2877 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)])
2878
2879 /* This is how to output an element of a case-vector that is absolute. */
2880
2881 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2882 ix86_output_addr_vec_elt ((FILE), (VALUE))
2883
2884 /* This is how to output an element of a case-vector that is relative. */
2885
2886 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2887 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2888
2889 /* Under some conditions we need jump tables in the text section, because
2890 the assembler cannot handle label differences between sections. */
2891
2892 #define JUMP_TABLES_IN_TEXT_SECTION \
2893 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA)
2894
2895 /* A C statement that outputs an address constant appropriate to
2896 for DWARF debugging. */
2897
2898 #define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \
2899 i386_dwarf_output_addr_const ((FILE), (X))
2900
2901 /* Either simplify a location expression, or return the original. */
2902
2903 #define ASM_SIMPLIFY_DWARF_ADDR(X) \
2904 i386_simplify_dwarf_addr (X)
2905
2906 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2907 and switch back. For x86 we do this only to save a few bytes that
2908 would otherwise be unused in the text section. */
2909 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2910 asm (SECTION_OP "\n\t" \
2911 "call " USER_LABEL_PREFIX #FUNC "\n" \
2912 TEXT_SECTION_ASM_OP);
2913 \f
2914 /* Print operand X (an rtx) in assembler syntax to file FILE.
2915 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2916 Effect of various CODE letters is described in i386.c near
2917 print_operand function. */
2918
2919 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2920 ((CODE) == '*' || (CODE) == '+')
2921
2922 /* Print the name of a register based on its machine mode and number.
2923 If CODE is 'w', pretend the mode is HImode.
2924 If CODE is 'b', pretend the mode is QImode.
2925 If CODE is 'k', pretend the mode is SImode.
2926 If CODE is 'q', pretend the mode is DImode.
2927 If CODE is 'h', pretend the reg is the `high' byte register.
2928 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
2929
2930 #define PRINT_REG(X, CODE, FILE) \
2931 print_reg ((X), (CODE), (FILE))
2932
2933 #define PRINT_OPERAND(FILE, X, CODE) \
2934 print_operand ((FILE), (X), (CODE))
2935
2936 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2937 print_operand_address ((FILE), (ADDR))
2938
2939 /* Print the name of a register for based on its machine mode and number.
2940 This macro is used to print debugging output.
2941 This macro is different from PRINT_REG in that it may be used in
2942 programs that are not linked with aux-output.o. */
2943
2944 #define DEBUG_PRINT_REG(X, CODE, FILE) \
2945 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \
2946 static const char * const qi_name[] = QI_REGISTER_NAMES; \
2947 fprintf ((FILE), "%d ", REGNO (X)); \
2948 if (REGNO (X) == FLAGS_REG) \
2949 { fputs ("flags", (FILE)); break; } \
2950 if (REGNO (X) == DIRFLAG_REG) \
2951 { fputs ("dirflag", (FILE)); break; } \
2952 if (REGNO (X) == FPSR_REG) \
2953 { fputs ("fpsr", (FILE)); break; } \
2954 if (REGNO (X) == ARG_POINTER_REGNUM) \
2955 { fputs ("argp", (FILE)); break; } \
2956 if (REGNO (X) == FRAME_POINTER_REGNUM) \
2957 { fputs ("frame", (FILE)); break; } \
2958 if (STACK_TOP_P (X)) \
2959 { fputs ("st(0)", (FILE)); break; } \
2960 if (FP_REG_P (X)) \
2961 { fputs (hi_name[REGNO(X)], (FILE)); break; } \
2962 if (REX_INT_REG_P (X)) \
2963 { \
2964 switch (GET_MODE_SIZE (GET_MODE (X))) \
2965 { \
2966 default: \
2967 case 8: \
2968 fprintf ((FILE), "r%i", REGNO (X) \
2969 - FIRST_REX_INT_REG + 8); \
2970 break; \
2971 case 4: \
2972 fprintf ((FILE), "r%id", REGNO (X) \
2973 - FIRST_REX_INT_REG + 8); \
2974 break; \
2975 case 2: \
2976 fprintf ((FILE), "r%iw", REGNO (X) \
2977 - FIRST_REX_INT_REG + 8); \
2978 break; \
2979 case 1: \
2980 fprintf ((FILE), "r%ib", REGNO (X) \
2981 - FIRST_REX_INT_REG + 8); \
2982 break; \
2983 } \
2984 break; \
2985 } \
2986 switch (GET_MODE_SIZE (GET_MODE (X))) \
2987 { \
2988 case 8: \
2989 fputs ("r", (FILE)); \
2990 fputs (hi_name[REGNO (X)], (FILE)); \
2991 break; \
2992 default: \
2993 fputs ("e", (FILE)); \
2994 case 2: \
2995 fputs (hi_name[REGNO (X)], (FILE)); \
2996 break; \
2997 case 1: \
2998 fputs (qi_name[REGNO (X)], (FILE)); \
2999 break; \
3000 } \
3001 } while (0)
3002
3003 /* a letter which is not needed by the normal asm syntax, which
3004 we can use for operand syntax in the extended asm */
3005
3006 #define ASM_OPERAND_LETTER '#'
3007 #define RET return ""
3008 #define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
3009 \f
3010 /* Define the codes that are matched by predicates in i386.c. */
3011
3012 #define PREDICATE_CODES \
3013 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \
3014 SYMBOL_REF, LABEL_REF, CONST}}, \
3015 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3016 SYMBOL_REF, LABEL_REF, CONST}}, \
3017 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \
3018 SYMBOL_REF, LABEL_REF, CONST}}, \
3019 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3020 SYMBOL_REF, LABEL_REF, CONST}}, \
3021 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3022 SYMBOL_REF, LABEL_REF, CONST}}, \
3023 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3024 SYMBOL_REF, LABEL_REF, CONST}}, \
3025 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3026 SYMBOL_REF, LABEL_REF}}, \
3027 {"shiftdi_operand", {SUBREG, REG, MEM}}, \
3028 {"const_int_1_operand", {CONST_INT}}, \
3029 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
3030 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3031 LABEL_REF, SUBREG, REG, MEM}}, \
3032 {"pic_symbolic_operand", {CONST}}, \
3033 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \
3034 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \
3035 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
3036 {"const1_operand", {CONST_INT}}, \
3037 {"const248_operand", {CONST_INT}}, \
3038 {"incdec_operand", {CONST_INT}}, \
3039 {"mmx_reg_operand", {REG}}, \
3040 {"reg_no_sp_operand", {SUBREG, REG}}, \
3041 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3042 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
3043 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
3044 {"q_regs_operand", {SUBREG, REG}}, \
3045 {"non_q_regs_operand", {SUBREG, REG}}, \
3046 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
3047 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \
3048 GE, UNGE, LTGT, UNEQ}}, \
3049 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \
3050 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \
3051 }}, \
3052 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \
3053 GTU, UNORDERED, ORDERED, UNLE, UNLT, \
3054 UNGE, UNGT, LTGT, UNEQ }}, \
3055 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \
3056 {"ext_register_operand", {SUBREG, REG}}, \
3057 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \
3058 {"mult_operator", {MULT}}, \
3059 {"div_operator", {DIV}}, \
3060 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \
3061 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \
3062 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \
3063 LSHIFTRT, ROTATERT}}, \
3064 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \
3065 {"memory_displacement_operand", {MEM}}, \
3066 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3067 LABEL_REF, SUBREG, REG, MEM, AND}}, \
3068 {"long_memory_operand", {MEM}},
3069
3070 /* A list of predicates that do special things with modes, and so
3071 should not elicit warnings for VOIDmode match_operand. */
3072
3073 #define SPECIAL_MODE_PREDICATES \
3074 "ext_register_operand",
3075 \f
3076 /* CM_32 is used by 32bit ABI
3077 CM_SMALL is small model assuming that all code and data fits in the first
3078 31bits of address space.
3079 CM_KERNEL is model assuming that all code and data fits in the negative
3080 31bits of address space.
3081 CM_MEDIUM is model assuming that code fits in the first 31bits of address
3082 space. Size of data is unlimited.
3083 CM_LARGE is model making no assumptions about size of particular sections.
3084
3085 CM_SMALL_PIC is model for PIC libraries assuming that code+data+got/plt
3086 tables first in 31bits of address space.
3087 */
3088 enum cmodel {
3089 CM_32,
3090 CM_SMALL,
3091 CM_KERNEL,
3092 CM_MEDIUM,
3093 CM_LARGE,
3094 CM_SMALL_PIC
3095 };
3096
3097 /* Size of the RED_ZONE area. */
3098 #define RED_ZONE_SIZE 128
3099 /* Reserved area of the red zone for temporaries. */
3100 #define RED_ZONE_RESERVE 8
3101 extern const char *ix86_debug_arg_string, *ix86_debug_addr_string;
3102
3103 enum asm_dialect {
3104 ASM_ATT,
3105 ASM_INTEL
3106 };
3107 extern const char *ix86_asm_string;
3108 extern enum asm_dialect ix86_asm_dialect;
3109 /* Value of -mcmodel specified by user. */
3110 extern const char *ix86_cmodel_string;
3111 extern enum cmodel ix86_cmodel;
3112 \f
3113 /* Variables in i386.c */
3114 extern const char *ix86_cpu_string; /* for -mcpu=<xxx> */
3115 extern const char *ix86_arch_string; /* for -march=<xxx> */
3116 extern const char *ix86_fpmath_string; /* for -mfpmath=<xxx> */
3117 extern const char *ix86_regparm_string; /* # registers to use to pass args */
3118 extern const char *ix86_align_loops_string; /* power of two alignment for loops */
3119 extern const char *ix86_align_jumps_string; /* power of two alignment for non-loop jumps */
3120 extern const char *ix86_align_funcs_string; /* power of two alignment for functions */
3121 extern const char *ix86_preferred_stack_boundary_string;/* power of two alignment for stack boundary */
3122 extern const char *ix86_branch_cost_string; /* values 1-5: see jump.c */
3123 extern int ix86_regparm; /* ix86_regparm_string as a number */
3124 extern int ix86_preferred_stack_boundary; /* preferred stack boundary alignment in bits */
3125 extern int ix86_branch_cost; /* values 1-5: see jump.c */
3126 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; /* smalled class containing REGNO */
3127 // Commented out the following two lines due to lack of definition for "rtx" - Brian
3128 //extern rtx ix86_compare_op0; /* operand 0 for comparisons */
3129 //extern rtx ix86_compare_op1; /* operand 1 for comparisons */
3130 \f
3131 /* To properly truncate FP values into integers, we need to set i387 control
3132 word. We can't emit proper mode switching code before reload, as spills
3133 generated by reload may truncate values incorrectly, but we still can avoid
3134 redundant computation of new control word by the mode switching pass.
3135 The fldcw instructions are still emitted redundantly, but this is probably
3136 not going to be noticeable problem, as most CPUs do have fast path for
3137 the sequence.
3138
3139 The machinery is to emit simple truncation instructions and split them
3140 before reload to instructions having USEs of two memory locations that
3141 are filled by this code to old and new control word.
3142
3143 Post-reload pass may be later used to eliminate the redundant fildcw if
3144 needed. */
3145
3146 enum fp_cw_mode {FP_CW_STORED, FP_CW_UNINITIALIZED, FP_CW_ANY};
3147
3148 /* Define this macro if the port needs extra instructions inserted
3149 for mode switching in an optimizing compilation. */
3150
3151 #define OPTIMIZE_MODE_SWITCHING(ENTITY) 1
3152
3153 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
3154 initializer for an array of integers. Each initializer element N
3155 refers to an entity that needs mode switching, and specifies the
3156 number of different modes that might need to be set for this
3157 entity. The position of the initializer in the initializer -
3158 starting counting at zero - determines the integer that is used to
3159 refer to the mode-switched entity in question. */
3160
3161 #define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY }
3162
3163 /* ENTITY is an integer specifying a mode-switched entity. If
3164 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
3165 return an integer value not larger than the corresponding element
3166 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
3167 must be switched into prior to the execution of INSN. */
3168
3169 #define MODE_NEEDED(ENTITY, I) \
3170 (GET_CODE (I) == CALL_INSN \
3171 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \
3172 || GET_CODE (PATTERN (I)) == ASM_INPUT))\
3173 ? FP_CW_UNINITIALIZED \
3174 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \
3175 ? FP_CW_ANY \
3176 : FP_CW_STORED)
3177
3178 /* This macro specifies the order in which modes for ENTITY are
3179 processed. 0 is the highest priority. */
3180
3181 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
3182
3183 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
3184 is the set of hard registers live at the point where the insn(s)
3185 are to be inserted. */
3186
3187 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3188 ((MODE) == FP_CW_STORED \
3189 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \
3190 assign_386_stack_local (HImode, 2)), 0\
3191 : 0)
3192 \f
3193 /* Avoid renaming of stack registers, as doing so in combination with
3194 scheduling just increases amount of live registers at time and in
3195 the turn amount of fxch instructions needed.
3196
3197 ??? Maybe Pentium chips benefits from renaming, someone can try... */
3198
3199 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
3200 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG)
3201
3202 \f
3203 /*
3204 Local variables:
3205 version-control: t
3206 End:
3207 */