1 /* Definitions of target machine for GNU compiler for IA-32.
2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* The purpose of this file is to define the characteristics of the i386,
23 independent of assembler syntax or operating system.
25 Three other files build on this one to describe a specific assembler syntax:
26 bsd386.h, att386.h, and sun386.h.
28 The actual tm.h file for a particular system should include
29 this file, and then the file for the appropriate assembler syntax.
31 Many macros that specify assembler syntax are omitted entirely from
32 this file because they really belong in the files for particular
33 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,
34 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many
35 that start with ASM_ or end in ASM_OP. */
37 /* Stubs for half-pic support if not OSF/1 reference platform. */
40 #define HALF_PIC_P() 0
41 #define HALF_PIC_NUMBER_PTRS 0
42 #define HALF_PIC_NUMBER_REFS 0
43 #define HALF_PIC_ENCODE(DECL)
44 #define HALF_PIC_DECLARE(NAME)
45 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it")
46 #define HALF_PIC_ADDRESS_P(X) 0
47 #define HALF_PIC_PTR(X) (X)
48 #define HALF_PIC_FINISH(STREAM)
51 /* Define the specific costs for a given cpu */
53 struct processor_costs
{
54 const int add
; /* cost of an add instruction */
55 const int lea
; /* cost of a lea instruction */
56 const int shift_var
; /* variable shift costs */
57 const int shift_const
; /* constant shift costs */
58 const int mult_init
; /* cost of starting a multiply */
59 const int mult_bit
; /* cost of multiply per each bit set */
60 const int divide
; /* cost of a divide/mod */
61 int movsx
; /* The cost of movsx operation. */
62 int movzx
; /* The cost of movzx operation. */
63 const int large_insn
; /* insns larger than this cost more */
64 const int move_ratio
; /* The threshold of number of scalar
65 memory-to-memory move insns. */
66 const int movzbl_load
; /* cost of loading using movzbl */
67 const int int_load
[3]; /* cost of loading integer registers
68 in QImode, HImode and SImode relative
69 to reg-reg move (2). */
70 const int int_store
[3]; /* cost of storing integer register
71 in QImode, HImode and SImode */
72 const int fp_move
; /* cost of reg,reg fld/fst */
73 const int fp_load
[3]; /* cost of loading FP register
74 in SFmode, DFmode and XFmode */
75 const int fp_store
[3]; /* cost of storing FP register
76 in SFmode, DFmode and XFmode */
77 const int mmx_move
; /* cost of moving MMX register. */
78 const int mmx_load
[2]; /* cost of loading MMX register
79 in SImode and DImode */
80 const int mmx_store
[2]; /* cost of storing MMX register
81 in SImode and DImode */
82 const int sse_move
; /* cost of moving SSE register. */
83 const int sse_load
[3]; /* cost of loading SSE register
84 in SImode, DImode and TImode*/
85 const int sse_store
[3]; /* cost of storing SSE register
86 in SImode, DImode and TImode*/
87 const int mmxsse_to_integer
; /* cost of moving mmxsse register to
88 integer and vice versa. */
89 const int prefetch_block
; /* bytes moved to cache for prefetch. */
90 const int simultaneous_prefetches
; /* number of parallel prefetch
94 extern const struct processor_costs
*ix86_cost
;
96 /* Run-time compilation parameters selecting different hardware subsets. */
98 extern int target_flags
;
100 /* Macros used in the machine description to test the flags. */
102 /* configure can arrange to make this 2, to force a 486. */
104 #ifndef TARGET_CPU_DEFAULT
105 #define TARGET_CPU_DEFAULT 0
108 /* Masks for the -m switches */
109 #define MASK_80387 0x00000001 /* Hardware floating point */
110 #define MASK_RTD 0x00000002 /* Use ret that pops args */
111 #define MASK_ALIGN_DOUBLE 0x00000004 /* align doubles to 2 word boundary */
112 #define MASK_SVR3_SHLIB 0x00000008 /* Uninit locals into bss */
113 #define MASK_IEEE_FP 0x00000010 /* IEEE fp comparisons */
114 #define MASK_FLOAT_RETURNS 0x00000020 /* Return float in st(0) */
115 #define MASK_NO_FANCY_MATH_387 0x00000040 /* Disable sin, cos, sqrt */
116 #define MASK_OMIT_LEAF_FRAME_POINTER 0x080 /* omit leaf frame pointers */
117 #define MASK_STACK_PROBE 0x00000100 /* Enable stack probing */
118 #define MASK_NO_ALIGN_STROPS 0x00000200 /* Enable aligning of string ops. */
119 #define MASK_INLINE_ALL_STROPS 0x00000400 /* Inline stringops in all cases */
120 #define MASK_NO_PUSH_ARGS 0x00000800 /* Use push instructions */
121 #define MASK_ACCUMULATE_OUTGOING_ARGS 0x00001000/* Accumulate outgoing args */
122 #define MASK_ACCUMULATE_OUTGOING_ARGS_SET 0x00002000
123 #define MASK_MMX 0x00004000 /* Support MMX regs/builtins */
124 #define MASK_MMX_SET 0x00008000
125 #define MASK_SSE 0x00010000 /* Support SSE regs/builtins */
126 #define MASK_SSE_SET 0x00020000
127 #define MASK_SSE2 0x00040000 /* Support SSE2 regs/builtins */
128 #define MASK_SSE2_SET 0x00080000
129 #define MASK_3DNOW 0x00100000 /* Support 3Dnow builtins */
130 #define MASK_3DNOW_SET 0x00200000
131 #define MASK_3DNOW_A 0x00400000 /* Support Athlon 3Dnow builtins */
132 #define MASK_3DNOW_A_SET 0x00800000
133 #define MASK_128BIT_LONG_DOUBLE 0x01000000 /* long double size is 128bit */
134 #define MASK_64BIT 0x02000000 /* Produce 64bit code */
135 /* ... overlap with subtarget options starts by 0x04000000. */
136 #define MASK_NO_RED_ZONE 0x04000000 /* Do not use red zone */
138 /* Use the floating point instructions */
139 #define TARGET_80387 (target_flags & MASK_80387)
141 /* Compile using ret insn that pops args.
142 This will not work unless you use prototypes at least
143 for all functions that can take varying numbers of args. */
144 #define TARGET_RTD (target_flags & MASK_RTD)
146 /* Align doubles to a two word boundary. This breaks compatibility with
147 the published ABI's for structures containing doubles, but produces
148 faster code on the pentium. */
149 #define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE)
151 /* Use push instructions to save outgoing args. */
152 #define TARGET_PUSH_ARGS (!(target_flags & MASK_NO_PUSH_ARGS))
154 /* Accumulate stack adjustments to prologue/epilogue. */
155 #define TARGET_ACCUMULATE_OUTGOING_ARGS \
156 (target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)
158 /* Put uninitialized locals into bss, not data.
159 Meaningful only on svr3. */
160 #define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB)
162 /* Use IEEE floating point comparisons. These handle correctly the cases
163 where the result of a comparison is unordered. Normally SIGFPE is
164 generated in such cases, in which case this isn't needed. */
165 #define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP)
167 /* Functions that return a floating point value may return that value
168 in the 387 FPU or in 386 integer registers. If set, this flag causes
169 the 387 to be used, which is compatible with most calling conventions. */
170 #define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS)
172 /* Long double is 128bit instead of 96bit, even when only 80bits are used.
173 This mode wastes cache, but avoid misaligned data accesses and simplifies
174 address calculations. */
175 #define TARGET_128BIT_LONG_DOUBLE (target_flags & MASK_128BIT_LONG_DOUBLE)
177 /* Disable generation of FP sin, cos and sqrt operations for 387.
178 This is because FreeBSD lacks these in the math-emulator-code */
179 #define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
181 /* Don't create frame pointers for leaf functions */
182 #define TARGET_OMIT_LEAF_FRAME_POINTER \
183 (target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
185 /* Debug GO_IF_LEGITIMATE_ADDRESS */
186 #define TARGET_DEBUG_ADDR (ix86_debug_addr_string != 0)
188 /* Debug FUNCTION_ARG macros */
189 #define TARGET_DEBUG_ARG (ix86_debug_arg_string != 0)
192 /* 64bit Sledgehammer mode */
193 #ifdef TARGET_BI_ARCH
194 #define TARGET_64BIT (target_flags & MASK_64BIT)
196 #ifdef TARGET_64BIT_DEFAULT
197 #define TARGET_64BIT 1
199 #define TARGET_64BIT 0
203 #define TARGET_386 (ix86_cpu == PROCESSOR_I386)
204 #define TARGET_486 (ix86_cpu == PROCESSOR_I486)
205 #define TARGET_PENTIUM (ix86_cpu == PROCESSOR_PENTIUM)
206 #define TARGET_PENTIUMPRO (ix86_cpu == PROCESSOR_PENTIUMPRO)
207 #define TARGET_K6 (ix86_cpu == PROCESSOR_K6)
208 #define TARGET_ATHLON (ix86_cpu == PROCESSOR_ATHLON)
209 #define TARGET_PENTIUM4 (ix86_cpu == PROCESSOR_PENTIUM4)
211 #define CPUMASK (1 << ix86_cpu)
212 extern const int x86_use_leave
, x86_push_memory
, x86_zero_extend_with_and
;
213 extern const int x86_use_bit_test
, x86_cmove
, x86_deep_branch
;
214 extern const int x86_branch_hints
, x86_unroll_strlen
;
215 extern const int x86_double_with_add
, x86_partial_reg_stall
, x86_movx
;
216 extern const int x86_use_loop
, x86_use_fiop
, x86_use_mov0
;
217 extern const int x86_use_cltd
, x86_read_modify_write
;
218 extern const int x86_read_modify
, x86_split_long_moves
;
219 extern const int x86_promote_QImode
, x86_single_stringop
;
220 extern const int x86_himode_math
, x86_qimode_math
, x86_promote_qi_regs
;
221 extern const int x86_promote_hi_regs
, x86_integer_DFmode_moves
;
222 extern const int x86_add_esp_4
, x86_add_esp_8
, x86_sub_esp_4
, x86_sub_esp_8
;
223 extern const int x86_partial_reg_dependency
, x86_memory_mismatch_stall
;
224 extern const int x86_accumulate_outgoing_args
, x86_prologue_using_move
;
225 extern const int x86_epilogue_using_move
, x86_decompose_lea
;
226 extern const int x86_arch_always_fancy_math_387
;
227 extern int x86_prefetch_sse
;
229 #define TARGET_USE_LEAVE (x86_use_leave & CPUMASK)
230 #define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK)
231 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK)
232 #define TARGET_USE_BIT_TEST (x86_use_bit_test & CPUMASK)
233 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK)
234 /* For sane SSE instruction set generation we need fcomi instruction. It is
235 safe to enable all CMOVE instructions. */
236 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
237 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK)
238 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK)
239 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK)
240 #define TARGET_USE_SAHF ((x86_use_sahf & CPUMASK) && !TARGET_64BIT)
241 #define TARGET_MOVX (x86_movx & CPUMASK)
242 #define TARGET_PARTIAL_REG_STALL (x86_partial_reg_stall & CPUMASK)
243 #define TARGET_USE_LOOP (x86_use_loop & CPUMASK)
244 #define TARGET_USE_FIOP (x86_use_fiop & CPUMASK)
245 #define TARGET_USE_MOV0 (x86_use_mov0 & CPUMASK)
246 #define TARGET_USE_CLTD (x86_use_cltd & CPUMASK)
247 #define TARGET_SPLIT_LONG_MOVES (x86_split_long_moves & CPUMASK)
248 #define TARGET_READ_MODIFY_WRITE (x86_read_modify_write & CPUMASK)
249 #define TARGET_READ_MODIFY (x86_read_modify & CPUMASK)
250 #define TARGET_PROMOTE_QImode (x86_promote_QImode & CPUMASK)
251 #define TARGET_SINGLE_STRINGOP (x86_single_stringop & CPUMASK)
252 #define TARGET_QIMODE_MATH (x86_qimode_math & CPUMASK)
253 #define TARGET_HIMODE_MATH (x86_himode_math & CPUMASK)
254 #define TARGET_PROMOTE_QI_REGS (x86_promote_qi_regs & CPUMASK)
255 #define TARGET_PROMOTE_HI_REGS (x86_promote_hi_regs & CPUMASK)
256 #define TARGET_ADD_ESP_4 (x86_add_esp_4 & CPUMASK)
257 #define TARGET_ADD_ESP_8 (x86_add_esp_8 & CPUMASK)
258 #define TARGET_SUB_ESP_4 (x86_sub_esp_4 & CPUMASK)
259 #define TARGET_SUB_ESP_8 (x86_sub_esp_8 & CPUMASK)
260 #define TARGET_INTEGER_DFMODE_MOVES (x86_integer_DFmode_moves & CPUMASK)
261 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & CPUMASK)
262 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & CPUMASK)
263 #define TARGET_PROLOGUE_USING_MOVE (x86_prologue_using_move & CPUMASK)
264 #define TARGET_EPILOGUE_USING_MOVE (x86_epilogue_using_move & CPUMASK)
265 #define TARGET_DECOMPOSE_LEA (x86_decompose_lea & CPUMASK)
266 #define TARGET_PREFETCH_SSE (x86_prefetch_sse)
268 #define TARGET_STACK_PROBE (target_flags & MASK_STACK_PROBE)
270 #define TARGET_ALIGN_STRINGOPS (!(target_flags & MASK_NO_ALIGN_STROPS))
271 #define TARGET_INLINE_ALL_STRINGOPS (target_flags & MASK_INLINE_ALL_STROPS)
273 #define ASSEMBLER_DIALECT (ix86_asm_dialect)
275 #define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0)
276 #define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
277 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0)
278 #define TARGET_MIX_SSE_I387 ((ix86_fpmath & FPMATH_SSE) \
279 && (ix86_fpmath & FPMATH_387))
280 #define TARGET_MMX ((target_flags & MASK_MMX) != 0)
281 #define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0)
282 #define TARGET_3DNOW_A ((target_flags & MASK_3DNOW_A) != 0)
285 #define TARGET_RED_ZONE (!(target_flags & MASK_NO_RED_ZONE))
287 /* WARNING: Do not mark empty strings for translation, as calling
288 gettext on an empty string does NOT return an empty
292 #define TARGET_SWITCHES \
293 { { "80387", MASK_80387, N_("Use hardware fp") }, \
294 { "no-80387", -MASK_80387, N_("Do not use hardware fp") }, \
295 { "hard-float", MASK_80387, N_("Use hardware fp") }, \
296 { "soft-float", -MASK_80387, N_("Do not use hardware fp") }, \
297 { "no-soft-float", MASK_80387, N_("Use hardware fp") }, \
298 { "386", 0, "" /*Deprecated.*/}, \
299 { "486", 0, "" /*Deprecated.*/}, \
300 { "pentium", 0, "" /*Deprecated.*/}, \
301 { "pentiumpro", 0, "" /*Deprecated.*/}, \
302 { "intel-syntax", 0, "" /*Deprecated.*/}, \
303 { "no-intel-syntax", 0, "" /*Deprecated.*/}, \
305 N_("Alternate calling convention") }, \
306 { "no-rtd", -MASK_RTD, \
307 N_("Use normal calling convention") }, \
308 { "align-double", MASK_ALIGN_DOUBLE, \
309 N_("Align some doubles on dword boundary") }, \
310 { "no-align-double", -MASK_ALIGN_DOUBLE, \
311 N_("Align doubles on word boundary") }, \
312 { "svr3-shlib", MASK_SVR3_SHLIB, \
313 N_("Uninitialized locals in .bss") }, \
314 { "no-svr3-shlib", -MASK_SVR3_SHLIB, \
315 N_("Uninitialized locals in .data") }, \
316 { "ieee-fp", MASK_IEEE_FP, \
317 N_("Use IEEE math for fp comparisons") }, \
318 { "no-ieee-fp", -MASK_IEEE_FP, \
319 N_("Do not use IEEE math for fp comparisons") }, \
320 { "fp-ret-in-387", MASK_FLOAT_RETURNS, \
321 N_("Return values of functions in FPU registers") }, \
322 { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS , \
323 N_("Do not return values of functions in FPU registers")}, \
324 { "no-fancy-math-387", MASK_NO_FANCY_MATH_387, \
325 N_("Do not generate sin, cos, sqrt for FPU") }, \
326 { "fancy-math-387", -MASK_NO_FANCY_MATH_387, \
327 N_("Generate sin, cos, sqrt for FPU")}, \
328 { "omit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER, \
329 N_("Omit the frame pointer in leaf functions") }, \
330 { "no-omit-leaf-frame-pointer",-MASK_OMIT_LEAF_FRAME_POINTER, "" }, \
331 { "stack-arg-probe", MASK_STACK_PROBE, \
332 N_("Enable stack probing") }, \
333 { "no-stack-arg-probe", -MASK_STACK_PROBE, "" }, \
334 { "windows", 0, 0 /* undocumented */ }, \
335 { "dll", 0, 0 /* undocumented */ }, \
336 { "align-stringops", -MASK_NO_ALIGN_STROPS, \
337 N_("Align destination of the string operations") }, \
338 { "no-align-stringops", MASK_NO_ALIGN_STROPS, \
339 N_("Do not align destination of the string operations") }, \
340 { "inline-all-stringops", MASK_INLINE_ALL_STROPS, \
341 N_("Inline all known string operations") }, \
342 { "no-inline-all-stringops", -MASK_INLINE_ALL_STROPS, \
343 N_("Do not inline all known string operations") }, \
344 { "push-args", -MASK_NO_PUSH_ARGS, \
345 N_("Use push instructions to save outgoing arguments") }, \
346 { "no-push-args", MASK_NO_PUSH_ARGS, \
347 N_("Do not use push instructions to save outgoing arguments") }, \
348 { "accumulate-outgoing-args", (MASK_ACCUMULATE_OUTGOING_ARGS \
349 | MASK_ACCUMULATE_OUTGOING_ARGS_SET), \
350 N_("Use push instructions to save outgoing arguments") }, \
351 { "no-accumulate-outgoing-args",MASK_ACCUMULATE_OUTGOING_ARGS_SET, \
352 N_("Do not use push instructions to save outgoing arguments") }, \
353 { "mmx", MASK_MMX | MASK_MMX_SET, \
354 N_("Support MMX built-in functions") }, \
355 { "no-mmx", -MASK_MMX, \
356 N_("Do not support MMX built-in functions") }, \
357 { "no-mmx", MASK_MMX_SET, "" }, \
358 { "3dnow", MASK_3DNOW | MASK_3DNOW_SET, \
359 N_("Support 3DNow! built-in functions") }, \
360 { "no-3dnow", -MASK_3DNOW, "" }, \
361 { "no-3dnow", MASK_3DNOW_SET, \
362 N_("Do not support 3DNow! built-in functions") }, \
363 { "sse", MASK_SSE | MASK_SSE_SET, \
364 N_("Support MMX and SSE built-in functions and code generation") }, \
365 { "no-sse", -MASK_SSE, "" }, \
366 { "no-sse", MASK_SSE_SET, \
367 N_("Do not support MMX and SSE built-in functions and code generation") },\
368 { "sse2", MASK_SSE2 | MASK_SSE2_SET, \
369 N_("Support MMX, SSE and SSE2 built-in functions and code generation") }, \
370 { "no-sse2", -MASK_SSE2, "" }, \
371 { "no-sse2", MASK_SSE2_SET, \
372 N_("Do not support MMX, SSE and SSE2 built-in functions and code generation") }, \
373 { "128bit-long-double", MASK_128BIT_LONG_DOUBLE, \
374 N_("sizeof(long double) is 16") }, \
375 { "96bit-long-double", -MASK_128BIT_LONG_DOUBLE, \
376 N_("sizeof(long double) is 12") }, \
377 { "64", MASK_64BIT, \
378 N_("Generate 64bit x86-64 code") }, \
379 { "32", -MASK_64BIT, \
380 N_("Generate 32bit i386 code") }, \
381 { "red-zone", -MASK_NO_RED_ZONE, \
382 N_("Use red-zone in the x86-64 code") }, \
383 { "no-red-zone", MASK_NO_RED_ZONE, \
384 N_("Do not use red-zone in the x86-64 code") }, \
386 { "", TARGET_DEFAULT, 0 }}
388 #ifdef TARGET_64BIT_DEFAULT
389 #define TARGET_DEFAULT (MASK_64BIT | TARGET_SUBTARGET_DEFAULT)
391 #define TARGET_DEFAULT TARGET_SUBTARGET_DEFAULT
394 /* Which processor to schedule for. The cpu attribute defines a list that
395 mirrors this list, so changes to i386.md must be made at the same time. */
399 PROCESSOR_I386
, /* 80386 */
400 PROCESSOR_I486
, /* 80486DX, 80486SX, 80486DX[24] */
402 PROCESSOR_PENTIUMPRO
,
414 extern enum processor_type ix86_cpu
;
415 extern enum fpmath_unit ix86_fpmath
;
417 extern int ix86_arch
;
419 /* This macro is similar to `TARGET_SWITCHES' but defines names of
420 command options that have values. Its definition is an
421 initializer with a subgrouping for each command option.
423 Each subgrouping contains a string constant, that defines the
424 fixed part of the option name, and the address of a variable. The
425 variable, type `char *', is set to the variable part of the given
426 option if the fixed part matches. The actual option name is made
427 by appending `-m' to the specified name. */
428 #define TARGET_OPTIONS \
429 { { "cpu=", &ix86_cpu_string, \
430 N_("Schedule code for given CPU")}, \
431 { "fpmath=", &ix86_fpmath_string, \
432 N_("Generate floating point mathematics using given instruction set")},\
433 { "arch=", &ix86_arch_string, \
434 N_("Generate code for given CPU")}, \
435 { "regparm=", &ix86_regparm_string, \
436 N_("Number of registers used to pass integer arguments") }, \
437 { "align-loops=", &ix86_align_loops_string, \
438 N_("Loop code aligned to this power of 2") }, \
439 { "align-jumps=", &ix86_align_jumps_string, \
440 N_("Jump targets are aligned to this power of 2") }, \
441 { "align-functions=", &ix86_align_funcs_string, \
442 N_("Function starts are aligned to this power of 2") }, \
443 { "preferred-stack-boundary=", \
444 &ix86_preferred_stack_boundary_string, \
445 N_("Attempt to keep stack aligned to this power of 2") }, \
446 { "branch-cost=", &ix86_branch_cost_string, \
447 N_("Branches are this expensive (1-5, arbitrary units)") }, \
448 { "cmodel=", &ix86_cmodel_string, \
449 N_("Use given x86-64 code model") }, \
450 { "debug-arg", &ix86_debug_arg_string, \
451 "" /* Undocumented. */ }, \
452 { "debug-addr", &ix86_debug_addr_string, \
453 "" /* Undocumented. */ }, \
454 { "asm=", &ix86_asm_string, \
455 N_("Use given assembler dialect") }, \
460 /* Sometimes certain combinations of command options do not make
461 sense on a particular target machine. You can define a macro
462 `OVERRIDE_OPTIONS' to take account of this. This macro, if
463 defined, is executed once just after all the command options have
466 Don't use this macro to turn on various extra optimizations for
467 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
469 #define OVERRIDE_OPTIONS override_options ()
471 /* These are meant to be redefined in the host dependent files */
472 #define SUBTARGET_SWITCHES
473 #define SUBTARGET_OPTIONS
475 /* Define this to change the optimizations performed by default. */
476 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \
477 optimization_options ((LEVEL), (SIZE))
479 /* Specs for the compiler proper */
483 #define CC1_CPU_SPEC "\
486 %n`-m386' is deprecated. Use `-march=i386' or `-mcpu=i386' instead.\n} \
488 %n`-m486' is deprecated. Use `-march=i486' or `-mcpu=i486' instead.\n} \
489 %{mpentium:-mcpu=pentium \
490 %n`-mpentium' is deprecated. Use `-march=pentium' or `-mcpu=pentium' instead.\n} \
491 %{mpentiumpro:-mcpu=pentiumpro \
492 %n`-mpentiumpro' is deprecated. Use `-march=pentiumpro' or `-mcpu=pentiumpro' instead.\n}} \
493 %{mintel-syntax:-masm=intel \
494 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
495 %{mno-intel-syntax:-masm=att \
496 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
499 #define TARGET_CPU_DEFAULT_i386 0
500 #define TARGET_CPU_DEFAULT_i486 1
501 #define TARGET_CPU_DEFAULT_pentium 2
502 #define TARGET_CPU_DEFAULT_pentium_mmx 3
503 #define TARGET_CPU_DEFAULT_pentiumpro 4
504 #define TARGET_CPU_DEFAULT_pentium2 5
505 #define TARGET_CPU_DEFAULT_pentium3 6
506 #define TARGET_CPU_DEFAULT_pentium4 7
507 #define TARGET_CPU_DEFAULT_k6 8
508 #define TARGET_CPU_DEFAULT_k6_2 9
509 #define TARGET_CPU_DEFAULT_k6_3 10
510 #define TARGET_CPU_DEFAULT_athlon 11
511 #define TARGET_CPU_DEFAULT_athlon_sse 12
513 #define TARGET_CPU_DEFAULT_NAMES {"i386", "i486", "pentium", "pentium-mmx",\
514 "pentiumpro", "pentium2", "pentium3", \
515 "pentium4", "k6", "k6-2", "k6-3",\
516 "athlon", "athlon-4"}
517 #ifndef CPP_CPU_DEFAULT_SPEC
518 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_i486
519 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i486__"
521 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium
522 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__"
524 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium_mmx
525 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__"
527 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentiumpro
528 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__"
530 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium2
531 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\
534 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium3
535 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i686__ -D__tune_pentiumpro__\
536 -D__tune_pentium2__ -D__tune_pentium3__"
538 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_pentium4
539 #define CPP_CPU_DEFAULT_SPEC "-D__tune_pentium4__"
541 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6
542 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__"
544 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_2
545 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_2__"
547 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_k6_3
548 #define CPP_CPU_DEFAULT_SPEC "-D__tune_k6__ -D__tune_k6_3__"
550 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon
551 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__"
553 #if TARGET_CPU_DEFAULT == TARGET_CPU_DEFAULT_athlon_sse
554 #define CPP_CPU_DEFAULT_SPEC "-D__tune_athlon__ -D__tune_athlon_sse__"
556 #ifndef CPP_CPU_DEFAULT_SPEC
557 #define CPP_CPU_DEFAULT_SPEC "-D__tune_i386__"
559 #endif /* CPP_CPU_DEFAULT_SPEC */
561 #ifdef TARGET_BI_ARCH
562 #define NO_BUILTIN_SIZE_TYPE
563 #define NO_BUILTIN_PTRDIFF_TYPE
566 #ifdef NO_BUILTIN_SIZE_TYPE
567 #define CPP_CPU32_SIZE_TYPE_SPEC \
568 " -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int"
569 #define CPP_CPU64_SIZE_TYPE_SPEC \
570 " -D__SIZE_TYPE__=unsigned\\ long\\ int -D__PTRDIFF_TYPE__=long\\ int"
572 #define CPP_CPU32_SIZE_TYPE_SPEC ""
573 #define CPP_CPU64_SIZE_TYPE_SPEC ""
576 #define CPP_CPU32_SPEC \
577 "-Acpu=i386 -Amachine=i386 %{!ansi:%{!std=c*:%{!std=i*:-Di386}}} -D__i386 \
578 -D__i386__ %(cpp_cpu32sizet)"
580 #define CPP_CPU64_SPEC \
581 "-Acpu=x86_64 -Amachine=x86_64 -D__x86_64 -D__x86_64__ %(cpp_cpu64sizet)"
583 #define CPP_CPUCOMMON_SPEC "\
584 %{march=i386:%{!mcpu*:-D__tune_i386__ }}\
585 %{march=i486:-D__i486 -D__i486__ %{!mcpu*:-D__tune_i486__ }}\
586 %{march=pentium|march=i586:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
587 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ }}\
588 %{march=pentium-mmx:-D__i586 -D__i586__ -D__pentium -D__pentium__ \
590 %{!mcpu*:-D__tune_i586__ -D__tune_pentium__ -D__tune_pentium_mmx__}}\
591 %{march=pentiumpro|march=i686:-D__i686 -D__i686__ \
592 -D__pentiumpro -D__pentiumpro__ \
593 %{!mcpu*:-D__tune_i686__ -D__tune_pentiumpro__ }}\
594 %{march=k6:-D__k6 -D__k6__ %{!mcpu*:-D__tune_k6__ }}\
595 %{march=k6-2:-D__k6 -D__k6__ -D__k6_2__ \
596 %{!mcpu*:-D__tune_k6__ -D__tune_k6_2__ }}\
597 %{march=k6-3:-D__k6 -D__k6__ -D__k6_3__ \
598 %{!mcpu*:-D__tune_k6__ -D__tune_k6_3__ }}\
599 %{march=athlon|march=athlon-tbird:-D__athlon -D__athlon__ \
600 %{!mcpu*:-D__tune_athlon__ }}\
601 %{march=athlon-4|march=athlon-xp|march=athlon-mp:-D__athlon -D__athlon__ \
603 %{!mcpu*:-D__tune_athlon__ -D__tune_athlon_sse__ }}\
604 %{march=pentium4:-D__pentium4 -D__pentium4__ %{!mcpu*:-D__tune_pentium4__ }}\
605 %{m386|mcpu=i386:-D__tune_i386__ }\
606 %{m486|mcpu=i486:-D__tune_i486__ }\
607 %{mpentium|mcpu=pentium|mcpu=i586|mcpu=pentium-mmx:-D__tune_i586__ -D__tune_pentium__ }\
608 %{mpentiumpro|mcpu=pentiumpro|mcpu=i686|cpu=pentium2|cpu=pentium3:-D__tune_i686__ \
609 -D__tune_pentiumpro__ }\
610 %{mcpu=k6|mcpu=k6-2|mcpu=k6-3:-D__tune_k6__ }\
611 %{mcpu=athlon|mcpu=athlon-tbird|mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\
613 %{mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\
614 -D__tune_athlon_sse__ }\
615 %{mcpu=pentium4:-D__tune_pentium4__ }\
616 %{march=athlon-tbird|march=athlon-xp|march=athlon-mp|march=pentium3|march=pentium4:\
618 %{march=pentium-mmx|march=k6|march=k6-2|march=k6-3\
619 |march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
620 |march=athlon-mp|march=pentium2|march=pentium3|march=pentium4: -D__MMX__ }\
621 %{march=k6-2|march=k6-3\
622 |march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
623 |march=athlon-mp: -D__3dNOW__ }\
624 %{march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
625 |march=athlon-mp: -D__3dNOW_A__ }\
626 %{march=pentium4: -D__SSE2__ }\
627 %{!march*:%{!mcpu*:%{!m386:%{!m486:%{!mpentium*:%(cpp_cpu_default)}}}}}"
630 #ifdef TARGET_BI_ARCH
631 #ifdef TARGET_64BIT_DEFAULT
632 #define CPP_CPU_SPEC "%{m32:%(cpp_cpu32)}%{!m32:%(cpp_cpu64)} %(cpp_cpucommon)"
634 #define CPP_CPU_SPEC "%{m64:%(cpp_cpu64)}%{!m64:%(cpp_cpu32)} %(cpp_cpucommon)"
637 #ifdef TARGET_64BIT_DEFAULT
638 #define CPP_CPU_SPEC "%(cpp_cpu64) %(cpp_cpucommon)"
640 #define CPP_CPU_SPEC "%(cpp_cpu32) %(cpp_cpucommon)"
646 #define CC1_SPEC "%(cc1_cpu) "
649 /* This macro defines names of additional specifications to put in the
650 specs that can be used in various specifications like CC1_SPEC. Its
651 definition is an initializer with a subgrouping for each command option.
653 Each subgrouping contains a string constant, that defines the
654 specification name, and a string constant that used by the GNU CC driver
657 Do not define this macro if it does not need to do anything. */
659 #ifndef SUBTARGET_EXTRA_SPECS
660 #define SUBTARGET_EXTRA_SPECS
663 #define EXTRA_SPECS \
664 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
665 { "cpp_cpu", CPP_CPU_SPEC }, \
666 { "cpp_cpu32", CPP_CPU32_SPEC }, \
667 { "cpp_cpu64", CPP_CPU64_SPEC }, \
668 { "cpp_cpu32sizet", CPP_CPU32_SIZE_TYPE_SPEC }, \
669 { "cpp_cpu64sizet", CPP_CPU64_SIZE_TYPE_SPEC }, \
670 { "cpp_cpucommon", CPP_CPUCOMMON_SPEC }, \
671 { "cc1_cpu", CC1_CPU_SPEC }, \
672 SUBTARGET_EXTRA_SPECS
675 /* target machine storage layout */
677 /* Define for XFmode or TFmode extended real floating point support.
678 This will automatically cause REAL_ARITHMETIC to be defined.
680 The XFmode is specified by i386 ABI, while TFmode may be faster
681 due to alignment and simplifications in the address calculations.
683 #define LONG_DOUBLE_TYPE_SIZE (TARGET_128BIT_LONG_DOUBLE ? 128 : 96)
684 #define MAX_LONG_DOUBLE_TYPE_SIZE 64
685 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
686 /* Tell real.c that this is the 80-bit Intel extended float format
687 packaged in a 128-bit or 96bit entity. */
688 #define INTEL_EXTENDED_IEEE_FORMAT 1
691 #define SHORT_TYPE_SIZE 16
692 #define INT_TYPE_SIZE 32
693 #define FLOAT_TYPE_SIZE 32
694 #define LONG_TYPE_SIZE BITS_PER_WORD
695 #define MAX_WCHAR_TYPE_SIZE 32
696 #define DOUBLE_TYPE_SIZE 64
697 #define LONG_LONG_TYPE_SIZE 64
699 #if defined (TARGET_BI_ARCH) || defined (TARGET_64BIT_DEFAULT)
700 #define MAX_BITS_PER_WORD 64
701 #define MAX_LONG_TYPE_SIZE 64
703 #define MAX_BITS_PER_WORD 32
704 #define MAX_LONG_TYPE_SIZE 32
707 /* Define if you don't want extended real, but do want to use the
708 software floating point emulator for REAL_ARITHMETIC and
709 decimal <-> binary conversion. */
710 /* #define REAL_ARITHMETIC */
712 /* Define this if most significant byte of a word is the lowest numbered. */
713 /* That is true on the 80386. */
715 #define BITS_BIG_ENDIAN 0
717 /* Define this if most significant byte of a word is the lowest numbered. */
718 /* That is not true on the 80386. */
719 #define BYTES_BIG_ENDIAN 0
721 /* Define this if most significant word of a multiword number is the lowest
723 /* Not true for 80386 */
724 #define WORDS_BIG_ENDIAN 0
726 /* number of bits in an addressable storage unit */
727 #define BITS_PER_UNIT 8
729 /* Width in bits of a "word", which is the contents of a machine register.
730 Note that this is not necessarily the width of data type `int';
731 if using 16-bit ints on a 80386, this would still be 32.
732 But on a machine with 16-bit registers, this would be 16. */
733 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
735 /* Width of a word, in units (bytes). */
736 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
737 #define MIN_UNITS_PER_WORD 4
739 /* Width in bits of a pointer.
740 See also the macro `Pmode' defined below. */
741 #define POINTER_SIZE BITS_PER_WORD
743 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
744 #define PARM_BOUNDARY BITS_PER_WORD
746 /* Boundary (in *bits*) on which stack pointer should be aligned. */
747 #define STACK_BOUNDARY BITS_PER_WORD
749 /* Boundary (in *bits*) on which the stack pointer preferrs to be
750 aligned; the compiler cannot rely on having this alignment. */
751 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary
753 /* As of July 2001, many runtimes to not align the stack properly when
754 entering main. This causes expand_main_function to forcably align
755 the stack, which results in aligned frames for functions called from
756 main, though it does nothing for the alignment of main itself. */
757 #define FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN \
758 (ix86_preferred_stack_boundary > STACK_BOUNDARY && !TARGET_64BIT)
760 /* Allocation boundary for the code of a function. */
761 #define FUNCTION_BOUNDARY 16
763 /* Alignment of field after `int : 0' in a structure. */
765 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD
767 /* Minimum size in bits of the largest boundary to which any
768 and all fundamental data types supported by the hardware
769 might need to be aligned. No data type wants to be aligned
772 Pentium+ preferrs DFmode values to be aligned to 64 bit boundary
773 and Pentium Pro XFmode values at 128 bit boundaries. */
775 #define BIGGEST_ALIGNMENT 128
777 /* Decide whether a variable of mode MODE must be 128 bit aligned. */
778 #define ALIGN_MODE_128(MODE) \
779 ((MODE) == XFmode || (MODE) == TFmode || ((MODE) == TImode) \
780 || (MODE) == V4SFmode || (MODE) == V4SImode)
782 /* The published ABIs say that doubles should be aligned on word
783 boundaries, so lower the aligment for structure fields unless
784 -malign-double is set. */
785 /* BIGGEST_FIELD_ALIGNMENT is also used in libobjc, where it must be
786 constant. Use the smaller value in that context. */
787 #ifndef IN_TARGET_LIBS
788 #define BIGGEST_FIELD_ALIGNMENT (TARGET_64BIT ? 128 : (TARGET_ALIGN_DOUBLE ? 64 : 32))
790 #define BIGGEST_FIELD_ALIGNMENT 32
793 /* If defined, a C expression to compute the alignment given to a
794 constant that is being placed in memory. EXP is the constant
795 and ALIGN is the alignment that the object would ordinarily have.
796 The value of this macro is used instead of that alignment to align
799 If this macro is not defined, then ALIGN is used.
801 The typical use of this macro is to increase alignment for string
802 constants to be word aligned so that `strcpy' calls that copy
803 constants can be done inline. */
805 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))
807 /* If defined, a C expression to compute the alignment for a static
808 variable. TYPE is the data type, and ALIGN is the alignment that
809 the object would ordinarily have. The value of this macro is used
810 instead of that alignment to align the object.
812 If this macro is not defined, then ALIGN is used.
814 One use of this macro is to increase alignment of medium-size
815 data to make it all fit in fewer cache lines. Another is to
816 cause character arrays to be word-aligned so that `strcpy' calls
817 that copy constants to character arrays can be done inline. */
819 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))
821 /* If defined, a C expression to compute the alignment for a local
822 variable. TYPE is the data type, and ALIGN is the alignment that
823 the object would ordinarily have. The value of this macro is used
824 instead of that alignment to align the object.
826 If this macro is not defined, then ALIGN is used.
828 One use of this macro is to increase alignment of medium-size
829 data to make it all fit in fewer cache lines. */
831 #define LOCAL_ALIGNMENT(TYPE, ALIGN) ix86_local_alignment ((TYPE), (ALIGN))
833 /* If defined, a C expression that gives the alignment boundary, in
834 bits, of an argument with the specified mode and type. If it is
835 not defined, `PARM_BOUNDARY' is used for all arguments. */
837 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
838 ix86_function_arg_boundary ((MODE), (TYPE))
840 /* Set this non-zero if move instructions will actually fail to work
841 when given unaligned data. */
842 #define STRICT_ALIGNMENT 0
844 /* If bit field type is int, don't let it cross an int,
845 and give entire struct the alignment of an int. */
846 /* Required on the 386 since it doesn't have bitfield insns. */
847 #define PCC_BITFIELD_TYPE_MATTERS 1
849 /* Standard register usage. */
851 /* This processor has special stack-like registers. See reg-stack.c
855 #define IS_STACK_MODE(MODE) \
856 ((MODE) == DFmode || (MODE) == SFmode || (MODE) == XFmode \
859 /* Number of actual hardware registers.
860 The hardware registers are assigned numbers for the compiler
861 from 0 to just below FIRST_PSEUDO_REGISTER.
862 All registers that the compiler knows about must be given numbers,
863 even those that are not normally considered general registers.
865 In the 80386 we give the 8 general purpose registers the numbers 0-7.
866 We number the floating point registers 8-15.
867 Note that registers 0-7 can be accessed as a short or int,
868 while only 0-3 may be used with byte `mov' instructions.
870 Reg 16 does not correspond to any hardware register, but instead
871 appears in the RTL as an argument pointer prior to reload, and is
872 eliminated during reloading in favor of either the stack or frame
875 #define FIRST_PSEUDO_REGISTER 53
877 /* Number of hardware registers that go into the DWARF-2 unwind info.
878 If not defined, equals FIRST_PSEUDO_REGISTER. */
880 #define DWARF_FRAME_REGISTERS 17
882 /* 1 for registers that have pervasive standard uses
883 and are not available for the register allocator.
884 On the 80386, the stack pointer is such, as is the arg pointer.
886 The value is an mask - bit 1 is set for fixed registers
887 for 32bit target, while 2 is set for fixed registers for 64bit.
888 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
890 #define FIXED_REGISTERS \
891 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
892 { 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, \
893 /*arg,flags,fpsr,dir,frame*/ \
895 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
896 0, 0, 0, 0, 0, 0, 0, 0, \
897 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
898 0, 0, 0, 0, 0, 0, 0, 0, \
899 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
900 1, 1, 1, 1, 1, 1, 1, 1, \
901 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
902 1, 1, 1, 1, 1, 1, 1, 1}
905 /* 1 for registers not available across function calls.
906 These must include the FIXED_REGISTERS and also any
907 registers that can be used without being saved.
908 The latter must include the registers where values are returned
909 and the register where structure-value addresses are passed.
910 Aside from that, you can include as many other registers as you like.
912 The value is an mask - bit 1 is set for call used
913 for 32bit target, while 2 is set for call used for 64bit.
914 Proper value is computed in the CONDITIONAL_REGISTER_USAGE.
916 #define CALL_USED_REGISTERS \
917 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \
918 { 3, 3, 3, 0, 2, 2, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, \
919 /*arg,flags,fpsr,dir,frame*/ \
921 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \
922 3, 3, 3, 3, 3, 3, 3, 3, \
923 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/ \
924 3, 3, 3, 3, 3, 3, 3, 3, \
925 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \
926 3, 3, 3, 3, 1, 1, 1, 1, \
927 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \
928 3, 3, 3, 3, 3, 3, 3, 3} \
930 /* Order in which to allocate registers. Each register must be
931 listed once, even those in FIXED_REGISTERS. List frame pointer
932 late and fixed registers last. Note that, in general, we prefer
933 registers listed in CALL_USED_REGISTERS, keeping the others
934 available for storage of persistent values.
936 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,
937 so this is just empty initializer for array. */
939 #define REG_ALLOC_ORDER \
940 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
941 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
942 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
945 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
946 to be rearranged based on a particular function. When using sse math,
947 we want to allocase SSE before x87 registers and vice vera. */
949 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
952 /* Macro to conditionally modify fixed_regs/call_used_regs. */
953 #define CONDITIONAL_REGISTER_USAGE \
956 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
958 fixed_regs[i] = (fixed_regs[i] & (TARGET_64BIT ? 2 : 1)) != 0; \
959 call_used_regs[i] = (call_used_regs[i] \
960 & (TARGET_64BIT ? 2 : 1)) != 0; \
962 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
964 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
965 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
970 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
971 if (TEST_HARD_REG_BIT (reg_class_contents[(int)MMX_REGS], i)) \
972 fixed_regs[i] = call_used_regs[i] = 1; \
977 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
978 if (TEST_HARD_REG_BIT (reg_class_contents[(int)SSE_REGS], i)) \
979 fixed_regs[i] = call_used_regs[i] = 1; \
981 if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \
985 COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \
986 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
987 if (TEST_HARD_REG_BIT (x, i)) \
988 fixed_regs[i] = call_used_regs[i] = 1; \
992 /* Return number of consecutive hard regs needed starting at reg REGNO
993 to hold something of mode MODE.
994 This is ordinarily the length in words of a value of mode MODE
995 but can be less for certain modes in special long registers.
997 Actually there are no two word move instructions for consecutive
998 registers. And only registers 0-3 may have mov byte instructions
1002 #define HARD_REGNO_NREGS(REGNO, MODE) \
1003 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \
1004 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1005 : ((MODE) == TFmode \
1006 ? (TARGET_64BIT ? 2 : 3) \
1007 : (MODE) == TCmode \
1008 ? (TARGET_64BIT ? 4 : 6) \
1009 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
1011 #define VALID_SSE_REG_MODE(MODE) \
1012 ((MODE) == TImode || (MODE) == V4SFmode || (MODE) == V4SImode \
1013 || (MODE) == SFmode \
1014 || (TARGET_SSE2 && ((MODE) == DFmode || VALID_MMX_REG_MODE (MODE))))
1016 #define VALID_MMX_REG_MODE_3DNOW(MODE) \
1017 ((MODE) == V2SFmode || (MODE) == SFmode)
1019 #define VALID_MMX_REG_MODE(MODE) \
1020 ((MODE) == DImode || (MODE) == V8QImode || (MODE) == V4HImode \
1021 || (MODE) == V2SImode || (MODE) == SImode)
1023 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1024 (VALID_SSE_REG_MODE (MODE) && TARGET_SSE ? 1 \
1025 : VALID_MMX_REG_MODE (MODE) && TARGET_MMX ? 1 \
1026 : VALID_MMX_REG_MODE_3DNOW (MODE) && TARGET_3DNOW ? 1 : 0)
1028 #define VALID_FP_MODE_P(MODE) \
1029 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
1030 || (!TARGET_64BIT && (MODE) == XFmode) \
1031 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == TCmode \
1032 || (!TARGET_64BIT && (MODE) == XCmode))
1034 #define VALID_INT_MODE_P(MODE) \
1035 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
1036 || (MODE) == DImode \
1037 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \
1038 || (MODE) == CDImode \
1039 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode)))
1041 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
1043 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1044 ix86_hard_regno_mode_ok ((REGNO), (MODE))
1046 /* Value is 1 if it is a good idea to tie two pseudo registers
1047 when one has mode MODE1 and one has mode MODE2.
1048 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1049 for any hard reg, then this must be 0 for correct output. */
1051 #define MODES_TIEABLE_P(MODE1, MODE2) \
1052 ((MODE1) == (MODE2) \
1053 || (((MODE1) == HImode || (MODE1) == SImode \
1054 || ((MODE1) == QImode \
1055 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1056 || ((MODE1) == DImode && TARGET_64BIT)) \
1057 && ((MODE2) == HImode || (MODE2) == SImode \
1058 || ((MODE1) == QImode \
1059 && (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
1060 || ((MODE2) == DImode && TARGET_64BIT))))
1063 /* Specify the modes required to caller save a given hard regno.
1064 We do this on i386 to prevent flags from being saved at all.
1066 Kill any attempts to combine saving of modes. */
1068 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1069 (CC_REGNO_P (REGNO) ? VOIDmode \
1070 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
1071 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \
1072 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
1073 : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
1075 /* Specify the registers used for certain standard purposes.
1076 The values of these macros are register numbers. */
1078 /* on the 386 the pc register is %eip, and is not usable as a general
1079 register. The ordinary mov instructions won't work */
1080 /* #define PC_REGNUM */
1082 /* Register to use for pushing function arguments. */
1083 #define STACK_POINTER_REGNUM 7
1085 /* Base register for access to local variables of the function. */
1086 #define HARD_FRAME_POINTER_REGNUM 6
1088 /* Base register for access to local variables of the function. */
1089 #define FRAME_POINTER_REGNUM 20
1091 /* First floating point reg */
1092 #define FIRST_FLOAT_REG 8
1094 /* First & last stack-like regs */
1095 #define FIRST_STACK_REG FIRST_FLOAT_REG
1096 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7)
1098 #define FLAGS_REG 17
1100 #define DIRFLAG_REG 19
1102 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)
1103 #define LAST_SSE_REG (FIRST_SSE_REG + 7)
1105 #define FIRST_MMX_REG (LAST_SSE_REG + 1)
1106 #define LAST_MMX_REG (FIRST_MMX_REG + 7)
1108 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1)
1109 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7)
1111 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1)
1112 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7)
1114 /* Value should be nonzero if functions must have frame pointers.
1115 Zero means the frame pointer need not be set up (and parms
1116 may be accessed via the stack pointer) in functions that seem suitable.
1117 This is computed in `reload', in reload1.c. */
1118 #define FRAME_POINTER_REQUIRED ix86_frame_pointer_required ()
1120 /* Override this in other tm.h files to cope with various OS losage
1121 requiring a frame pointer. */
1122 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
1123 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
1126 /* Make sure we can access arbitrary call frames. */
1127 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses ()
1129 /* Base register for access to arguments of the function. */
1130 #define ARG_POINTER_REGNUM 16
1132 /* Register in which static-chain is passed to a function.
1133 We do use ECX as static chain register for 32 bit ABI. On the
1134 64bit ABI, ECX is an argument register, so we use R10 instead. */
1135 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
1137 /* Register to hold the addressing base for position independent
1138 code access to data items. We don't use PIC pointer for 64bit
1139 mode. Define the regnum to dummy value to prevent gcc from
1140 pessimizing code dealing with EBX. */
1141 #define PIC_OFFSET_TABLE_REGNUM \
1142 (TARGET_64BIT || !flag_pic ? INVALID_REGNUM : 3)
1144 /* Register in which address to store a structure value
1145 arrives in the function. On the 386, the prologue
1146 copies this from the stack to register %eax. */
1147 #define STRUCT_VALUE_INCOMING 0
1149 /* Place in which caller passes the structure value address.
1150 0 means push the value on the stack like an argument. */
1151 #define STRUCT_VALUE 0
1153 /* A C expression which can inhibit the returning of certain function
1154 values in registers, based on the type of value. A nonzero value
1155 says to return the function value in memory, just as large
1156 structures are always returned. Here TYPE will be a C expression
1157 of type `tree', representing the data type of the value.
1159 Note that values of mode `BLKmode' must be explicitly handled by
1160 this macro. Also, the option `-fpcc-struct-return' takes effect
1161 regardless of this macro. On most systems, it is possible to
1162 leave the macro undefined; this causes a default definition to be
1163 used, whose value is the constant 1 for `BLKmode' values, and 0
1166 Do not use this macro to indicate that structures and unions
1167 should always be returned in memory. You should instead use
1168 `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */
1170 #define RETURN_IN_MEMORY(TYPE) \
1171 ix86_return_in_memory (TYPE)
1174 /* Define the classes of registers for register constraints in the
1175 machine description. Also define ranges of constants.
1177 One of the classes must always be named ALL_REGS and include all hard regs.
1178 If there is more than one class, another class must be named NO_REGS
1179 and contain no registers.
1181 The name GENERAL_REGS must be the name of a class (or an alias for
1182 another name such as ALL_REGS). This is the class of registers
1183 that is allowed by "g" or "r" in a register constraint.
1184 Also, registers outside this class are allocated only when
1185 instructions express preferences for them.
1187 The classes must be numbered in nondecreasing order; that is,
1188 a larger-numbered class must never be contained completely
1189 in a smaller-numbered class.
1191 For any two classes, it is very desirable that there be another
1192 class that represents their union.
1194 It might seem that class BREG is unnecessary, since no useful 386
1195 opcode needs reg %ebx. But some systems pass args to the OS in ebx,
1196 and the "b" register constraint is useful in asms for syscalls.
1198 The flags and fpsr registers are in no class. */
1203 AREG
, DREG
, CREG
, BREG
, SIREG
, DIREG
,
1204 AD_REGS
, /* %eax/%edx for DImode */
1205 Q_REGS
, /* %eax %ebx %ecx %edx */
1206 NON_Q_REGS
, /* %esi %edi %ebp %esp */
1207 INDEX_REGS
, /* %eax %ebx %ecx %edx %esi %edi %ebp */
1208 LEGACY_REGS
, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */
1209 GENERAL_REGS
, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/
1210 FP_TOP_REG
, FP_SECOND_REG
, /* %st(0) %st(1) */
1220 ALL_REGS
, LIM_REG_CLASSES
1223 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
1225 #define INTEGER_CLASS_P(CLASS) \
1226 reg_class_subset_p ((CLASS), GENERAL_REGS)
1227 #define FLOAT_CLASS_P(CLASS) \
1228 reg_class_subset_p ((CLASS), FLOAT_REGS)
1229 #define SSE_CLASS_P(CLASS) \
1230 reg_class_subset_p ((CLASS), SSE_REGS)
1231 #define MMX_CLASS_P(CLASS) \
1232 reg_class_subset_p ((CLASS), MMX_REGS)
1233 #define MAYBE_INTEGER_CLASS_P(CLASS) \
1234 reg_classes_intersect_p ((CLASS), GENERAL_REGS)
1235 #define MAYBE_FLOAT_CLASS_P(CLASS) \
1236 reg_classes_intersect_p ((CLASS), FLOAT_REGS)
1237 #define MAYBE_SSE_CLASS_P(CLASS) \
1238 reg_classes_intersect_p (SSE_REGS, (CLASS))
1239 #define MAYBE_MMX_CLASS_P(CLASS) \
1240 reg_classes_intersect_p (MMX_REGS, (CLASS))
1242 #define Q_CLASS_P(CLASS) \
1243 reg_class_subset_p ((CLASS), Q_REGS)
1245 /* Give names of register classes as strings for dump file. */
1247 #define REG_CLASS_NAMES \
1249 "AREG", "DREG", "CREG", "BREG", \
1252 "Q_REGS", "NON_Q_REGS", \
1256 "FP_TOP_REG", "FP_SECOND_REG", \
1260 "FP_TOP_SSE_REGS", \
1261 "FP_SECOND_SSE_REGS", \
1265 "FLOAT_INT_SSE_REGS", \
1268 /* Define which registers fit in which classes.
1269 This is an initializer for a vector of HARD_REG_SET
1270 of length N_REG_CLASSES. */
1272 #define REG_CLASS_CONTENTS \
1274 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \
1275 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \
1276 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \
1277 { 0x03, 0x0 }, /* AD_REGS */ \
1278 { 0x0f, 0x0 }, /* Q_REGS */ \
1279 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \
1280 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \
1281 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \
1282 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \
1283 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
1284 { 0xff00, 0x0 }, /* FLOAT_REGS */ \
1285 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \
1286 { 0xe0000000, 0x1f }, /* MMX_REGS */ \
1287 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \
1288 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \
1289 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \
1290 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \
1291 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \
1292 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \
1293 { 0xffffffff,0x1fffff } \
1296 /* The same information, inverted:
1297 Return the class number of the smallest class containing
1298 reg number REGNO. This could be a conditional expression
1299 or could index an array. */
1301 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO])
1303 /* When defined, the compiler allows registers explicitly used in the
1304 rtl to be used as spill registers but prevents the compiler from
1305 extending the lifetime of these registers. */
1307 #define SMALL_REGISTER_CLASSES 1
1309 #define QI_REG_P(X) \
1310 (REG_P (X) && REGNO (X) < 4)
1312 #define GENERAL_REGNO_P(N) \
1313 ((N) < 8 || REX_INT_REGNO_P (N))
1315 #define GENERAL_REG_P(X) \
1316 (REG_P (X) && GENERAL_REGNO_P (REGNO (X)))
1318 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X))
1320 #define NON_QI_REG_P(X) \
1321 (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER)
1323 #define REX_INT_REGNO_P(N) ((N) >= FIRST_REX_INT_REG && (N) <= LAST_REX_INT_REG)
1324 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X)))
1326 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
1327 #define FP_REGNO_P(N) ((N) >= FIRST_STACK_REG && (N) <= LAST_STACK_REG)
1328 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X)))
1329 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N))
1331 #define SSE_REGNO_P(N) \
1332 (((N) >= FIRST_SSE_REG && (N) <= LAST_SSE_REG) \
1333 || ((N) >= FIRST_REX_SSE_REG && (N) <= LAST_REX_SSE_REG))
1335 #define SSE_REGNO(N) \
1336 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8)
1337 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N)))
1339 #define SSE_FLOAT_MODE_P(MODE) \
1340 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
1342 #define MMX_REGNO_P(N) ((N) >= FIRST_MMX_REG && (N) <= LAST_MMX_REG)
1343 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
1345 #define STACK_REG_P(XOP) \
1347 REGNO (XOP) >= FIRST_STACK_REG && \
1348 REGNO (XOP) <= LAST_STACK_REG)
1350 #define NON_STACK_REG_P(XOP) (REG_P (XOP) && ! STACK_REG_P (XOP))
1352 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG)
1354 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
1355 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG)
1357 /* Indicate whether hard register numbered REG_NO should be converted
1359 #define CONVERT_HARD_REGISTER_TO_SSA_P(REG_NO) \
1360 ((REG_NO) == FLAGS_REG || (REG_NO) == ARG_POINTER_REGNUM)
1362 /* The class value for index registers, and the one for base regs. */
1364 #define INDEX_REG_CLASS INDEX_REGS
1365 #define BASE_REG_CLASS GENERAL_REGS
1367 /* Get reg_class from a letter such as appears in the machine description. */
1369 #define REG_CLASS_FROM_LETTER(C) \
1370 ((C) == 'r' ? GENERAL_REGS : \
1371 (C) == 'R' ? LEGACY_REGS : \
1372 (C) == 'q' ? TARGET_64BIT ? GENERAL_REGS : Q_REGS : \
1373 (C) == 'Q' ? Q_REGS : \
1374 (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1377 (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1380 (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \
1383 (C) == 'a' ? AREG : \
1384 (C) == 'b' ? BREG : \
1385 (C) == 'c' ? CREG : \
1386 (C) == 'd' ? DREG : \
1387 (C) == 'x' ? TARGET_SSE ? SSE_REGS : NO_REGS : \
1388 (C) == 'Y' ? TARGET_SSE2? SSE_REGS : NO_REGS : \
1389 (C) == 'y' ? TARGET_MMX ? MMX_REGS : NO_REGS : \
1390 (C) == 'A' ? AD_REGS : \
1391 (C) == 'D' ? DIREG : \
1392 (C) == 'S' ? SIREG : NO_REGS)
1394 /* The letters I, J, K, L and M in a register constraint string
1395 can be used to stand for particular ranges of immediate operands.
1396 This macro defines what the ranges are.
1397 C is the letter, and VALUE is a constant value.
1398 Return 1 if VALUE is in the range specified by C.
1400 I is for non-DImode shifts.
1401 J is for DImode shifts.
1402 K is for signed imm8 operands.
1403 L is for andsi as zero-extending move.
1404 M is for shifts that can be executed by the "lea" opcode.
1405 N is for immedaite operands for out/in instructions (0-255)
1408 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1409 ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 \
1410 : (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 \
1411 : (C) == 'K' ? (VALUE) >= -128 && (VALUE) <= 127 \
1412 : (C) == 'L' ? (VALUE) == 0xff || (VALUE) == 0xffff \
1413 : (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 \
1414 : (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 \
1417 /* Similar, but for floating constants, and defining letters G and H.
1418 Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if
1419 TARGET_387 isn't set, because the stack register converter may need to
1420 load 0.0 into the function value register. */
1422 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1423 ((C) == 'G' ? standard_80387_constant_p (VALUE) \
1424 : ((C) == 'H' ? standard_sse_constant_p (VALUE) : 0))
1426 /* A C expression that defines the optional machine-dependent
1427 constraint letters that can be used to segregate specific types of
1428 operands, usually memory references, for the target machine. Any
1429 letter that is not elsewhere defined and not matched by
1430 `REG_CLASS_FROM_LETTER' may be used. Normally this macro will not
1433 If it is required for a particular target machine, it should
1434 return 1 if VALUE corresponds to the operand type represented by
1435 the constraint letter C. If C is not defined as an extra
1436 constraint, the value returned should be 0 regardless of VALUE. */
1438 #define EXTRA_CONSTRAINT(VALUE, C) \
1439 ((C) == 'e' ? x86_64_sign_extended_value (VALUE) \
1440 : (C) == 'Z' ? x86_64_zero_extended_value (VALUE) \
1443 /* Place additional restrictions on the register class to use when it
1444 is necessary to be able to hold a value of mode MODE in a reload
1445 register for which class CLASS would ordinarily be used. */
1447 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
1448 ((MODE) == QImode && !TARGET_64BIT \
1449 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \
1450 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \
1453 /* Given an rtx X being reloaded into a reg required to be
1454 in class CLASS, return the class of reg to actually use.
1455 In general this is just CLASS; but on some machines
1456 in some cases it is preferable to use a more restrictive class.
1457 On the 80386 series, we prevent floating constants from being
1458 reloaded into floating registers (since no move-insn can do that)
1459 and we ensure that QImodes aren't reloaded into the esi or edi reg. */
1461 /* Put float CONST_DOUBLE in the constant pool instead of fp regs.
1462 QImode must go into class Q_REGS.
1463 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
1464 movdf to do mem-to-mem moves through integer regs. */
1466 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1467 ix86_preferred_reload_class ((X), (CLASS))
1469 /* If we are copying between general and FP registers, we need a memory
1470 location. The same is true for SSE and MMX registers. */
1471 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1472 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1)
1474 /* QImode spills from non-QI registers need a scratch. This does not
1475 happen often -- the only example so far requires an uninitialized
1478 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \
1479 (((CLASS) == GENERAL_REGS || (CLASS) == LEGACY_REGS \
1480 || (CLASS) == INDEX_REGS) && !TARGET_64BIT && (MODE) == QImode \
1483 /* Return the maximum number of consecutive registers
1484 needed to represent mode MODE in a register of class CLASS. */
1485 /* On the 80386, this is the size of MODE in words,
1486 except in the FP regs, where a single reg is always enough.
1487 The TFmodes are really just 80bit values, so we use only 3 registers
1488 to hold them, instead of 4, as the size would suggest.
1490 #define CLASS_MAX_NREGS(CLASS, MODE) \
1491 (!MAYBE_INTEGER_CLASS_P (CLASS) \
1492 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \
1493 : ((GET_MODE_SIZE ((MODE) == TFmode ? XFmode : (MODE)) \
1494 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1496 /* A C expression whose value is nonzero if pseudos that have been
1497 assigned to registers of class CLASS would likely be spilled
1498 because registers of CLASS are needed for spill registers.
1500 The default value of this macro returns 1 if CLASS has exactly one
1501 register and zero otherwise. On most machines, this default
1502 should be used. Only define this macro to some other expression
1503 if pseudo allocated by `local-alloc.c' end up in memory because
1504 their hard registers were needed for spill registers. If this
1505 macro returns nonzero for those classes, those pseudos will only
1506 be allocated by `global.c', which knows how to reallocate the
1507 pseudo to another register. If there would not be another
1508 register available for reallocation, you should not change the
1509 definition of this macro since the only effect of such a
1510 definition would be to slow down register allocation. */
1512 #define CLASS_LIKELY_SPILLED_P(CLASS) \
1513 (((CLASS) == AREG) \
1514 || ((CLASS) == DREG) \
1515 || ((CLASS) == CREG) \
1516 || ((CLASS) == BREG) \
1517 || ((CLASS) == AD_REGS) \
1518 || ((CLASS) == SIREG) \
1519 || ((CLASS) == DIREG))
1521 /* A C statement that adds to CLOBBERS any hard regs the port wishes
1522 to automatically clobber for all asms.
1524 We do this in the new i386 backend to maintain source compatibility
1525 with the old cc0-based compiler. */
1527 #define MD_ASM_CLOBBERS(CLOBBERS) \
1529 (CLOBBERS) = tree_cons (NULL_TREE, build_string (5, "flags"), \
1531 (CLOBBERS) = tree_cons (NULL_TREE, build_string (4, "fpsr"), \
1533 (CLOBBERS) = tree_cons (NULL_TREE, build_string (7, "dirflag"), \
1537 /* Stack layout; function entry, exit and calling. */
1539 /* Define this if pushing a word on the stack
1540 makes the stack pointer a smaller address. */
1541 #define STACK_GROWS_DOWNWARD
1543 /* Define this if the nominal address of the stack frame
1544 is at the high-address end of the local variables;
1545 that is, each additional local variable allocated
1546 goes at a more negative offset in the frame. */
1547 #define FRAME_GROWS_DOWNWARD
1549 /* Offset within stack frame to start allocating local variables at.
1550 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1551 first local allocated. Otherwise, it is the offset to the BEGINNING
1552 of the first local allocated. */
1553 #define STARTING_FRAME_OFFSET 0
1555 /* If we generate an insn to push BYTES bytes,
1556 this says how many the stack pointer really advances by.
1557 On 386 pushw decrements by exactly 2 no matter what the position was.
1558 On the 386 there is no pushb; we use pushw instead, and this
1559 has the effect of rounding up to 2.
1561 For 64bit ABI we round up to 8 bytes.
1564 #define PUSH_ROUNDING(BYTES) \
1566 ? (((BYTES) + 7) & (-8)) \
1567 : (((BYTES) + 1) & (-2)))
1569 /* If defined, the maximum amount of space required for outgoing arguments will
1570 be computed and placed into the variable
1571 `current_function_outgoing_args_size'. No space will be pushed onto the
1572 stack for each call; instead, the function prologue should increase the stack
1573 frame size by this amount. */
1575 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
1577 /* If defined, a C expression whose value is nonzero when we want to use PUSH
1578 instructions to pass outgoing arguments. */
1580 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS)
1582 /* Offset of first parameter from the argument pointer register value. */
1583 #define FIRST_PARM_OFFSET(FNDECL) 0
1585 /* Define this macro if functions should assume that stack space has been
1586 allocated for arguments even when their values are passed in registers.
1588 The value of this macro is the size, in bytes, of the area reserved for
1589 arguments passed in registers for the function represented by FNDECL.
1591 This space can be allocated by the caller, or be a part of the
1592 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says
1594 #define REG_PARM_STACK_SPACE(FNDECL) 0
1596 /* Define as a C expression that evaluates to nonzero if we do not know how
1597 to pass TYPE solely in registers. The file expr.h defines a
1598 definition that is usually appropriate, refer to expr.h for additional
1599 documentation. If `REG_PARM_STACK_SPACE' is defined, the argument will be
1600 computed in the stack and then loaded into a register. */
1601 #define MUST_PASS_IN_STACK(MODE, TYPE) \
1603 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1604 || TREE_ADDRESSABLE (TYPE) \
1605 || ((MODE) == TImode) \
1606 || ((MODE) == BLKmode \
1608 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
1609 && 0 == (int_size_in_bytes (TYPE) \
1610 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
1611 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
1612 == (BYTES_BIG_ENDIAN ? upward : downward)))))
1614 /* Value is the number of bytes of arguments automatically
1615 popped when returning from a subroutine call.
1616 FUNDECL is the declaration node of the function (as a tree),
1617 FUNTYPE is the data type of the function (as a tree),
1618 or for a library call it is an identifier node for the subroutine name.
1619 SIZE is the number of bytes of arguments passed on the stack.
1621 On the 80386, the RTD insn may be used to pop them if the number
1622 of args is fixed, but if the number is variable then the caller
1623 must pop them all. RTD can't be used for library calls now
1624 because the library is compiled with the Unix compiler.
1625 Use of RTD is a selectable option, since it is incompatible with
1626 standard Unix calling sequences. If the option is not selected,
1627 the caller must always pop the args.
1629 The attribute NTAPI is equivalent to RTD on a per module basis. */
1631 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \
1632 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
1634 /* Define how to find the value returned by a function.
1635 VALTYPE is the data type of the value (as a tree).
1636 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1637 otherwise, FUNC is 0. */
1638 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1639 ix86_function_value (VALTYPE)
1641 #define FUNCTION_VALUE_REGNO_P(N) \
1642 ix86_function_value_regno_p (N)
1644 /* Define how to find the value returned by a library function
1645 assuming the value has mode MODE. */
1647 #define LIBCALL_VALUE(MODE) \
1648 ix86_libcall_value (MODE)
1650 /* Define the size of the result block used for communication between
1651 untyped_call and untyped_return. The block contains a DImode value
1652 followed by the block used by fnsave and frstor. */
1654 #define APPLY_RESULT_SIZE (8+108)
1656 /* 1 if N is a possible register number for function argument passing. */
1657 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N)
1659 /* Define a data type for recording info about an argument list
1660 during the scan of that argument list. This data type should
1661 hold all necessary information about the function itself
1662 and about the args processed so far, enough to enable macros
1663 such as FUNCTION_ARG to determine where the next arg should go. */
1665 typedef struct ix86_args
{
1666 int words
; /* # words passed so far */
1667 int nregs
; /* # registers available for passing */
1668 int regno
; /* next available register number */
1669 int sse_words
; /* # sse words passed so far */
1670 int sse_nregs
; /* # sse registers available for passing */
1671 int sse_regno
; /* next available sse register number */
1672 int maybe_vaarg
; /* true for calls to possibly vardic fncts. */
1675 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1676 for a call to a function whose data type is FNTYPE.
1677 For a library call, FNTYPE is 0. */
1679 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1680 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME))
1682 /* Update the data in CUM to advance over an argument
1683 of mode MODE and data type TYPE.
1684 (TYPE is null for libcalls where that information may not be available.) */
1686 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1687 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1689 /* Define where to put the arguments to a function.
1690 Value is zero to push the argument on the stack,
1691 or a hard register in which to store the argument.
1693 MODE is the argument's machine mode.
1694 TYPE is the data type of the argument (as a tree).
1695 This is null for libcalls where that information may
1697 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1698 the preceding args and about the function being called.
1699 NAMED is nonzero if this argument is a named parameter
1700 (otherwise it is an extra parameter matching an ellipsis). */
1702 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1703 function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1705 /* For an arg passed partly in registers and partly in memory,
1706 this is the number of registers used.
1707 For args passed entirely in registers or entirely in memory, zero. */
1709 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1711 /* If PIC, we cannot make sibling calls to global functions
1712 because the PLT requires %ebx live.
1713 If we are returning floats on the register stack, we cannot make
1714 sibling calls to functions that return floats. (The stack adjust
1715 instruction will wind up after the sibcall jump, and not be executed.) */
1716 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1718 && (! flag_pic || ! TREE_PUBLIC (DECL)) \
1719 && (! TARGET_FLOAT_RETURNS_IN_80387 \
1720 || ! FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (DECL)))) \
1721 || FLOAT_MODE_P (TYPE_MODE (TREE_TYPE (TREE_TYPE (cfun->decl))))))
1723 /* Perform any needed actions needed for a function that is receiving a
1724 variable number of arguments.
1728 MODE and TYPE are the mode and type of the current parameter.
1730 PRETEND_SIZE is a variable that should be set to the amount of stack
1731 that must be pushed by the prolog to pretend that our caller pushed
1734 Normally, this macro will push all remaining incoming registers on the
1735 stack and set PRETEND_SIZE to the length of the registers pushed. */
1737 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1738 ix86_setup_incoming_varargs (&(CUM), (MODE), (TYPE), &(PRETEND_SIZE), \
1741 /* Define the `__builtin_va_list' type for the ABI. */
1742 #define BUILD_VA_LIST_TYPE(VALIST) \
1743 ((VALIST) = ix86_build_va_list ())
1745 /* Implement `va_start' for varargs and stdarg. */
1746 #define EXPAND_BUILTIN_VA_START(STDARG, VALIST, NEXTARG) \
1747 ix86_va_start ((STDARG), (VALIST), (NEXTARG))
1749 /* Implement `va_arg'. */
1750 #define EXPAND_BUILTIN_VA_ARG(VALIST, TYPE) \
1751 ix86_va_arg ((VALIST), (TYPE))
1753 /* This macro is invoked at the end of compilation. It is used here to
1754 output code for -fpic that will load the return address into %ebx. */
1757 #define ASM_FILE_END(FILE) ix86_asm_file_end (FILE)
1759 /* Output assembler code to FILE to increment profiler label # LABELNO
1760 for profiling a function entry. */
1762 #define FUNCTION_PROFILER(FILE, LABELNO) \
1766 fprintf ((FILE), "\tleal\t%sP%d@GOTOFF(%%ebx),%%edx\n", \
1767 LPREFIX, (LABELNO)); \
1768 fprintf ((FILE), "\tcall\t*_mcount@GOT(%%ebx)\n"); \
1772 fprintf ((FILE), "\tmovl\t$%sP%d,%%edx\n", LPREFIX, (LABELNO)); \
1773 fprintf ((FILE), "\tcall\t_mcount\n"); \
1777 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1778 the stack pointer does not matter. The value is tested only in
1779 functions that have frame pointers.
1780 No definition is equivalent to always zero. */
1781 /* Note on the 386 it might be more efficient not to define this since
1782 we have to restore it ourselves from the frame pointer, in order to
1785 #define EXIT_IGNORE_STACK 1
1787 /* Output assembler code for a block containing the constant parts
1788 of a trampoline, leaving space for the variable parts. */
1790 /* On the 386, the trampoline contains two instructions:
1793 The trampoline is generated entirely at runtime. The operand of JMP
1794 is the address of FUNCTION relative to the instruction following the
1795 JMP (which is 5 bytes long). */
1797 /* Length in units of the trampoline for entering a nested function. */
1799 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 23 : 10)
1801 /* Emit RTL insns to initialize the variable parts of a trampoline.
1802 FNADDR is an RTX for the address of the function's pure code.
1803 CXT is an RTX for the static chain value for the function. */
1805 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1806 x86_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
1808 /* Definitions for register eliminations.
1810 This is an array of structures. Each structure initializes one pair
1811 of eliminable registers. The "from" register number is given first,
1812 followed by "to". Eliminations of the same "from" register are listed
1813 in order of preference.
1815 There are two registers that can always be eliminated on the i386.
1816 The frame pointer and the arg pointer can be replaced by either the
1817 hard frame pointer or to the stack pointer, depending upon the
1818 circumstances. The hard frame pointer is not used before reload and
1819 so it is not eligible for elimination. */
1821 #define ELIMINABLE_REGS \
1822 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1823 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1824 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1825 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
1827 /* Given FROM and TO register numbers, say whether this elimination is
1828 allowed. Frame pointer elimination is automatically handled.
1830 All other eliminations are valid. */
1832 #define CAN_ELIMINATE(FROM, TO) \
1833 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
1835 /* Define the offset between two registers, one to be eliminated, and the other
1836 its replacement, at the start of a routine. */
1838 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1839 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO)))
1841 /* Addressing modes, and classification of registers for them. */
1843 /* #define HAVE_POST_INCREMENT 0 */
1844 /* #define HAVE_POST_DECREMENT 0 */
1846 /* #define HAVE_PRE_DECREMENT 0 */
1847 /* #define HAVE_PRE_INCREMENT 0 */
1849 /* Macros to check register numbers against specific register classes. */
1851 /* These assume that REGNO is a hard or pseudo reg number.
1852 They give nonzero only if REGNO is a hard reg of the suitable class
1853 or a pseudo reg currently allocated to a suitable hard reg.
1854 Since they use reg_renumber, they are safe only once reg_renumber
1855 has been allocated, which happens in local-alloc.c. */
1857 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1858 ((REGNO) < STACK_POINTER_REGNUM \
1859 || (REGNO >= FIRST_REX_INT_REG \
1860 && (REGNO) <= LAST_REX_INT_REG) \
1861 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1862 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1863 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM)
1865 #define REGNO_OK_FOR_BASE_P(REGNO) \
1866 ((REGNO) <= STACK_POINTER_REGNUM \
1867 || (REGNO) == ARG_POINTER_REGNUM \
1868 || (REGNO) == FRAME_POINTER_REGNUM \
1869 || (REGNO >= FIRST_REX_INT_REG \
1870 && (REGNO) <= LAST_REX_INT_REG) \
1871 || ((unsigned) reg_renumber[(REGNO)] >= FIRST_REX_INT_REG \
1872 && (unsigned) reg_renumber[(REGNO)] <= LAST_REX_INT_REG) \
1873 || (unsigned) reg_renumber[(REGNO)] <= STACK_POINTER_REGNUM)
1875 #define REGNO_OK_FOR_SIREG_P(REGNO) \
1876 ((REGNO) == 4 || reg_renumber[(REGNO)] == 4)
1877 #define REGNO_OK_FOR_DIREG_P(REGNO) \
1878 ((REGNO) == 5 || reg_renumber[(REGNO)] == 5)
1880 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1881 and check its validity for a certain class.
1882 We have two alternate definitions for each of them.
1883 The usual definition accepts all pseudo regs; the other rejects
1884 them unless they have been allocated suitable hard regs.
1885 The symbol REG_OK_STRICT causes the latter definition to be used.
1887 Most source files want to accept pseudo regs in the hope that
1888 they will get allocated to the class that the insn wants them to be in.
1889 Source files for reload pass need to be strict.
1890 After reload, it makes no difference, since pseudo regs have
1891 been eliminated by then. */
1894 /* Non strict versions, pseudos are ok */
1895 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \
1896 (REGNO (X) < STACK_POINTER_REGNUM \
1897 || (REGNO (X) >= FIRST_REX_INT_REG \
1898 && REGNO (X) <= LAST_REX_INT_REG) \
1899 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1901 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \
1902 (REGNO (X) <= STACK_POINTER_REGNUM \
1903 || REGNO (X) == ARG_POINTER_REGNUM \
1904 || REGNO (X) == FRAME_POINTER_REGNUM \
1905 || (REGNO (X) >= FIRST_REX_INT_REG \
1906 && REGNO (X) <= LAST_REX_INT_REG) \
1907 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1909 /* Strict versions, hard registers only */
1910 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1911 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1913 #ifndef REG_OK_STRICT
1914 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X)
1915 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X)
1918 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X)
1919 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
1922 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1923 that is a valid memory address for an instruction.
1924 The MODE argument is the machine mode for the MEM expression
1925 that wants to use this address.
1927 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
1928 except for CONSTANT_ADDRESS_P which is usually machine-independent.
1930 See legitimize_pic_address in i386.c for details as to what
1931 constitutes a legitimate address when -fpic is used. */
1933 #define MAX_REGS_PER_ADDRESS 2
1935 #define CONSTANT_ADDRESS_P(X) \
1936 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1937 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1938 || GET_CODE (X) == CONST_DOUBLE)
1940 /* Nonzero if the constant value X is a legitimate general operand.
1941 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1943 #define LEGITIMATE_CONSTANT_P(X) 1
1945 #ifdef REG_OK_STRICT
1946 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1948 if (legitimate_address_p ((MODE), (X), 1)) \
1953 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1955 if (legitimate_address_p ((MODE), (X), 0)) \
1961 /* If defined, a C expression to determine the base term of address X.
1962 This macro is used in only one place: `find_base_term' in alias.c.
1964 It is always safe for this macro to not be defined. It exists so
1965 that alias analysis can understand machine-dependent addresses.
1967 The typical use of this macro is to handle addresses containing
1968 a label_ref or symbol_ref within an UNSPEC. */
1970 #define FIND_BASE_TERM(X) ix86_find_base_term (X)
1972 /* Try machine-dependent ways of modifying an illegitimate address
1973 to be legitimate. If we find one, return the new, valid address.
1974 This macro is used in only one place: `memory_address' in explow.c.
1976 OLDX is the address as it was before break_out_memory_refs was called.
1977 In some cases it is useful to look at this to decide what needs to be done.
1979 MODE and WIN are passed so that this macro can use
1980 GO_IF_LEGITIMATE_ADDRESS.
1982 It is always safe for this macro to do nothing. It exists to recognize
1983 opportunities to optimize the output.
1985 For the 80386, we handle X+REG by loading X into a register R and
1986 using R+REG. R will go in a general reg and indexing will be used.
1987 However, if REG is a broken-out memory address or multiplication,
1988 nothing needs to be done because REG can certainly go in a general reg.
1990 When -fpic is used, special handling is needed for symbolic references.
1991 See comments by legitimize_pic_address in i386.c for details. */
1993 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1995 (X) = legitimize_address ((X), (OLDX), (MODE)); \
1996 if (memory_address_p ((MODE), (X))) \
2000 #define REWRITE_ADDRESS(X) rewrite_address (X)
2002 /* Nonzero if the constant value X is a legitimate general operand
2003 when generating PIC code. It is given that flag_pic is on and
2004 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
2006 #define LEGITIMATE_PIC_OPERAND_P(X) \
2007 (! SYMBOLIC_CONST (X) \
2008 || legitimate_pic_address_disp_p (X))
2010 #define SYMBOLIC_CONST(X) \
2011 (GET_CODE (X) == SYMBOL_REF \
2012 || GET_CODE (X) == LABEL_REF \
2013 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
2015 /* Go to LABEL if ADDR (a legitimate address expression)
2016 has an effect that depends on the machine mode it is used for.
2017 On the 80386, only postdecrement and postincrement address depend thus
2018 (the amount of decrement or increment being the length of the operand). */
2019 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2021 if (GET_CODE (ADDR) == POST_INC \
2022 || GET_CODE (ADDR) == POST_DEC) \
2026 /* Codes for all the SSE/MMX builtins. */
2038 IX86_BUILTIN_CMPEQPS
,
2039 IX86_BUILTIN_CMPLTPS
,
2040 IX86_BUILTIN_CMPLEPS
,
2041 IX86_BUILTIN_CMPGTPS
,
2042 IX86_BUILTIN_CMPGEPS
,
2043 IX86_BUILTIN_CMPNEQPS
,
2044 IX86_BUILTIN_CMPNLTPS
,
2045 IX86_BUILTIN_CMPNLEPS
,
2046 IX86_BUILTIN_CMPNGTPS
,
2047 IX86_BUILTIN_CMPNGEPS
,
2048 IX86_BUILTIN_CMPORDPS
,
2049 IX86_BUILTIN_CMPUNORDPS
,
2050 IX86_BUILTIN_CMPNEPS
,
2051 IX86_BUILTIN_CMPEQSS
,
2052 IX86_BUILTIN_CMPLTSS
,
2053 IX86_BUILTIN_CMPLESS
,
2054 IX86_BUILTIN_CMPGTSS
,
2055 IX86_BUILTIN_CMPGESS
,
2056 IX86_BUILTIN_CMPNEQSS
,
2057 IX86_BUILTIN_CMPNLTSS
,
2058 IX86_BUILTIN_CMPNLESS
,
2059 IX86_BUILTIN_CMPNGTSS
,
2060 IX86_BUILTIN_CMPNGESS
,
2061 IX86_BUILTIN_CMPORDSS
,
2062 IX86_BUILTIN_CMPUNORDSS
,
2063 IX86_BUILTIN_CMPNESS
,
2065 IX86_BUILTIN_COMIEQSS
,
2066 IX86_BUILTIN_COMILTSS
,
2067 IX86_BUILTIN_COMILESS
,
2068 IX86_BUILTIN_COMIGTSS
,
2069 IX86_BUILTIN_COMIGESS
,
2070 IX86_BUILTIN_COMINEQSS
,
2071 IX86_BUILTIN_UCOMIEQSS
,
2072 IX86_BUILTIN_UCOMILTSS
,
2073 IX86_BUILTIN_UCOMILESS
,
2074 IX86_BUILTIN_UCOMIGTSS
,
2075 IX86_BUILTIN_UCOMIGESS
,
2076 IX86_BUILTIN_UCOMINEQSS
,
2078 IX86_BUILTIN_CVTPI2PS
,
2079 IX86_BUILTIN_CVTPS2PI
,
2080 IX86_BUILTIN_CVTSI2SS
,
2081 IX86_BUILTIN_CVTSS2SI
,
2082 IX86_BUILTIN_CVTTPS2PI
,
2083 IX86_BUILTIN_CVTTSS2SI
,
2090 IX86_BUILTIN_LOADAPS
,
2091 IX86_BUILTIN_LOADUPS
,
2092 IX86_BUILTIN_STOREAPS
,
2093 IX86_BUILTIN_STOREUPS
,
2094 IX86_BUILTIN_LOADSS
,
2095 IX86_BUILTIN_STORESS
,
2098 IX86_BUILTIN_MOVHLPS
,
2099 IX86_BUILTIN_MOVLHPS
,
2100 IX86_BUILTIN_LOADHPS
,
2101 IX86_BUILTIN_LOADLPS
,
2102 IX86_BUILTIN_STOREHPS
,
2103 IX86_BUILTIN_STORELPS
,
2105 IX86_BUILTIN_MASKMOVQ
,
2106 IX86_BUILTIN_MOVMSKPS
,
2107 IX86_BUILTIN_PMOVMSKB
,
2109 IX86_BUILTIN_MOVNTPS
,
2110 IX86_BUILTIN_MOVNTQ
,
2112 IX86_BUILTIN_PACKSSWB
,
2113 IX86_BUILTIN_PACKSSDW
,
2114 IX86_BUILTIN_PACKUSWB
,
2119 IX86_BUILTIN_PADDSB
,
2120 IX86_BUILTIN_PADDSW
,
2121 IX86_BUILTIN_PADDUSB
,
2122 IX86_BUILTIN_PADDUSW
,
2126 IX86_BUILTIN_PSUBSB
,
2127 IX86_BUILTIN_PSUBSW
,
2128 IX86_BUILTIN_PSUBUSB
,
2129 IX86_BUILTIN_PSUBUSW
,
2139 IX86_BUILTIN_PCMPEQB
,
2140 IX86_BUILTIN_PCMPEQW
,
2141 IX86_BUILTIN_PCMPEQD
,
2142 IX86_BUILTIN_PCMPGTB
,
2143 IX86_BUILTIN_PCMPGTW
,
2144 IX86_BUILTIN_PCMPGTD
,
2146 IX86_BUILTIN_PEXTRW
,
2147 IX86_BUILTIN_PINSRW
,
2149 IX86_BUILTIN_PMADDWD
,
2151 IX86_BUILTIN_PMAXSW
,
2152 IX86_BUILTIN_PMAXUB
,
2153 IX86_BUILTIN_PMINSW
,
2154 IX86_BUILTIN_PMINUB
,
2156 IX86_BUILTIN_PMULHUW
,
2157 IX86_BUILTIN_PMULHW
,
2158 IX86_BUILTIN_PMULLW
,
2160 IX86_BUILTIN_PSADBW
,
2161 IX86_BUILTIN_PSHUFW
,
2171 IX86_BUILTIN_PSLLWI
,
2172 IX86_BUILTIN_PSLLDI
,
2173 IX86_BUILTIN_PSLLQI
,
2174 IX86_BUILTIN_PSRAWI
,
2175 IX86_BUILTIN_PSRADI
,
2176 IX86_BUILTIN_PSRLWI
,
2177 IX86_BUILTIN_PSRLDI
,
2178 IX86_BUILTIN_PSRLQI
,
2180 IX86_BUILTIN_PUNPCKHBW
,
2181 IX86_BUILTIN_PUNPCKHWD
,
2182 IX86_BUILTIN_PUNPCKHDQ
,
2183 IX86_BUILTIN_PUNPCKLBW
,
2184 IX86_BUILTIN_PUNPCKLWD
,
2185 IX86_BUILTIN_PUNPCKLDQ
,
2187 IX86_BUILTIN_SHUFPS
,
2191 IX86_BUILTIN_RSQRTPS
,
2192 IX86_BUILTIN_RSQRTSS
,
2193 IX86_BUILTIN_SQRTPS
,
2194 IX86_BUILTIN_SQRTSS
,
2196 IX86_BUILTIN_UNPCKHPS
,
2197 IX86_BUILTIN_UNPCKLPS
,
2200 IX86_BUILTIN_ANDNPS
,
2205 IX86_BUILTIN_LDMXCSR
,
2206 IX86_BUILTIN_STMXCSR
,
2207 IX86_BUILTIN_SFENCE
,
2209 /* 3DNow! Original */
2211 IX86_BUILTIN_PAVGUSB
,
2215 IX86_BUILTIN_PFCMPEQ
,
2216 IX86_BUILTIN_PFCMPGE
,
2217 IX86_BUILTIN_PFCMPGT
,
2222 IX86_BUILTIN_PFRCPIT1
,
2223 IX86_BUILTIN_PFRCPIT2
,
2224 IX86_BUILTIN_PFRSQIT1
,
2225 IX86_BUILTIN_PFRSQRT
,
2227 IX86_BUILTIN_PFSUBR
,
2229 IX86_BUILTIN_PMULHRW
,
2231 /* 3DNow! Athlon Extensions */
2233 IX86_BUILTIN_PFNACC
,
2234 IX86_BUILTIN_PFPNACC
,
2236 IX86_BUILTIN_PSWAPDSI
,
2237 IX86_BUILTIN_PSWAPDSF
,
2239 IX86_BUILTIN_SSE_ZERO
,
2240 IX86_BUILTIN_MMX_ZERO
,
2245 /* Define this macro if references to a symbol must be treated
2246 differently depending on something about the variable or
2247 function named by the symbol (such as what section it is in).
2249 On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol
2250 so that we may access it directly in the GOT. */
2252 #define ENCODE_SECTION_INFO(DECL) \
2256 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2257 ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \
2259 if (GET_CODE (rtl) == MEM) \
2261 if (TARGET_DEBUG_ADDR \
2262 && TREE_CODE_CLASS (TREE_CODE (DECL)) == 'd') \
2264 fprintf (stderr, "Encode %s, public = %d\n", \
2265 IDENTIFIER_POINTER (DECL_NAME (DECL)), \
2266 TREE_PUBLIC (DECL)); \
2269 SYMBOL_REF_FLAG (XEXP (rtl, 0)) \
2270 = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \
2271 || ! TREE_PUBLIC (DECL)); \
2276 /* The `FINALIZE_PIC' macro serves as a hook to emit these special
2277 codes once the function is being compiled into assembly code, but
2278 not before. (It is not done before, because in the case of
2279 compiling an inline function, it would lead to multiple PIC
2280 prologues being included in functions which used inline functions
2281 and were compiled to assembly language.) */
2283 #define FINALIZE_PIC \
2284 (current_function_uses_pic_offset_table |= current_function_profile)
2287 /* Max number of args passed in registers. If this is more than 3, we will
2288 have problems with ebx (register #4), since it is a caller save register and
2289 is also used as the pic register in ELF. So for now, don't allow more than
2290 3 registers to be passed in registers. */
2292 #define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
2294 #define SSE_REGPARM_MAX (TARGET_64BIT ? 8 : 0)
2297 /* Specify the machine mode that this machine uses
2298 for the index in the tablejump instruction. */
2299 #define CASE_VECTOR_MODE (!TARGET_64BIT || flag_pic ? SImode : DImode)
2301 /* Define as C expression which evaluates to nonzero if the tablejump
2302 instruction expects the table to contain offsets from the address of the
2304 Do not define this if the table should contain absolute addresses. */
2305 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2307 /* Define this as 1 if `char' should by default be signed; else as 0. */
2308 #define DEFAULT_SIGNED_CHAR 1
2310 /* Number of bytes moved into a data cache for a single prefetch operation. */
2311 #define PREFETCH_BLOCK ix86_cost->prefetch_block
2313 /* Number of prefetch operations that can be done in parallel. */
2314 #define SIMULTANEOUS_PREFETCHES ix86_cost->simultaneous_prefetches
2316 /* Max number of bytes we can move from memory to memory
2317 in one reasonably fast instruction. */
2320 /* MOVE_MAX_PIECES is the number of bytes at a time which we can
2321 move efficiently, as opposed to MOVE_MAX which is the maximum
2322 number of bytes we can move with a single instruction. */
2323 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4)
2325 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2326 move-instruction pairs, we will do a movstr or libcall instead.
2327 Increasing the value will always make code faster, but eventually
2328 incurs high cost in increased code size.
2330 If you don't define this, a reasonable default is used. */
2332 #define MOVE_RATIO (optimize_size ? 3 : ix86_cost->move_ratio)
2334 /* Define if shifts truncate the shift count
2335 which implies one can omit a sign-extension or zero-extension
2336 of a shift count. */
2337 /* On i386, shifts do truncate the count. But bit opcodes don't. */
2339 /* #define SHIFT_COUNT_TRUNCATED */
2341 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2342 is done just by pretending it is already truncated. */
2343 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2345 /* We assume that the store-condition-codes instructions store 0 for false
2346 and some other value for true. This is the value stored for true. */
2348 #define STORE_FLAG_VALUE 1
2350 /* When a prototype says `char' or `short', really pass an `int'.
2351 (The 386 can't easily push less than an int.) */
2353 #define PROMOTE_PROTOTYPES (!TARGET_64BIT)
2355 /* A macro to update M and UNSIGNEDP when an object whose type is
2356 TYPE and which has the specified mode and signedness is to be
2357 stored in a register. This macro is only called when TYPE is a
2360 On i386 it is sometimes useful to promote HImode and QImode
2361 quantities to SImode. The choice depends on target type. */
2363 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2365 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \
2366 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \
2370 /* Specify the machine mode that pointers have.
2371 After generation of rtl, the compiler makes no further distinction
2372 between pointers and any other objects of this machine mode. */
2373 #define Pmode (TARGET_64BIT ? DImode : SImode)
2375 /* A function address in a call instruction
2376 is a byte address (for indexing purposes)
2377 so give the MEM rtx a byte's mode. */
2378 #define FUNCTION_MODE QImode
2380 /* A part of a C `switch' statement that describes the relative costs
2381 of constant RTL expressions. It must contain `case' labels for
2382 expression codes `const_int', `const', `symbol_ref', `label_ref'
2383 and `const_double'. Each case must ultimately reach a `return'
2384 statement to return the relative cost of the use of that kind of
2385 constant value in an expression. The cost may depend on the
2386 precise value of the constant, which is available for examination
2387 in X, and the rtx code of the expression in which it is contained,
2388 found in OUTER_CODE.
2390 CODE is the expression code--redundant, since it can be obtained
2391 with `GET_CODE (X)'. */
2393 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
2398 if (TARGET_64BIT && !x86_64_sign_extended_value (RTX)) \
2400 if (TARGET_64BIT && !x86_64_zero_extended_value (RTX)) \
2402 return flag_pic && SYMBOLIC_CONST (RTX) ? 1 : 0; \
2404 case CONST_DOUBLE: \
2407 if (GET_MODE (RTX) == VOIDmode) \
2410 code = standard_80387_constant_p (RTX); \
2411 return code == 1 ? 1 : \
2416 /* Delete the definition here when TOPLEVEL_COSTS_N_INSNS gets added to cse.c */
2417 #define TOPLEVEL_COSTS_N_INSNS(N) \
2418 do { total = COSTS_N_INSNS (N); goto egress_rtx_costs; } while (0)
2420 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
2421 This can be used, for example, to indicate how costly a multiply
2422 instruction is. In writing this macro, you can use the construct
2423 `COSTS_N_INSNS (N)' to specify a cost equal to N fast
2424 instructions. OUTER_CODE is the code of the expression in which X
2427 This macro is optional; do not define it if the default cost
2428 assumptions are adequate for the target machine. */
2430 #define RTX_COSTS(X, CODE, OUTER_CODE) \
2432 /* The zero extensions is often completely free on x86_64, so make \
2433 it as cheap as possible. */ \
2434 if (TARGET_64BIT && GET_MODE (X) == DImode \
2435 && GET_MODE (XEXP (X, 0)) == SImode) \
2437 total = 1; goto egress_rtx_costs; \
2440 TOPLEVEL_COSTS_N_INSNS (TARGET_ZERO_EXTEND_WITH_AND ? \
2441 ix86_cost->add : ix86_cost->movzx); \
2444 TOPLEVEL_COSTS_N_INSNS (ix86_cost->movsx); \
2447 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2448 && (GET_MODE (XEXP (X, 0)) != DImode || TARGET_64BIT)) \
2450 HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2452 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2453 if ((value == 2 || value == 3) \
2454 && !TARGET_DECOMPOSE_LEA \
2455 && ix86_cost->lea <= ix86_cost->shift_const) \
2456 TOPLEVEL_COSTS_N_INSNS (ix86_cost->lea); \
2458 /* fall through */ \
2464 if (!TARGET_64BIT && GET_MODE (XEXP (X, 0)) == DImode) \
2466 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2468 if (INTVAL (XEXP (X, 1)) > 32) \
2469 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const + 2); \
2471 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_const * 2); \
2475 if (GET_CODE (XEXP (X, 1)) == AND) \
2476 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 2); \
2478 TOPLEVEL_COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); \
2483 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2484 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_const); \
2486 TOPLEVEL_COSTS_N_INSNS (ix86_cost->shift_var); \
2491 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2493 unsigned HOST_WIDE_INT value = INTVAL (XEXP (X, 1)); \
2496 while (value != 0) \
2502 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2503 + nbits * ix86_cost->mult_bit); \
2505 else /* This is arbitrary */ \
2506 TOPLEVEL_COSTS_N_INSNS (ix86_cost->mult_init \
2507 + 7 * ix86_cost->mult_bit); \
2513 TOPLEVEL_COSTS_N_INSNS (ix86_cost->divide); \
2516 if (!TARGET_DECOMPOSE_LEA \
2517 && INTEGRAL_MODE_P (GET_MODE (X)) \
2518 && GET_MODE_BITSIZE (GET_MODE (X)) <= GET_MODE_BITSIZE (Pmode)) \
2520 if (GET_CODE (XEXP (X, 0)) == PLUS \
2521 && GET_CODE (XEXP (XEXP (X, 0), 0)) == MULT \
2522 && GET_CODE (XEXP (XEXP (XEXP (X, 0), 0), 1)) == CONST_INT \
2523 && CONSTANT_P (XEXP (X, 1))) \
2525 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 0), 0), 1));\
2526 if (val == 2 || val == 4 || val == 8) \
2528 return (COSTS_N_INSNS (ix86_cost->lea) \
2529 + rtx_cost (XEXP (XEXP (X, 0), 1), \
2531 + rtx_cost (XEXP (XEXP (XEXP (X, 0), 0), 0), \
2533 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2536 else if (GET_CODE (XEXP (X, 0)) == MULT \
2537 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
2539 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
2540 if (val == 2 || val == 4 || val == 8) \
2542 return (COSTS_N_INSNS (ix86_cost->lea) \
2543 + rtx_cost (XEXP (XEXP (X, 0), 0), \
2545 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2548 else if (GET_CODE (XEXP (X, 0)) == PLUS) \
2550 return (COSTS_N_INSNS (ix86_cost->lea) \
2551 + rtx_cost (XEXP (XEXP (X, 0), 0), (OUTER_CODE)) \
2552 + rtx_cost (XEXP (XEXP (X, 0), 1), (OUTER_CODE)) \
2553 + rtx_cost (XEXP (X, 1), (OUTER_CODE))); \
2557 /* fall through */ \
2562 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2563 return (COSTS_N_INSNS (ix86_cost->add) * 2 \
2564 + (rtx_cost (XEXP (X, 0), (OUTER_CODE)) \
2565 << (GET_MODE (XEXP (X, 0)) != DImode)) \
2566 + (rtx_cost (XEXP (X, 1), (OUTER_CODE)) \
2567 << (GET_MODE (XEXP (X, 1)) != DImode))); \
2569 /* fall through */ \
2572 if (!TARGET_64BIT && GET_MODE (X) == DImode) \
2573 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add * 2); \
2574 TOPLEVEL_COSTS_N_INSNS (ix86_cost->add); \
2580 /* An expression giving the cost of an addressing mode that contains
2581 ADDRESS. If not defined, the cost is computed from the ADDRESS
2582 expression and the `CONST_COSTS' values.
2584 For most CISC machines, the default cost is a good approximation
2585 of the true cost of the addressing mode. However, on RISC
2586 machines, all instructions normally have the same length and
2587 execution time. Hence all addresses will have equal costs.
2589 In cases where more than one form of an address is known, the form
2590 with the lowest cost will be used. If multiple forms have the
2591 same, lowest, cost, the one that is the most complex will be used.
2593 For example, suppose an address that is equal to the sum of a
2594 register and a constant is used twice in the same basic block.
2595 When this macro is not defined, the address will be computed in a
2596 register and memory references will be indirect through that
2597 register. On machines where the cost of the addressing mode
2598 containing the sum is no higher than that of a simple indirect
2599 reference, this will produce an additional instruction and
2600 possibly require an additional register. Proper specification of
2601 this macro eliminates this overhead for such machines.
2603 Similar use of this macro is made in strength reduction of loops.
2605 ADDRESS need not be valid as an address. In such a case, the cost
2606 is not relevant and can be any value; invalid addresses need not be
2607 assigned a different cost.
2609 On machines where an address involving more than one register is as
2610 cheap as an address computation involving only one register,
2611 defining `ADDRESS_COST' to reflect this can cause two registers to
2612 be live over a region of code where only one would have been if
2613 `ADDRESS_COST' were not defined in that manner. This effect should
2614 be considered in the definition of this macro. Equivalent costs
2615 should probably only be given to addresses with different numbers
2616 of registers on machines with lots of registers.
2618 This macro will normally either not be defined or be defined as a
2621 For i386, it is better to use a complex address than let gcc copy
2622 the address into a reg and make a new pseudo. But not if the address
2623 requires to two regs - that would mean more pseudos with longer
2626 #define ADDRESS_COST(RTX) \
2627 ix86_address_cost (RTX)
2629 /* A C expression for the cost of moving data from a register in class FROM to
2630 one in class TO. The classes are expressed using the enumeration values
2631 such as `GENERAL_REGS'. A value of 2 is the default; other values are
2632 interpreted relative to that.
2634 It is not required that the cost always equal 2 when FROM is the same as TO;
2635 on some machines it is expensive to move between registers if they are not
2636 general registers. */
2638 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2639 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2))
2641 /* A C expression for the cost of moving data of mode M between a
2642 register and memory. A value of 2 is the default; this cost is
2643 relative to those in `REGISTER_MOVE_COST'.
2645 If moving between registers and memory is more expensive than
2646 between two registers, you should define this macro to express the
2649 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
2650 ix86_memory_move_cost ((MODE), (CLASS), (IN))
2652 /* A C expression for the cost of a branch instruction. A value of 1
2653 is the default; other values are interpreted relative to that. */
2655 #define BRANCH_COST ix86_branch_cost
2657 /* Define this macro as a C expression which is nonzero if accessing
2658 less than a word of memory (i.e. a `char' or a `short') is no
2659 faster than accessing a word of memory, i.e., if such access
2660 require more than one instruction or if there is no difference in
2661 cost between byte and (aligned) word loads.
2663 When this macro is not defined, the compiler will access a field by
2664 finding the smallest containing object; when it is defined, a
2665 fullword load will be used if alignment permits. Unless bytes
2666 accesses are faster than word accesses, using word accesses is
2667 preferable since it may eliminate subsequent memory access if
2668 subsequent accesses occur to other fields in the same word of the
2669 structure, but to different bytes. */
2671 #define SLOW_BYTE_ACCESS 0
2673 /* Nonzero if access to memory by shorts is slow and undesirable. */
2674 #define SLOW_SHORT_ACCESS 0
2676 /* Define this macro to be the value 1 if unaligned accesses have a
2677 cost many times greater than aligned accesses, for example if they
2678 are emulated in a trap handler.
2680 When this macro is non-zero, the compiler will act as if
2681 `STRICT_ALIGNMENT' were non-zero when generating code for block
2682 moves. This can cause significantly more instructions to be
2683 produced. Therefore, do not set this macro non-zero if unaligned
2684 accesses only add a cycle or two to the time for a memory access.
2686 If the value of this macro is always zero, it need not be defined. */
2688 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */
2690 /* Define this macro to inhibit strength reduction of memory
2691 addresses. (On some machines, such strength reduction seems to do
2692 harm rather than good.) */
2694 /* #define DONT_REDUCE_ADDR */
2696 /* Define this macro if it is as good or better to call a constant
2697 function address than to call an address kept in a register.
2699 Desirable on the 386 because a CALL with a constant address is
2700 faster than one with a register address. */
2702 #define NO_FUNCTION_CSE
2704 /* Define this macro if it is as good or better for a function to call
2705 itself with an explicit address than to call an address kept in a
2708 #define NO_RECURSIVE_FUNCTION_CSE
2710 /* Add any extra modes needed to represent the condition code.
2712 For the i386, we need separate modes when floating-point
2713 equality comparisons are being done.
2715 Add CCNO to indicate comparisons against zero that requires
2716 Overflow flag to be unset. Sign bit test is used instead and
2717 thus can be used to form "a&b>0" type of tests.
2719 Add CCGC to indicate comparisons agains zero that allows
2720 unspecified garbage in the Carry flag. This mode is used
2721 by inc/dec instructions.
2723 Add CCGOC to indicate comparisons agains zero that allows
2724 unspecified garbage in the Carry and Overflow flag. This
2725 mode is used to simulate comparisons of (a-b) and (a+b)
2726 against zero using sub/cmp/add operations.
2728 Add CCZ to indicate that only the Zero flag is valid. */
2730 #define EXTRA_CC_MODES \
2731 CC (CCGCmode, "CCGC") \
2732 CC (CCGOCmode, "CCGOC") \
2733 CC (CCNOmode, "CCNO") \
2734 CC (CCZmode, "CCZ") \
2735 CC (CCFPmode, "CCFP") \
2736 CC (CCFPUmode, "CCFPU")
2738 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2739 return the mode to be used for the comparison.
2741 For floating-point equality comparisons, CCFPEQmode should be used.
2742 VOIDmode should be used in all other cases.
2744 For integer comparisons against zero, reduce to CCNOmode or CCZmode if
2745 possible, to allow for more combinations. */
2747 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y))
2749 /* Return non-zero if MODE implies a floating point inequality can be
2752 #define REVERSIBLE_CC_MODE(MODE) 1
2754 /* A C expression whose value is reversed condition code of the CODE for
2755 comparison done in CC_MODE mode. */
2756 #define REVERSE_CONDITION(CODE, MODE) \
2757 ((MODE) != CCFPmode && (MODE) != CCFPUmode ? reverse_condition (CODE) \
2758 : reverse_condition_maybe_unordered (CODE))
2761 /* Control the assembler format that we output, to the extent
2762 this does not vary between assemblers. */
2764 /* How to refer to registers in assembler output.
2765 This sequence is indexed by compiler's hard-register-number (see above). */
2767 /* In order to refer to the first 8 regs as 32 bit regs prefix an "e"
2768 For non floating point regs, the following are the HImode names.
2770 For float regs, the stack top is sometimes referred to as "%st(0)"
2771 instead of just "%st". PRINT_REG handles this with the "y" code. */
2773 #undef HI_REGISTER_NAMES
2774 #define HI_REGISTER_NAMES \
2775 {"ax","dx","cx","bx","si","di","bp","sp", \
2776 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","", \
2777 "flags","fpsr", "dirflag", "frame", \
2778 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \
2779 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7" , \
2780 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2781 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
2783 #define REGISTER_NAMES HI_REGISTER_NAMES
2785 /* Table of additional register names to use in user input. */
2787 #define ADDITIONAL_REGISTER_NAMES \
2788 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \
2789 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \
2790 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \
2791 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \
2792 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \
2793 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 }, \
2794 { "mm0", 8}, { "mm1", 9}, { "mm2", 10}, { "mm3", 11}, \
2795 { "mm4", 12}, { "mm5", 13}, { "mm6", 14}, { "mm7", 15} }
2797 /* Note we are omitting these since currently I don't know how
2798 to get gcc to use these, since they want the same but different
2799 number as al, and ax.
2802 #define QI_REGISTER_NAMES \
2803 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",}
2805 /* These parallel the array above, and can be used to access bits 8:15
2806 of regs 0 through 3. */
2808 #define QI_HIGH_REGISTER_NAMES \
2809 {"ah", "dh", "ch", "bh", }
2811 /* How to renumber registers for dbx and gdb. */
2813 #define DBX_REGISTER_NUMBER(N) \
2814 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)])
2816 extern int const dbx_register_map
[FIRST_PSEUDO_REGISTER
];
2817 extern int const dbx64_register_map
[FIRST_PSEUDO_REGISTER
];
2818 extern int const svr4_dbx_register_map
[FIRST_PSEUDO_REGISTER
];
2820 /* Before the prologue, RA is at 0(%esp). */
2821 #define INCOMING_RETURN_ADDR_RTX \
2822 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
2824 /* After the prologue, RA is at -4(AP) in the current frame. */
2825 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2827 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \
2828 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
2830 /* PC is dbx register 8; let's use that column for RA. */
2831 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8)
2833 /* Before the prologue, the top of the frame is at 4(%esp). */
2834 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD
2836 /* Describe how we implement __builtin_eh_return. */
2837 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
2838 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
2841 /* Select a format to encode pointers in exception handling data. CODE
2842 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
2843 true if the symbol may be affected by dynamic relocations.
2845 ??? All x86 object file formats are capable of representing this.
2846 After all, the relocation needed is the same as for the call insn.
2847 Whether or not a particular assembler allows us to enter such, I
2848 guess we'll have to see. */
2849 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2851 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
2854 /* This is how to output the definition of a user-level label named NAME,
2855 such as the label on a static function or variable NAME. */
2857 #define ASM_OUTPUT_LABEL(FILE, NAME) \
2858 (assemble_name ((FILE), (NAME)), fputs (":\n", (FILE)))
2860 /* Store in OUTPUT a string (made with alloca) containing
2861 an assembler-name for a local static variable named NAME.
2862 LABELNO is an integer which is different for each call. */
2864 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2865 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2866 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2868 /* This is how to output an insn to push a register on the stack.
2869 It need not be very fast code. */
2871 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
2872 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)])
2874 /* This is how to output an insn to pop a register from the stack.
2875 It need not be very fast code. */
2877 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
2878 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)])
2880 /* This is how to output an element of a case-vector that is absolute. */
2882 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2883 ix86_output_addr_vec_elt ((FILE), (VALUE))
2885 /* This is how to output an element of a case-vector that is relative. */
2887 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2888 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL))
2890 /* Under some conditions we need jump tables in the text section, because
2891 the assembler cannot handle label differences between sections. */
2893 #define JUMP_TABLES_IN_TEXT_SECTION \
2894 (!TARGET_64BIT && flag_pic && !HAVE_AS_GOTOFF_IN_DATA)
2896 /* A C statement that outputs an address constant appropriate to
2897 for DWARF debugging. */
2899 #define ASM_OUTPUT_DWARF_ADDR_CONST(FILE, X) \
2900 i386_dwarf_output_addr_const ((FILE), (X))
2902 /* Either simplify a location expression, or return the original. */
2904 #define ASM_SIMPLIFY_DWARF_ADDR(X) \
2905 i386_simplify_dwarf_addr (X)
2907 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC,
2908 and switch back. For x86 we do this only to save a few bytes that
2909 would otherwise be unused in the text section. */
2910 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2911 asm (SECTION_OP "\n\t" \
2912 "call " USER_LABEL_PREFIX #FUNC "\n" \
2913 TEXT_SECTION_ASM_OP);
2915 /* Print operand X (an rtx) in assembler syntax to file FILE.
2916 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2917 Effect of various CODE letters is described in i386.c near
2918 print_operand function. */
2920 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2921 ((CODE) == '*' || (CODE) == '+')
2923 /* Print the name of a register based on its machine mode and number.
2924 If CODE is 'w', pretend the mode is HImode.
2925 If CODE is 'b', pretend the mode is QImode.
2926 If CODE is 'k', pretend the mode is SImode.
2927 If CODE is 'q', pretend the mode is DImode.
2928 If CODE is 'h', pretend the reg is the `high' byte register.
2929 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */
2931 #define PRINT_REG(X, CODE, FILE) \
2932 print_reg ((X), (CODE), (FILE))
2934 #define PRINT_OPERAND(FILE, X, CODE) \
2935 print_operand ((FILE), (X), (CODE))
2937 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2938 print_operand_address ((FILE), (ADDR))
2940 /* Print the name of a register for based on its machine mode and number.
2941 This macro is used to print debugging output.
2942 This macro is different from PRINT_REG in that it may be used in
2943 programs that are not linked with aux-output.o. */
2945 #define DEBUG_PRINT_REG(X, CODE, FILE) \
2946 do { static const char * const hi_name[] = HI_REGISTER_NAMES; \
2947 static const char * const qi_name[] = QI_REGISTER_NAMES; \
2948 fprintf ((FILE), "%d ", REGNO (X)); \
2949 if (REGNO (X) == FLAGS_REG) \
2950 { fputs ("flags", (FILE)); break; } \
2951 if (REGNO (X) == DIRFLAG_REG) \
2952 { fputs ("dirflag", (FILE)); break; } \
2953 if (REGNO (X) == FPSR_REG) \
2954 { fputs ("fpsr", (FILE)); break; } \
2955 if (REGNO (X) == ARG_POINTER_REGNUM) \
2956 { fputs ("argp", (FILE)); break; } \
2957 if (REGNO (X) == FRAME_POINTER_REGNUM) \
2958 { fputs ("frame", (FILE)); break; } \
2959 if (STACK_TOP_P (X)) \
2960 { fputs ("st(0)", (FILE)); break; } \
2962 { fputs (hi_name[REGNO(X)], (FILE)); break; } \
2963 if (REX_INT_REG_P (X)) \
2965 switch (GET_MODE_SIZE (GET_MODE (X))) \
2969 fprintf ((FILE), "r%i", REGNO (X) \
2970 - FIRST_REX_INT_REG + 8); \
2973 fprintf ((FILE), "r%id", REGNO (X) \
2974 - FIRST_REX_INT_REG + 8); \
2977 fprintf ((FILE), "r%iw", REGNO (X) \
2978 - FIRST_REX_INT_REG + 8); \
2981 fprintf ((FILE), "r%ib", REGNO (X) \
2982 - FIRST_REX_INT_REG + 8); \
2987 switch (GET_MODE_SIZE (GET_MODE (X))) \
2990 fputs ("r", (FILE)); \
2991 fputs (hi_name[REGNO (X)], (FILE)); \
2994 fputs ("e", (FILE)); \
2996 fputs (hi_name[REGNO (X)], (FILE)); \
2999 fputs (qi_name[REGNO (X)], (FILE)); \
3004 /* a letter which is not needed by the normal asm syntax, which
3005 we can use for operand syntax in the extended asm */
3007 #define ASM_OPERAND_LETTER '#'
3008 #define RET return ""
3009 #define AT_SP(MODE) (gen_rtx_MEM ((MODE), stack_pointer_rtx))
3011 /* Define the codes that are matched by predicates in i386.c. */
3013 #define PREDICATE_CODES \
3014 {"x86_64_immediate_operand", {CONST_INT, SUBREG, REG, \
3015 SYMBOL_REF, LABEL_REF, CONST}}, \
3016 {"x86_64_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3017 SYMBOL_REF, LABEL_REF, CONST}}, \
3018 {"x86_64_movabs_operand", {CONST_INT, SUBREG, REG, \
3019 SYMBOL_REF, LABEL_REF, CONST}}, \
3020 {"x86_64_szext_nonmemory_operand", {CONST_INT, SUBREG, REG, \
3021 SYMBOL_REF, LABEL_REF, CONST}}, \
3022 {"x86_64_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3023 SYMBOL_REF, LABEL_REF, CONST}}, \
3024 {"x86_64_szext_general_operand", {CONST_INT, SUBREG, REG, MEM, \
3025 SYMBOL_REF, LABEL_REF, CONST}}, \
3026 {"x86_64_zext_immediate_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3027 SYMBOL_REF, LABEL_REF}}, \
3028 {"shiftdi_operand", {SUBREG, REG, MEM}}, \
3029 {"const_int_1_operand", {CONST_INT}}, \
3030 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
3031 {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3032 LABEL_REF, SUBREG, REG, MEM}}, \
3033 {"pic_symbolic_operand", {CONST}}, \
3034 {"call_insn_operand", {REG, SUBREG, MEM, SYMBOL_REF}}, \
3035 {"constant_call_address_operand", {SYMBOL_REF, CONST}}, \
3036 {"const0_operand", {CONST_INT, CONST_DOUBLE}}, \
3037 {"const1_operand", {CONST_INT}}, \
3038 {"const248_operand", {CONST_INT}}, \
3039 {"incdec_operand", {CONST_INT}}, \
3040 {"mmx_reg_operand", {REG}}, \
3041 {"reg_no_sp_operand", {SUBREG, REG}}, \
3042 {"general_no_elim_operand", {CONST_INT, CONST_DOUBLE, CONST, \
3043 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM}}, \
3044 {"nonmemory_no_elim_operand", {CONST_INT, REG, SUBREG}}, \
3045 {"q_regs_operand", {SUBREG, REG}}, \
3046 {"non_q_regs_operand", {SUBREG, REG}}, \
3047 {"fcmov_comparison_operator", {EQ, NE, LTU, GTU, LEU, GEU, UNORDERED, \
3048 ORDERED, LT, UNLT, GT, UNGT, LE, UNLE, \
3049 GE, UNGE, LTGT, UNEQ}}, \
3050 {"sse_comparison_operator", {EQ, LT, LE, UNORDERED, NE, UNGE, UNGT, \
3051 ORDERED, UNEQ, UNLT, UNLE, LTGT, GE, GT \
3053 {"ix86_comparison_operator", {EQ, NE, LE, LT, GE, GT, LEU, LTU, GEU, \
3054 GTU, UNORDERED, ORDERED, UNLE, UNLT, \
3055 UNGE, UNGT, LTGT, UNEQ }}, \
3056 {"cmp_fp_expander_operand", {CONST_DOUBLE, SUBREG, REG, MEM}}, \
3057 {"ext_register_operand", {SUBREG, REG}}, \
3058 {"binary_fp_operator", {PLUS, MINUS, MULT, DIV}}, \
3059 {"mult_operator", {MULT}}, \
3060 {"div_operator", {DIV}}, \
3061 {"arith_or_logical_operator", {PLUS, MULT, AND, IOR, XOR, SMIN, SMAX, \
3062 UMIN, UMAX, COMPARE, MINUS, DIV, MOD, \
3063 UDIV, UMOD, ASHIFT, ROTATE, ASHIFTRT, \
3064 LSHIFTRT, ROTATERT}}, \
3065 {"promotable_binary_operator", {PLUS, MULT, AND, IOR, XOR, ASHIFT}}, \
3066 {"memory_displacement_operand", {MEM}}, \
3067 {"cmpsi_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
3068 LABEL_REF, SUBREG, REG, MEM, AND}}, \
3069 {"long_memory_operand", {MEM}},
3071 /* A list of predicates that do special things with modes, and so
3072 should not elicit warnings for VOIDmode match_operand. */
3074 #define SPECIAL_MODE_PREDICATES \
3075 "ext_register_operand",
3077 /* CM_32 is used by 32bit ABI
3078 CM_SMALL is small model assuming that all code and data fits in the first
3079 31bits of address space.
3080 CM_KERNEL is model assuming that all code and data fits in the negative
3081 31bits of address space.
3082 CM_MEDIUM is model assuming that code fits in the first 31bits of address
3083 space. Size of data is unlimited.
3084 CM_LARGE is model making no assumptions about size of particular sections.
3086 CM_SMALL_PIC is model for PIC libraries assuming that code+data+got/plt
3087 tables first in 31bits of address space.
3098 /* Size of the RED_ZONE area. */
3099 #define RED_ZONE_SIZE 128
3100 /* Reserved area of the red zone for temporaries. */
3101 #define RED_ZONE_RESERVE 8
3102 extern const char *ix86_debug_arg_string
, *ix86_debug_addr_string
;
3108 extern const char *ix86_asm_string
;
3109 extern enum asm_dialect ix86_asm_dialect
;
3110 /* Value of -mcmodel specified by user. */
3111 extern const char *ix86_cmodel_string
;
3112 extern enum cmodel ix86_cmodel
;
3114 /* Variables in i386.c */
3115 extern const char *ix86_cpu_string
; /* for -mcpu=<xxx> */
3116 extern const char *ix86_arch_string
; /* for -march=<xxx> */
3117 extern const char *ix86_fpmath_string
; /* for -mfpmath=<xxx> */
3118 extern const char *ix86_regparm_string
; /* # registers to use to pass args */
3119 extern const char *ix86_align_loops_string
; /* power of two alignment for loops */
3120 extern const char *ix86_align_jumps_string
; /* power of two alignment for non-loop jumps */
3121 extern const char *ix86_align_funcs_string
; /* power of two alignment for functions */
3122 extern const char *ix86_preferred_stack_boundary_string
;/* power of two alignment for stack boundary */
3123 extern const char *ix86_branch_cost_string
; /* values 1-5: see jump.c */
3124 extern int ix86_regparm
; /* ix86_regparm_string as a number */
3125 extern int ix86_preferred_stack_boundary
; /* preferred stack boundary alignment in bits */
3126 extern int ix86_branch_cost
; /* values 1-5: see jump.c */
3127 extern enum reg_class
const regclass_map
[FIRST_PSEUDO_REGISTER
]; /* smalled class containing REGNO */
3128 // Commented out the following two lines due to lack of definition for "rtx" - Brian
3129 //extern rtx ix86_compare_op0; /* operand 0 for comparisons */
3130 //extern rtx ix86_compare_op1; /* operand 1 for comparisons */
3132 /* To properly truncate FP values into integers, we need to set i387 control
3133 word. We can't emit proper mode switching code before reload, as spills
3134 generated by reload may truncate values incorrectly, but we still can avoid
3135 redundant computation of new control word by the mode switching pass.
3136 The fldcw instructions are still emitted redundantly, but this is probably
3137 not going to be noticeable problem, as most CPUs do have fast path for
3140 The machinery is to emit simple truncation instructions and split them
3141 before reload to instructions having USEs of two memory locations that
3142 are filled by this code to old and new control word.
3144 Post-reload pass may be later used to eliminate the redundant fildcw if
3147 enum fp_cw_mode
{FP_CW_STORED
, FP_CW_UNINITIALIZED
, FP_CW_ANY
};
3149 /* Define this macro if the port needs extra instructions inserted
3150 for mode switching in an optimizing compilation. */
3152 #define OPTIMIZE_MODE_SWITCHING(ENTITY) 1
3154 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as
3155 initializer for an array of integers. Each initializer element N
3156 refers to an entity that needs mode switching, and specifies the
3157 number of different modes that might need to be set for this
3158 entity. The position of the initializer in the initializer -
3159 starting counting at zero - determines the integer that is used to
3160 refer to the mode-switched entity in question. */
3162 #define NUM_MODES_FOR_MODE_SWITCHING { FP_CW_ANY }
3164 /* ENTITY is an integer specifying a mode-switched entity. If
3165 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to
3166 return an integer value not larger than the corresponding element
3167 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY
3168 must be switched into prior to the execution of INSN. */
3170 #define MODE_NEEDED(ENTITY, I) \
3171 (GET_CODE (I) == CALL_INSN \
3172 || (GET_CODE (I) == INSN && (asm_noperands (PATTERN (I)) >= 0 \
3173 || GET_CODE (PATTERN (I)) == ASM_INPUT))\
3174 ? FP_CW_UNINITIALIZED \
3175 : recog_memoized (I) < 0 || get_attr_type (I) != TYPE_FISTP \
3179 /* This macro specifies the order in which modes for ENTITY are
3180 processed. 0 is the highest priority. */
3182 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N)
3184 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
3185 is the set of hard registers live at the point where the insn(s)
3186 are to be inserted. */
3188 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3189 ((MODE) == FP_CW_STORED \
3190 ? emit_i387_cw_initialization (assign_386_stack_local (HImode, 1), \
3191 assign_386_stack_local (HImode, 2)), 0\
3194 /* Avoid renaming of stack registers, as doing so in combination with
3195 scheduling just increases amount of live registers at time and in
3196 the turn amount of fxch instructions needed.
3198 ??? Maybe Pentium chips benefits from renaming, someone can try... */
3200 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \
3201 ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG)
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