reactos/dll/3rdparty/mesa32/src/tnl/t_vb_arbprogram.c

   1 /*
   2  * Mesa 3-D graphics library
   3  * Version:  6.3
   4  *
   5  * Copyright (C) 1999-2005  Brian Paul   All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included
  15  * in all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  21  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  22  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 /**
  26  * \file t_arb_program.c
  27  * Compile vertex programs to an intermediate representation.
  28  * Execute vertex programs over a buffer of vertices.
  29  * \author Keith Whitwell, Brian Paul
  30  */
  31
  32 #include "glheader.h"
  33 #include "context.h"
  34 #include "imports.h"
  35 #include "macros.h"
  36 #include "mtypes.h"
  37 #include "arbprogparse.h"
  38 #include "light.h"
  39 #include "program.h"
  40 #include "math/m_matrix.h"
  41 #include "math/m_translate.h"
  42 #include "t_context.h"
  43 #include "t_pipeline.h"
  44 #include "t_vb_arbprogram.h"
  45
  46 #define DISASSEM 0
  47
  48 /*--------------------------------------------------------------------------- */
  49
  50 struct opcode_info {
  51    GLuint nr_args;
  52    const char *string;
  53    void (*print)( union instruction , const struct opcode_info * );
  54 };
  55
  56 struct compilation {
  57    GLuint reg_active;
  58    union instruction *csr;
  59 };
  60
  61
  62 #define ARB_VP_MACHINE(stage) ((struct arb_vp_machine *)(stage->privatePtr))
  63
  64 #define PUFF(x) ((x)[1] = (x)[2] = (x)[3] = (x)[0])
  65
  66
  67
  68 /* Lower precision functions for the EXP, LOG and LIT opcodes.  The
  69  * LOG2() implementation is probably not accurate enough, and the
  70  * attempted optimization for Exp2 is definitely not accurate
  71  * enough - it discards all of t's fractional bits!
  72  */
  73 static GLfloat RoughApproxLog2(GLfloat t)
  74 {
  75    return LOG2(t);
  76 }
  77
  78 static GLfloat RoughApproxExp2(GLfloat t)
  79 {
  80 #if 0
  81    fi_type fi;
  82    fi.i = (GLint) t;
  83    fi.i = (fi.i << 23) + 0x3f800000;
  84    return fi.f;
  85 #else
  86    return (GLfloat) _mesa_pow(2.0, t);
  87 #endif
  88 }
  89
  90 static GLfloat RoughApproxPower(GLfloat x, GLfloat y)
  91 {
  92    return RoughApproxExp2(y * RoughApproxLog2(x));
  93 }
  94
  95
  96 /* Higher precision functions for the EX2, LG2 and POW opcodes:
  97  */
  98 static GLfloat ApproxLog2(GLfloat t)
  99 {
 100    return (GLfloat) (log(t) * 1.442695F);
 101 }
 102
 103 static GLfloat ApproxExp2(GLfloat t)
 104 {
 105    return (GLfloat) _mesa_pow(2.0, t);
 106 }
 107
 108 static GLfloat ApproxPower(GLfloat x, GLfloat y)
 109 {
 110    return (GLfloat) _mesa_pow(x, y);
 111 }
 112
 113 static GLfloat rough_approx_log2_0_1(GLfloat x)
 114 {
 115    return LOG2(x);
 116 }
 117
 118
 119
 120
 121 /**
 122  * Perform a reduced swizzle:
 123  */
 124 static void do_RSW( struct arb_vp_machine *m, union instruction op )
 125 {
 126    GLfloat *result = m->File[0][op.rsw.dst];
 127    const GLfloat *arg0 = m->File[op.rsw.file0][op.rsw.idx0];
 128    GLuint swz = op.rsw.swz;
 129    GLuint neg = op.rsw.neg;
 130
 131    result[0] = arg0[GET_RSW(swz, 0)];
 132    result[1] = arg0[GET_RSW(swz, 1)];
 133    result[2] = arg0[GET_RSW(swz, 2)];
 134    result[3] = arg0[GET_RSW(swz, 3)];
 135
 136    if (neg) {
 137       if (neg & 0x1) result[0] = -result[0];
 138       if (neg & 0x2) result[1] = -result[1];
 139       if (neg & 0x4) result[2] = -result[2];
 140       if (neg & 0x8) result[3] = -result[3];
 141    }
 142 }
 143
 144 /* Used to implement write masking.  To make things easier for the sse
 145  * generator I've gone back to a 1 argument version of this function
 146  * (dst.msk = arg), rather than the semantically cleaner (dst = SEL
 147  * arg0, arg1, msk)
 148  *
 149  * That means this is the only instruction which doesn't write a full
 150  * 4 dwords out.  This would make such a program harder to analyse,
 151  * but it looks like analysis is going to take place on a higher level
 152  * anyway.
 153  */
 154 static void do_MSK( struct arb_vp_machine *m, union instruction op )
 155 {
 156    GLfloat *dst = m->File[0][op.msk.dst];
 157    const GLfloat *arg = m->File[op.msk.file][op.msk.idx];
 158
 159    if (op.msk.mask & 0x1) dst[0] = arg[0];
 160    if (op.msk.mask & 0x2) dst[1] = arg[1];
 161    if (op.msk.mask & 0x4) dst[2] = arg[2];
 162    if (op.msk.mask & 0x8) dst[3] = arg[3];
 163 }
 164
 165
 166 static void do_PRT( struct arb_vp_machine *m, union instruction op )
 167 {
 168    const GLfloat *arg0 = m->File[op.alu.file0][op.alu.idx0];
 169
 170    _mesa_printf("%d: %f %f %f %f\n", m->vtx_nr,
 171                 arg0[0], arg0[1], arg0[2], arg0[3]);
 172 }
 173
 174
 175 /**
 176  * The traditional ALU and texturing instructions.  All operate on
 177  * internal registers and ignore write masks and swizzling issues.
 178  */
 179
 180 static void do_ABS( struct arb_vp_machine *m, union instruction op )
 181 {
 182    GLfloat *result = m->File[0][op.alu.dst];
 183    const GLfloat *arg0 = m->File[op.alu.file0][op.alu.idx0];
 184
 185    result[0] = (arg0[0] < 0.0) ? -arg0[0] : arg0[0];
 186    result[1] = (arg0[1] < 0.0) ? -arg0[1] : arg0[1];
 187    result[2] = (arg0[2] < 0.0) ? -arg0[2] : arg0[2];
 188    result[3] = (arg0[3] < 0.0) ? -arg0[3] : arg0[3];
 189 }
 190
 191 static void do_ADD( struct arb_vp_machine *m, union instruction op )
 192 {
 193    GLfloat *result = m->File[0][op.alu.dst];
 194    const GLfloat *arg0 = m->File[op.alu.file0][op.alu.idx0];
 195    const GLfloat *arg1 = m->File[op.alu.file1][op.alu.idx1];
 196
 197    result[0] = arg0[0] + arg1[0];
 198    result[1] = arg0[1] + arg1[1];
 199    result[2] = arg0[2] + arg1[2];
 200    result[3] = arg0[3] + arg1[3];
 201 }
 202
 203
 204 static void do_DP3( struct arb_vp_machine *m, union instruction op )
 205 {
 206    GLfloat *result = m->File[0][op.alu.dst];
 207    const GLfloat *arg0 = m->File[op.alu.file0][op.alu.idx0];
 208    const GLfloat *arg1 = m->File[op.alu.file1][op.alu.idx1];
 209
 210    result[0] = (arg0[0] * arg1[0] +
 211                 arg0[1] * arg1[1] +
 212                 arg0[2] * arg1[2]);
 213
 214    PUFF(result);
 215 }
 216
 217
 218
 219 static void do_DP4( struct arb_vp_machine *m, union instruction op )
 220 {
 221    GLfloat *result = m->File[0][op.alu.dst];
 222    const GLfloat *arg0 = m->File[op.alu.file0][op.alu.idx0];
 223    const GLfloat *arg1 = m->File[op.alu.file1][op.alu.idx1];
 224
 225    result[0] = (arg0[0] * arg1[0] +
 226                 arg0[1] * arg1[1] +
 227                 arg0[2] * arg1[2] +
 228                 arg0[3] * arg1[3]);
 229
 230    PUFF(result);
 231 }
 232
 233 static void do_DPH( struct arb_vp_machine *m, union instruction op )
 234 {
 235    GLfloat *result = m->File[0][op.alu.dst];
 236    const GLfloat *arg0 = m->File[op.alu.file0][op.alu.idx0];
 237    const GLfloat *arg1 = m->File[op.alu.file1][op.alu.idx1];
 238
 239    result[0] = (arg0[0] * arg1[0] +
 240                 arg0[1] * arg1[1] +
 241                 arg0[2] * arg1[2] +
 242                 1.0     * arg1[3]);
 243
 244    PUFF(result);
 245 }
 246
 247 static void do_DST( struct arb_vp_machine *m, union instruction op )
 248 {
 249    GLfloat *result = m->File[0][op.alu.dst];
 250    const GLfloat *arg0 = m->File[op.alu.file0][op.alu.idx0];
 251    const GLfloat *arg1 = m->File[op.alu.file1][op.alu.idx1];
 252
 253    result[0] = 1.0F;
 254    result[1] = arg0[1] * arg1[1];
 255    result[2] = arg0[2];
 256    result[3] = arg1[3];
 257 }
 258
 259
 260 /* Intended to be high precision:
 261  */
 262 static void do_EX2( struct arb_vp_machine *m, union instruction op )
 263 {
 264    GLfloat *result = m->File[0][op.alu.dst];
 265    const GLfloat *arg0 = m->File[op.alu.file0][op.alu.idx0];
 266
 267    result[0] = (GLfloat)ApproxExp2(arg0[0]);
 268    PUFF(result);
 269 }
 270
 271
 272 /* Allowed to be lower precision:
 273  */
 274 static void do_EXP( struct arb_vp_machine *m, union instruction op )
 275 {
 276    GLfloat *result = m->File[0][op.alu.dst];
 277    const GLfloat *arg0 = m->File[op.alu.file0][op.alu.idx0];
 278    GLfloat tmp = arg0[0];
 279    GLfloat flr_tmp = FLOORF(tmp);
 280    GLfloat frac_tmp = tmp - flr_tmp;
 281
 282    result[0] = LDEXPF(1.0, (int)flr_tmp);
 283    result[1] = frac_tmp;
 284    result[2] = LDEXPF(rough_approx_log2_0_1(frac_tmp), (int)flr_tmp);
 285    result[3] = 1.0F;
 286 }
 287
 288 static void do_FLR( struct arb_vp_machine *m, union instruction op )
 289 {
 290    GLfloat *result = m->File[0][op.alu.dst];
 291    const GLfloat *arg0 = m->File[op.alu.file0][op.alu.idx0];
 292
 293    result[0] = FLOORF(arg0[0]);
 294    result[1] = FLOORF(arg0[1]);
 295    result[2] = FLOORF(arg0[2]);
 296    result[3] = FLOORF(arg0[3]);
 297 }
 298
 299 static void do_FRC( struct arb_vp_machine *m, union instruction op )
 300 {
 301    GLfloat *result = m->File[0][op.alu.dst];
 302    const GLfloat *arg0 = m->File[op.alu.file0][op.alu.idx0];
 303
 304    result[0] = arg0[0] - FLOORF(arg0[0]);
 305    result[1] = arg0[1] - FLOORF(arg0[1]);
 306    result[2] = arg0[2] - FLOORF(arg0[2]);
 307    result[3] = arg0[3] - FLOORF(arg0[3]);
 308 }
 309
 310 /* High precision log base 2:
 311  */
 312 static void do_LG2( struct arb_vp_machine *m, union instruction op )
 313 {
 314    GLfloat *result = m->File[0][op.alu.dst];
 315    const GLfloat *arg0 = m->File[op.alu.file0][op.alu.idx0];
 316
 317    result[0] = ApproxLog2(arg0[0]);
 318    PUFF(result);
 319 }
 320
 321
 322
 323 static void do_LIT( struct arb_vp_machine *m, union instruction op )
 324 {
 325    GLfloat *result = m->File[0][op.alu.dst];
 326    const GLfloat *arg0 = m->File[op.alu.file0][op.alu.idx0];
 327    GLfloat tmp[4];
 328
 329    tmp[0] = 1.0;
 330    tmp[1] = 0.0;
 331    tmp[2] = 0.0;
 332    tmp[3] = 1.0;
 333
 334    if (arg0[0] > 0.0) {
 335       tmp[1] = arg0[0];
 336
 337       if (arg0[1] > 0.0) {
 338          tmp[2] = RoughApproxPower(arg0[1], arg0[3]);
 339       }
 340    }
 341
 342    COPY_4V(result, tmp);
 343 }
 344
 345
 346 /* Intended to allow a lower precision than required for LG2 above.
 347  */
 348 static void do_LOG( struct arb_vp_machine *m, union instruction op )
 349 {
 350    GLfloat *result = m->File[0][op.alu.dst];
 351    const GLfloat *arg0 = m->File[op.alu.file0][op.alu.idx0];
 352    GLfloat tmp = FABSF(arg0[0]);
 353    int exponent;
 354    GLfloat mantissa = FREXPF(tmp, &exponent);
 355
 356    result[0] = (GLfloat) (exponent - 1);
 357    result[1] = 2.0 * mantissa; /* map [.5, 1) -> [1, 2) */
 358    result[2] = exponent + LOG2(mantissa);
 359    result[3] = 1.0;
 360 }
 361
 362 static void do_MAX( struct arb_vp_machine *m, union instruction op )
 363 {
 364    GLfloat *result = m->File[0][op.alu.dst];
 365    const GLfloat *arg0 = m->File[op.alu.file0][op.alu.idx0];
 366    const GLfloat *arg1 = m->File[op.alu.file1][op.alu.idx1];
 367
 368    result[0] = (arg0[0] > arg1[0]) ? arg0[0] : arg1[0];
 369    result[1] = (arg0[1] > arg1[1]) ? arg0[1] : arg1[1];
 370    result[2] = (arg0[2] > arg1[2]) ? arg0[2] : arg1[2];
 371    result[3] = (arg0[3] > arg1[3]) ? arg0[3] : arg1[3];
 372 }
 373
 374
 375 static void do_MIN( struct arb_vp_machine *m, union instruction op )
 376 {
 377    GLfloat *result = m->File[0][op.alu.dst];
 378    const GLfloat *arg0 = m->File[op.alu.file0][op.alu.idx0];
 379    const GLfloat *arg1 = m->File[op.alu.file1][op.alu.idx1];
 380
 381    result[0] = (arg0[0] < arg1[0]) ? arg0[0] : arg1[0];
 382    result[1] = (arg0[1] < arg1[1]) ? arg0[1] : arg1[1];
 383    result[2] = (arg0[2] < arg1[2]) ? arg0[2] : arg1[2];
 384    result[3] = (arg0[3] < arg1[3]) ? arg0[3] : arg1[3];
 385 }
 386
 387 static void do_MOV( struct arb_vp_machine *m, union instruction op )
 388 {
 389    GLfloat *result = m->File[0][op.alu.dst];
 390    const GLfloat *arg0 = m->File[op.alu.file0][op.alu.idx0];
 391
 392    result[0] = arg0[0];
 393    result[1] = arg0[1];
 394    result[2] = arg0[2];
 395    result[3] = arg0[3];
 396 }
 397
 398 static void do_MUL( struct arb_vp_machine *m, union instruction op )
 399 {
 400    GLfloat *result = m->File[0][op.alu.dst];
 401    const GLfloat *arg0 = m->File[op.alu.file0][op.alu.idx0];
 402    const GLfloat *arg1 = m->File[op.alu.file1][op.alu.idx1];
 403
 404    result[0] = arg0[0] * arg1[0];
 405    result[1] = arg0[1] * arg1[1];
 406    result[2] = arg0[2] * arg1[2];
 407    result[3] = arg0[3] * arg1[3];
 408 }
 409
 410
 411 /* Intended to be "high" precision
 412  */
 413 static void do_POW( struct arb_vp_machine *m, union instruction op )
 414 {
 415    GLfloat *result = m->File[0][op.alu.dst];
 416    const GLfloat *arg0 = m->File[op.alu.file0][op.alu.idx0];
 417    const GLfloat *arg1 = m->File[op.alu.file1][op.alu.idx1];
 418
 419    result[0] = (GLfloat)ApproxPower(arg0[0], arg1[0]);
 420    PUFF(result);
 421 }
 422
 423 static void do_REL( struct arb_vp_machine *m, union instruction op )
 424 {
 425    GLfloat *result = m->File[0][op.alu.dst];
 426    GLuint idx = (op.alu.idx0 + (GLint)m->File[0][REG_ADDR][0]) & (MAX_NV_VERTEX_PROGRAM_PARAMS-1);
 427    const GLfloat *arg0 = m->File[op.alu.file0][idx];
 428
 429    result[0] = arg0[0];
 430    result[1] = arg0[1];
 431    result[2] = arg0[2];
 432    result[3] = arg0[3];
 433 }
 434
 435 static void do_RCP( struct arb_vp_machine *m, union instruction op )
 436 {
 437    GLfloat *result = m->File[0][op.alu.dst];
 438    const GLfloat *arg0 = m->File[op.alu.file0][op.alu.idx0];
 439
 440    result[0] = 1.0F / arg0[0];
 441    PUFF(result);
 442 }
 443
 444 static void do_RSQ( struct arb_vp_machine *m, union instruction op )
 445 {
 446    GLfloat *result = m->File[0][op.alu.dst];
 447    const GLfloat *arg0 = m->File[op.alu.file0][op.alu.idx0];
 448
 449    result[0] = INV_SQRTF(FABSF(arg0[0]));
 450    PUFF(result);
 451 }
 452
 453
 454 static void do_SGE( struct arb_vp_machine *m, union instruction op )
 455 {
 456    GLfloat *result = m->File[0][op.alu.dst];
 457    const GLfloat *arg0 = m->File[op.alu.file0][op.alu.idx0];
 458    const GLfloat *arg1 = m->File[op.alu.file1][op.alu.idx1];
 459
 460    result[0] = (arg0[0] >= arg1[0]) ? 1.0F : 0.0F;
 461    result[1] = (arg0[1] >= arg1[1]) ? 1.0F : 0.0F;
 462    result[2] = (arg0[2] >= arg1[2]) ? 1.0F : 0.0F;
 463    result[3] = (arg0[3] >= arg1[3]) ? 1.0F : 0.0F;
 464 }
 465
 466
 467 static void do_SLT( struct arb_vp_machine *m, union instruction op )
 468 {
 469    GLfloat *result = m->File[0][op.alu.dst];
 470    const GLfloat *arg0 = m->File[op.alu.file0][op.alu.idx0];
 471    const GLfloat *arg1 = m->File[op.alu.file1][op.alu.idx1];
 472
 473    result[0] = (arg0[0] < arg1[0]) ? 1.0F : 0.0F;
 474    result[1] = (arg0[1] < arg1[1]) ? 1.0F : 0.0F;
 475    result[2] = (arg0[2] < arg1[2]) ? 1.0F : 0.0F;
 476    result[3] = (arg0[3] < arg1[3]) ? 1.0F : 0.0F;
 477 }
 478
 479 static void do_SUB( struct arb_vp_machine *m, union instruction op )
 480 {
 481    GLfloat *result = m->File[0][op.alu.dst];
 482    const GLfloat *arg0 = m->File[op.alu.file0][op.alu.idx0];
 483    const GLfloat *arg1 = m->File[op.alu.file1][op.alu.idx1];
 484
 485    result[0] = arg0[0] - arg1[0];
 486    result[1] = arg0[1] - arg1[1];
 487    result[2] = arg0[2] - arg1[2];
 488    result[3] = arg0[3] - arg1[3];
 489 }
 490
 491
 492 static void do_XPD( struct arb_vp_machine *m, union instruction op )
 493 {
 494    GLfloat *result = m->File[0][op.alu.dst];
 495    const GLfloat *arg0 = m->File[op.alu.file0][op.alu.idx0];
 496    const GLfloat *arg1 = m->File[op.alu.file1][op.alu.idx1];
 497
 498    result[0] = arg0[1] * arg1[2] - arg0[2] * arg1[1];
 499    result[1] = arg0[2] * arg1[0] - arg0[0] * arg1[2];
 500    result[2] = arg0[0] * arg1[1] - arg0[1] * arg1[0];
 501 }
 502
 503 static void do_NOP( struct arb_vp_machine *m, union instruction op )
 504 {
 505 }
 506
 507 /* Some useful debugging functions:
 508  */
 509 static void print_mask( GLuint mask )
 510 {
 511    _mesa_printf(".");
 512    if (mask&0x1) _mesa_printf("x");
 513    if (mask&0x2) _mesa_printf("y");
 514    if (mask&0x4) _mesa_printf("z");
 515    if (mask&0x8) _mesa_printf("w");
 516 }
 517
 518 static void print_reg( GLuint file, GLuint reg )
 519 {
 520    static const char *reg_file[] = {
 521       "REG",
 522       "LOCAL_PARAM",
 523       "ENV_PARAM",
 524       "STATE_VAR",
 525    };
 526
 527    if (file == 0) {
 528       if (reg == REG_RES)
 529          _mesa_printf("RES");
 530       else if (reg >= REG_ARG0 && reg <= REG_ARG1)
 531          _mesa_printf("ARG%d", reg - REG_ARG0);
 532       else if (reg >= REG_TMP0 && reg <= REG_TMP11)
 533          _mesa_printf("TMP%d", reg - REG_TMP0);
 534       else if (reg >= REG_IN0 && reg <= REG_IN31)
 535          _mesa_printf("IN%d", reg - REG_IN0);
 536       else if (reg >= REG_OUT0 && reg <= REG_OUT14)
 537          _mesa_printf("OUT%d", reg - REG_OUT0);
 538       else if (reg == REG_ADDR)
 539          _mesa_printf("ADDR");
 540       else if (reg == REG_ID)
 541          _mesa_printf("ID");
 542       else
 543          _mesa_printf("REG%d", reg);
 544    }
 545    else
 546       _mesa_printf("%s:%d", reg_file[file], reg);
 547 }
 548
 549
 550 static void print_RSW( union instruction op, const struct opcode_info *info )
 551 {
 552    GLuint swz = op.rsw.swz;
 553    GLuint neg = op.rsw.neg;
 554    GLuint i;
 555
 556    _mesa_printf("%s ", info->string);
 557    print_reg(0, op.rsw.dst);
 558    _mesa_printf(", ");
 559    print_reg(op.rsw.file0, op.rsw.idx0);
 560    _mesa_printf(".");
 561    for (i = 0; i < 4; i++, swz >>= 2) {
 562       const char *cswz = "xyzw";
 563       if (neg & (1<<i))
 564          _mesa_printf("-");
 565       _mesa_printf("%c", cswz[swz&0x3]);
 566    }
 567    _mesa_printf("\n");
 568 }
 569
 570
 571 static void print_ALU( union instruction op, const struct opcode_info *info )
 572 {
 573    _mesa_printf("%s ", info->string);
 574    print_reg(0, op.alu.dst);
 575    _mesa_printf(", ");
 576    print_reg(op.alu.file0, op.alu.idx0);
 577    if (info->nr_args > 1) {
 578       _mesa_printf(", ");
 579       print_reg(op.alu.file1, op.alu.idx1);
 580    }
 581    _mesa_printf("\n");
 582 }
 583
 584 static void print_MSK( union instruction op, const struct opcode_info *info )
 585 {
 586    _mesa_printf("%s ", info->string);
 587    print_reg(0, op.msk.dst);
 588    print_mask(op.msk.mask);
 589    _mesa_printf(", ");
 590    print_reg(op.msk.file, op.msk.idx);
 591    _mesa_printf("\n");
 592 }
 593
 594
 595 static void print_NOP( union instruction op, const struct opcode_info *info )
 596 {
 597 }
 598
 599 #define NOP 0
 600 #define ALU 1
 601 #define SWZ 2
 602
 603 static const struct opcode_info opcode_info[] =
 604 {
 605    { 1, "ABS", print_ALU },
 606    { 2, "ADD", print_ALU },
 607    { 1, "ARL", print_NOP },
 608    { 2, "DP3", print_ALU },
 609    { 2, "DP4", print_ALU },
 610    { 2, "DPH", print_ALU },
 611    { 2, "DST", print_ALU },
 612    { 0, "END", print_NOP },
 613    { 1, "EX2", print_ALU },
 614    { 1, "EXP", print_ALU },
 615    { 1, "FLR", print_ALU },
 616    { 1, "FRC", print_ALU },
 617    { 1, "LG2", print_ALU },
 618    { 1, "LIT", print_ALU },
 619    { 1, "LOG", print_ALU },
 620    { 3, "MAD", print_NOP },
 621    { 2, "MAX", print_ALU },
 622    { 2, "MIN", print_ALU },
 623    { 1, "MOV", print_ALU },
 624    { 2, "MUL", print_ALU },
 625    { 2, "POW", print_ALU },
 626    { 1, "PRT", print_ALU }, /* PRINT */
 627    { 1, "RCC", print_NOP },
 628    { 1, "RCP", print_ALU },
 629    { 1, "RSQ", print_ALU },
 630    { 2, "SGE", print_ALU },
 631    { 2, "SLT", print_ALU },
 632    { 2, "SUB", print_ALU },
 633    { 1, "SWZ", print_NOP },
 634    { 2, "XPD", print_ALU },
 635    { 1, "RSW", print_RSW },
 636    { 2, "MSK", print_MSK },
 637    { 1, "REL", print_ALU },
 638 };
 639
 640 void _tnl_disassem_vba_insn( union instruction op )
 641 {
 642    const struct opcode_info *info = &opcode_info[op.alu.opcode];
 643    info->print( op, info );
 644 }
 645
 646
 647 static void (* const opcode_func[])(struct arb_vp_machine *, union instruction) =
 648 {
 649    do_ABS,
 650    do_ADD,
 651    do_NOP,
 652    do_DP3,
 653    do_DP4,
 654    do_DPH,
 655    do_DST,
 656    do_NOP,
 657    do_EX2,
 658    do_EXP,
 659    do_FLR,
 660    do_FRC,
 661    do_LG2,
 662    do_LIT,
 663    do_LOG,
 664    do_NOP,
 665    do_MAX,
 666    do_MIN,
 667    do_MOV,
 668    do_MUL,
 669    do_POW,
 670    do_PRT,
 671    do_NOP,
 672    do_RCP,
 673    do_RSQ,
 674    do_SGE,
 675    do_SLT,
 676    do_SUB,
 677    do_RSW,
 678    do_XPD,
 679    do_RSW,
 680    do_MSK,
 681    do_REL,
 682 };
 683
 684 static union instruction *cvp_next_instruction( struct compilation *cp )
 685 {
 686    union instruction *op = cp->csr++;
 687    op->dword = 0;
 688    return op;
 689 }
 690
 691 static struct reg cvp_make_reg( GLuint file, GLuint idx )
 692 {
 693    struct reg reg;
 694    reg.file = file;
 695    reg.idx = idx;
 696    return reg;
 697 }
 698
 699 static struct reg cvp_emit_rel( struct compilation *cp,
 700                                 struct reg reg,
 701                                 struct reg tmpreg )
 702 {
 703    union instruction *op = cvp_next_instruction(cp);
 704    op->alu.opcode = REL;
 705    op->alu.file0 = reg.file;
 706    op->alu.idx0 = reg.idx;
 707    op->alu.dst = tmpreg.idx;
 708    return tmpreg;
 709 }
 710
 711
 712 static struct reg cvp_load_reg( struct compilation *cp,
 713                                 GLuint file,
 714                                 GLuint index,
 715                                 GLuint rel,
 716                                 GLuint tmpidx )
 717 {
 718    struct reg tmpreg = cvp_make_reg(FILE_REG, tmpidx);
 719    struct reg reg;
 720
 721    switch (file) {
 722    case PROGRAM_TEMPORARY:
 723       return cvp_make_reg(FILE_REG, REG_TMP0 + index);
 724
 725    case PROGRAM_INPUT:
 726       return cvp_make_reg(FILE_REG, REG_IN0 + index);
 727
 728    case PROGRAM_OUTPUT:
 729       return cvp_make_reg(FILE_REG, REG_OUT0 + index);
 730
 731       /* These two aren't populated by the parser?
 732        */
 733    case PROGRAM_LOCAL_PARAM:
 734       reg = cvp_make_reg(FILE_LOCAL_PARAM, index);
 735       if (rel)
 736          return cvp_emit_rel(cp, reg, tmpreg);
 737       else
 738          return reg;
 739
 740    case PROGRAM_ENV_PARAM:
 741       reg = cvp_make_reg(FILE_ENV_PARAM, index);
 742       if (rel)
 743          return cvp_emit_rel(cp, reg, tmpreg);
 744       else
 745          return reg;
 746
 747    case PROGRAM_STATE_VAR:
 748       reg = cvp_make_reg(FILE_STATE_PARAM, index);
 749       if (rel)
 750          return cvp_emit_rel(cp, reg, tmpreg);
 751       else
 752          return reg;
 753
 754       /* Invalid values:
 755        */
 756    case PROGRAM_WRITE_ONLY:
 757    case PROGRAM_ADDRESS:
 758    default:
 759       assert(0);
 760       return tmpreg;            /* can't happen */
 761    }
 762 }
 763
 764 static struct reg cvp_emit_arg( struct compilation *cp,
 765                                 const struct vp_src_register *src,
 766                                 GLuint arg )
 767 {
 768    struct reg reg = cvp_load_reg( cp, src->File, src->Index, src->RelAddr, arg );
 769    union instruction rsw, noop;
 770
 771    /* Emit any necessary swizzling.
 772     */
 773    rsw.dword = 0;
 774    rsw.rsw.neg = src->Negate ? WRITEMASK_XYZW : 0;
 775    rsw.rsw.swz = ((GET_SWZ(src->Swizzle, 0) << 0) |
 776                   (GET_SWZ(src->Swizzle, 1) << 2) |
 777                   (GET_SWZ(src->Swizzle, 2) << 4) |
 778                   (GET_SWZ(src->Swizzle, 3) << 6));
 779
 780    noop.dword = 0;
 781    noop.rsw.neg = 0;
 782    noop.rsw.swz = RSW_NOOP;
 783
 784    if (rsw.dword != noop.dword) {
 785       union instruction *op = cvp_next_instruction(cp);
 786       struct reg rsw_reg = cvp_make_reg(FILE_REG, REG_ARG0 + arg);
 787       op->dword = rsw.dword;
 788       op->rsw.opcode = RSW;
 789       op->rsw.file0 = reg.file;
 790       op->rsw.idx0 = reg.idx;
 791       op->rsw.dst = rsw_reg.idx;
 792       return rsw_reg;
 793    }
 794    else
 795       return reg;
 796 }
 797
 798 static GLuint cvp_choose_result( struct compilation *cp,
 799                                  const struct vp_dst_register *dst,
 800                                  union instruction *fixup )
 801 {
 802    GLuint mask = dst->WriteMask;
 803    GLuint idx;
 804
 805    switch (dst->File) {
 806    case PROGRAM_TEMPORARY:
 807       idx = REG_TMP0 + dst->Index;
 808       break;
 809    case PROGRAM_OUTPUT:
 810       idx = REG_OUT0 + dst->Index;
 811       break;
 812    default:
 813       assert(0);
 814       return REG_RES;           /* can't happen */
 815    }
 816
 817    /* Optimization: When writing (with a writemask) to an undefined
 818     * value for the first time, the writemask may be ignored.
 819     */
 820    if (mask != WRITEMASK_XYZW && (cp->reg_active & (1 << idx))) {
 821       fixup->msk.opcode = MSK;
 822       fixup->msk.dst = idx;
 823       fixup->msk.file = FILE_REG;
 824       fixup->msk.idx = REG_RES;
 825       fixup->msk.mask = mask;
 826       cp->reg_active |= 1 << idx;
 827       return REG_RES;
 828    }
 829    else {
 830       fixup->dword = 0;
 831       cp->reg_active |= 1 << idx;
 832       return idx;
 833    }
 834 }
 835
 836 static struct reg cvp_emit_rsw( struct compilation *cp,
 837                                 GLuint dst,
 838                                 struct reg src,
 839                                 GLuint neg,
 840                                 GLuint swz,
 841                                 GLboolean force)
 842 {
 843    struct reg retval;
 844
 845    if (swz != RSW_NOOP || neg != 0) {
 846       union instruction *op = cvp_next_instruction(cp);
 847       op->rsw.opcode = RSW;
 848       op->rsw.dst = dst;
 849       op->rsw.file0 = src.file;
 850       op->rsw.idx0 = src.idx;
 851       op->rsw.neg = neg;
 852       op->rsw.swz = swz;
 853
 854       retval.file = FILE_REG;
 855       retval.idx = dst;
 856       return retval;
 857    }
 858    else if (force) {
 859       /* Oops.  Degenerate case:
 860        */
 861       union instruction *op = cvp_next_instruction(cp);
 862       op->alu.opcode = VP_OPCODE_MOV;
 863       op->alu.dst = dst;
 864       op->alu.file0 = src.file;
 865       op->alu.idx0 = src.idx;
 866
 867       retval.file = FILE_REG;
 868       retval.idx = dst;
 869       return retval;
 870    }
 871    else {
 872       return src;
 873    }
 874 }
 875
 876
 877 static void cvp_emit_inst( struct compilation *cp,
 878                            const struct vp_instruction *inst )
 879 {
 880    const struct opcode_info *info = &opcode_info[inst->Opcode];
 881    union instruction *op;
 882    union instruction fixup;
 883    struct reg reg[3];
 884    GLuint result, i;
 885
 886    assert(sizeof(*op) == sizeof(GLuint));
 887
 888    /* Need to handle SWZ, ARL specially.
 889     */
 890    switch (inst->Opcode) {
 891       /* Split into mul and add:
 892        */
 893    case VP_OPCODE_MAD:
 894       result = cvp_choose_result( cp, &inst->DstReg, &fixup );
 895       for (i = 0; i < 3; i++)
 896          reg[i] = cvp_emit_arg( cp, &inst->SrcReg[i], REG_ARG0+i );
 897
 898       op = cvp_next_instruction(cp);
 899       op->alu.opcode = VP_OPCODE_MUL;
 900       op->alu.file0 = reg[0].file;
 901       op->alu.idx0 = reg[0].idx;
 902       op->alu.file1 = reg[1].file;
 903       op->alu.idx1 = reg[1].idx;
 904       op->alu.dst = REG_ARG0;
 905
 906       op = cvp_next_instruction(cp);
 907       op->alu.opcode = VP_OPCODE_ADD;
 908       op->alu.file0 = FILE_REG;
 909       op->alu.idx0 = REG_ARG0;
 910       op->alu.file1 = reg[2].file;
 911       op->alu.idx1 = reg[2].idx;
 912       op->alu.dst = result;
 913
 914       if (result == REG_RES) {
 915          op = cvp_next_instruction(cp);
 916          op->dword = fixup.dword;
 917       }
 918       break;
 919
 920    case VP_OPCODE_ARL:
 921       reg[0] = cvp_emit_arg( cp, &inst->SrcReg[0], REG_ARG0 );
 922
 923       op = cvp_next_instruction(cp);
 924       op->alu.opcode = VP_OPCODE_FLR;
 925       op->alu.dst = REG_ADDR;
 926       op->alu.file0 = reg[0].file;
 927       op->alu.idx0 = reg[0].idx;
 928       break;
 929
 930    case VP_OPCODE_SWZ: {
 931       GLuint swz0 = 0, swz1 = 0;
 932       GLuint neg0 = 0, neg1 = 0;
 933       GLuint mask = 0;
 934
 935       /* Translate 3-bit-per-element swizzle into two 2-bit swizzles,
 936        * one from the source register the other from a constant
 937        * {0,0,0,1}.
 938        */
 939       for (i = 0; i < 4; i++) {
 940          GLuint swzelt = GET_SWZ(inst->SrcReg[0].Swizzle, i);
 941          if (swzelt >= SWIZZLE_ZERO) {
 942             neg0 |= inst->SrcReg[0].Negate & (1<<i);
 943             if (swzelt == SWIZZLE_ONE)
 944                swz0 |= SWIZZLE_W << (i*2);
 945             else if (i < SWIZZLE_W)
 946                swz0 |= i << (i*2);
 947          }
 948          else {
 949             mask |= 1<<i;
 950             neg1 |= inst->SrcReg[0].Negate & (1<<i);
 951             swz1 |= swzelt << (i*2);
 952          }
 953       }
 954
 955       result = cvp_choose_result( cp, &inst->DstReg, &fixup );
 956       reg[0].file = FILE_REG;
 957       reg[0].idx = REG_ID;
 958       reg[1] = cvp_emit_arg( cp, &inst->SrcReg[0], REG_ARG0 );
 959
 960       if (mask == WRITEMASK_XYZW) {
 961          cvp_emit_rsw(cp, result, reg[0], neg0, swz0, GL_TRUE);
 962
 963       }
 964       else if (mask == 0) {
 965          cvp_emit_rsw(cp, result, reg[1], neg1, swz1, GL_TRUE);
 966       }
 967       else {
 968          cvp_emit_rsw(cp, result, reg[0], neg0, swz0, GL_TRUE);
 969          reg[1] = cvp_emit_rsw(cp, REG_ARG0, reg[1], neg1, swz1, GL_FALSE);
 970
 971          op = cvp_next_instruction(cp);
 972          op->msk.opcode = MSK;
 973          op->msk.dst = result;
 974          op->msk.file = reg[1].file;
 975          op->msk.idx = reg[1].idx;
 976          op->msk.mask = mask;
 977       }
 978
 979       if (result == REG_RES) {
 980          op = cvp_next_instruction(cp);
 981          op->dword = fixup.dword;
 982       }
 983       break;
 984    }
 985
 986    case VP_OPCODE_END:
 987       break;
 988
 989    default:
 990       result = cvp_choose_result( cp, &inst->DstReg, &fixup );
 991       for (i = 0; i < info->nr_args; i++)
 992          reg[i] = cvp_emit_arg( cp, &inst->SrcReg[i], REG_ARG0 + i );
 993
 994       op = cvp_next_instruction(cp);
 995       op->alu.opcode = inst->Opcode;
 996       op->alu.file0 = reg[0].file;
 997       op->alu.idx0 = reg[0].idx;
 998       op->alu.file1 = reg[1].file;
 999       op->alu.idx1 = reg[1].idx;
1000       op->alu.dst = result;
1001
1002       if (result == REG_RES) {
1003          op = cvp_next_instruction(cp);
1004          op->dword = fixup.dword;
1005       }
1006       break;
1007    }
1008 }
1009
1010 static void free_tnl_data( struct vertex_program *program  )
1011 {
1012    struct tnl_compiled_program *p = program->TnlData;
1013    if (p->compiled_func)
1014       _mesa_free((void *)p->compiled_func);
1015    _mesa_free(p);
1016    program->TnlData = NULL;
1017 }
1018
1019 static void compile_vertex_program( struct vertex_program *program,
1020                                     GLboolean try_codegen )
1021 {
1022    struct compilation cp;
1023    struct tnl_compiled_program *p = CALLOC_STRUCT(tnl_compiled_program);
1024    GLuint i;
1025
1026    if (program->TnlData)
1027       free_tnl_data( program );
1028
1029    program->TnlData = p;
1030
1031    /* Initialize cp.  Note that ctx and VB aren't used in compilation
1032     * so we don't have to worry about statechanges:
1033     */
1034    memset(&cp, 0, sizeof(cp));
1035    cp.csr = p->instructions;
1036
1037    /* Compile instructions:
1038     */
1039    for (i = 0; i < program->Base.NumInstructions; i++) {
1040       cvp_emit_inst(&cp, &program->Instructions[i]);
1041    }
1042
1043    /* Finish up:
1044     */
1045    p->nr_instructions = cp.csr - p->instructions;
1046
1047    /* Print/disassemble:
1048     */
1049    if (DISASSEM) {
1050       for (i = 0; i < p->nr_instructions; i++) {
1051          _tnl_disassem_vba_insn(p->instructions[i]);
1052       }
1053       _mesa_printf("\n\n");
1054    }
1055
1056 #ifdef USE_SSE_ASM
1057    if (try_codegen)
1058       _tnl_sse_codegen_vertex_program(p);
1059 #endif
1060
1061 }
1062
1063
1064
1065
1066 /* ----------------------------------------------------------------------
1067  * Execution
1068  */
1069 static void userclip( GLcontext *ctx,
1070                       GLvector4f *clip,
1071                       GLubyte *clipmask,
1072                       GLubyte *clipormask,
1073                       GLubyte *clipandmask )
1074 {
1075    GLuint p;
1076
1077    for (p = 0; p < ctx->Const.MaxClipPlanes; p++) {
1078       if (ctx->Transform.ClipPlanesEnabled & (1 << p)) {
1079          GLuint nr, i;
1080          const GLfloat a = ctx->Transform._ClipUserPlane[p][0];
1081          const GLfloat b = ctx->Transform._ClipUserPlane[p][1];
1082          const GLfloat c = ctx->Transform._ClipUserPlane[p][2];
1083          const GLfloat d = ctx->Transform._ClipUserPlane[p][3];
1084          GLfloat *coord = (GLfloat *)clip->data;
1085          GLuint stride = clip->stride;
1086          GLuint count = clip->count;
1087
1088          for (nr = 0, i = 0 ; i < count ; i++) {
1089             GLfloat dp = (coord[0] * a +
1090                           coord[1] * b +
1091                           coord[2] * c +
1092                           coord[3] * d);
1093
1094             if (dp < 0) {
1095                nr++;
1096                clipmask[i] |= CLIP_USER_BIT;
1097             }
1098
1099             STRIDE_F(coord, stride);
1100          }
1101
1102          if (nr > 0) {
1103             *clipormask |= CLIP_USER_BIT;
1104             if (nr == count) {
1105                *clipandmask |= CLIP_USER_BIT;
1106                return;
1107             }
1108          }
1109       }
1110    }
1111 }
1112
1113
1114 static GLboolean do_ndc_cliptest( struct arb_vp_machine *m )
1115 {
1116    GLcontext *ctx = m->ctx;
1117    TNLcontext *tnl = TNL_CONTEXT(ctx);
1118    struct vertex_buffer *VB = m->VB;
1119
1120    /* Cliptest and perspective divide.  Clip functions must clear
1121     * the clipmask.
1122     */
1123    m->ormask = 0;
1124    m->andmask = CLIP_ALL_BITS;
1125
1126    if (tnl->NeedNdcCoords) {
1127       VB->NdcPtr =
1128          _mesa_clip_tab[VB->ClipPtr->size]( VB->ClipPtr,
1129                                             &m->ndcCoords,
1130                                             m->clipmask,
1131                                             &m->ormask,
1132                                             &m->andmask );
1133    }
1134    else {
1135       VB->NdcPtr = NULL;
1136       _mesa_clip_np_tab[VB->ClipPtr->size]( VB->ClipPtr,
1137                                             NULL,
1138                                             m->clipmask,
1139                                             &m->ormask,
1140                                             &m->andmask );
1141    }
1142
1143    if (m->andmask) {
1144       /* All vertices are outside the frustum */
1145       return GL_FALSE;
1146    }
1147
1148    /* Test userclip planes.  This contributes to VB->ClipMask.
1149     */
1150    if (ctx->Transform.ClipPlanesEnabled && !ctx->VertexProgram._Enabled) {
1151       userclip( ctx,
1152                 VB->ClipPtr,
1153                 m->clipmask,
1154                 &m->ormask,
1155                 &m->andmask );
1156
1157       if (m->andmask) {
1158          return GL_FALSE;
1159       }
1160    }
1161
1162    VB->ClipAndMask = m->andmask;
1163    VB->ClipOrMask = m->ormask;
1164    VB->ClipMask = m->clipmask;
1165
1166    return GL_TRUE;
1167 }
1168
1169
1170 static INLINE void call_func( struct tnl_compiled_program *p,
1171                               struct arb_vp_machine *m )
1172 {
1173    p->compiled_func(m);
1174 }
1175
1176 /**
1177  * Execute the given vertex program.
1178  *
1179  * TODO: Integrate the t_vertex.c code here, to build machine vertices
1180  * directly at this point.
1181  *
1182  * TODO: Eliminate the VB struct entirely and just use
1183  * struct arb_vertex_machine.
1184  */
1185 static GLboolean
1186 run_arb_vertex_program(GLcontext *ctx, struct tnl_pipeline_stage *stage)
1187 {
1188    struct vertex_program *program = (ctx->VertexProgram._Enabled ?
1189                                      ctx->VertexProgram.Current :
1190                                      ctx->_TnlProgram);
1191    struct vertex_buffer *VB = &TNL_CONTEXT(ctx)->vb;
1192    struct arb_vp_machine *m = ARB_VP_MACHINE(stage);
1193    struct tnl_compiled_program *p;
1194    GLuint i, j, outputs;
1195
1196    if (!program || program->IsNVProgram)
1197       return GL_TRUE;
1198
1199    if (program->Parameters) {
1200       _mesa_load_state_parameters(ctx, program->Parameters);
1201    }
1202
1203    p = (struct tnl_compiled_program *)program->TnlData;
1204    assert(p);
1205
1206
1207    m->nr_inputs = m->nr_outputs = 0;
1208
1209    for (i = 0; i < _TNL_ATTRIB_MAX; i++) {
1210       if (program->InputsRead & (1<<i)) {
1211          GLuint j = m->nr_inputs++;
1212          m->input[j].idx = i;
1213          m->input[j].data = (GLfloat *)m->VB->AttribPtr[i]->data;
1214          m->input[j].stride = m->VB->AttribPtr[i]->stride;
1215          m->input[j].size = m->VB->AttribPtr[i]->size;
1216          ASSIGN_4V(m->File[0][REG_IN0 + i], 0, 0, 0, 1);
1217       }
1218    }
1219
1220    for (i = 0; i < 15; i++) {
1221       if (program->OutputsWritten & (1<<i)) {
1222          GLuint j = m->nr_outputs++;
1223          m->output[j].idx = i;
1224          m->output[j].data = (GLfloat *)m->attribs[i].data;
1225       }
1226    }
1227
1228
1229    /* Run the actual program:
1230     */
1231    for (m->vtx_nr = 0; m->vtx_nr < VB->Count; m->vtx_nr++) {
1232       for (j = 0; j < m->nr_inputs; j++) {
1233          GLuint idx = REG_IN0 + m->input[j].idx;
1234          switch (m->input[j].size) {
1235          case 4: m->File[0][idx][3] = m->input[j].data[3];
1236          case 3: m->File[0][idx][2] = m->input[j].data[2];
1237          case 2: m->File[0][idx][1] = m->input[j].data[1];
1238          case 1: m->File[0][idx][0] = m->input[j].data[0];
1239          }
1240
1241          STRIDE_F(m->input[j].data, m->input[j].stride);
1242       }
1243
1244       if (p->compiled_func) {
1245          call_func( p, m );
1246       }
1247       else {
1248          for (j = 0; j < p->nr_instructions; j++) {
1249             union instruction inst = p->instructions[j];
1250             opcode_func[inst.alu.opcode]( m, inst );
1251          }
1252       }
1253
1254       for (j = 0; j < m->nr_outputs; j++) {
1255          GLuint idx = REG_OUT0 + m->output[j].idx;
1256          m->output[j].data[0] = m->File[0][idx][0];
1257          m->output[j].data[1] = m->File[0][idx][1];
1258          m->output[j].data[2] = m->File[0][idx][2];
1259          m->output[j].data[3] = m->File[0][idx][3];
1260          m->output[j].data += 4;
1261       }
1262    }
1263
1264    /* Setup the VB pointers so that the next pipeline stages get
1265     * their data from the right place (the program output arrays).
1266     *
1267     * TODO: 1) Have tnl use these RESULT values for outputs rather
1268     * than trying to shoe-horn inputs and outputs into one set of
1269     * values.
1270     *
1271     * TODO: 2) Integrate t_vertex.c so that we just go straight ahead
1272     * and build machine vertices here.
1273     */
1274    VB->ClipPtr = &m->attribs[VERT_RESULT_HPOS];
1275    VB->ClipPtr->count = VB->Count;
1276
1277    outputs = program->OutputsWritten;
1278
1279    if (outputs & (1<<VERT_RESULT_COL0)) {
1280       VB->ColorPtr[0] = &m->attribs[VERT_RESULT_COL0];
1281       VB->AttribPtr[VERT_ATTRIB_COLOR0] = VB->ColorPtr[0];
1282    }
1283
1284    if (outputs & (1<<VERT_RESULT_BFC0)) {
1285       VB->ColorPtr[1] = &m->attribs[VERT_RESULT_BFC0];
1286    }
1287
1288    if (outputs & (1<<VERT_RESULT_COL1)) {
1289       VB->SecondaryColorPtr[0] = &m->attribs[VERT_RESULT_COL1];
1290       VB->AttribPtr[VERT_ATTRIB_COLOR1] = VB->SecondaryColorPtr[0];
1291    }
1292
1293    if (outputs & (1<<VERT_RESULT_BFC1)) {
1294       VB->SecondaryColorPtr[1] = &m->attribs[VERT_RESULT_BFC1];
1295    }
1296
1297    if (outputs & (1<<VERT_RESULT_FOGC)) {
1298       VB->FogCoordPtr = &m->attribs[VERT_RESULT_FOGC];
1299       VB->AttribPtr[VERT_ATTRIB_FOG] = VB->FogCoordPtr;
1300    }
1301
1302    if (outputs & (1<<VERT_RESULT_PSIZ)) {
1303       VB->PointSizePtr = &m->attribs[VERT_RESULT_PSIZ];
1304       VB->AttribPtr[_TNL_ATTRIB_POINTSIZE] = &m->attribs[VERT_RESULT_PSIZ];
1305    }
1306
1307    for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
1308       if (outputs & (1<<(VERT_RESULT_TEX0+i))) {
1309          VB->TexCoordPtr[i] = &m->attribs[VERT_RESULT_TEX0 + i];
1310          VB->AttribPtr[VERT_ATTRIB_TEX0+i] = VB->TexCoordPtr[i];
1311       }
1312    }
1313
1314 #if 0
1315    for (i = 0; i < VB->Count; i++) {
1316       printf("Out %d: %f %f %f %f %f %f %f %f\n", i,
1317              VEC_ELT(VB->ClipPtr, GLfloat, i)[0],
1318              VEC_ELT(VB->ClipPtr, GLfloat, i)[1],
1319              VEC_ELT(VB->ClipPtr, GLfloat, i)[2],
1320              VEC_ELT(VB->ClipPtr, GLfloat, i)[3],
1321              VEC_ELT(VB->TexCoordPtr[0], GLfloat, i)[0],
1322              VEC_ELT(VB->TexCoordPtr[0], GLfloat, i)[1],
1323              VEC_ELT(VB->TexCoordPtr[0], GLfloat, i)[2],
1324              VEC_ELT(VB->TexCoordPtr[0], GLfloat, i)[3]);
1325    }
1326 #endif
1327
1328    /* Perform NDC and cliptest operations:
1329     */
1330    return do_ndc_cliptest(m);
1331 }
1332
1333
1334 static void
1335 validate_vertex_program( GLcontext *ctx, struct tnl_pipeline_stage *stage )
1336 {
1337    struct arb_vp_machine *m = ARB_VP_MACHINE(stage);
1338    struct vertex_program *program =
1339       (ctx->VertexProgram._Enabled ? ctx->VertexProgram.Current : 0);
1340
1341    if (!program && ctx->_MaintainTnlProgram) {
1342       program = ctx->_TnlProgram;
1343    }
1344
1345    if (program) {
1346       if (!program->TnlData)
1347          compile_vertex_program( program, m->try_codegen );
1348
1349       /* Grab the state GL state and put into registers:
1350        */
1351       m->File[FILE_LOCAL_PARAM] = program->Base.LocalParams;
1352       m->File[FILE_ENV_PARAM] = ctx->VertexProgram.Parameters;
1353       /* GL_NV_vertex_programs can't reference GL state */
1354       if (program->Parameters)
1355          m->File[FILE_STATE_PARAM] = program->Parameters->ParameterValues;
1356       else
1357          m->File[FILE_STATE_PARAM] = NULL;
1358    }
1359 }
1360
1361
1362
1363
1364
1365
1366
1367 /**
1368  * Called the first time stage->run is called.  In effect, don't
1369  * allocate data until the first time the stage is run.
1370  */
1371 static GLboolean init_vertex_program( GLcontext *ctx,
1372                                       struct tnl_pipeline_stage *stage )
1373 {
1374    TNLcontext *tnl = TNL_CONTEXT(ctx);
1375    struct vertex_buffer *VB = &(tnl->vb);
1376    struct arb_vp_machine *m;
1377    const GLuint size = VB->Size;
1378    GLuint i;
1379
1380    stage->privatePtr = _mesa_malloc(sizeof(*m));
1381    m = ARB_VP_MACHINE(stage);
1382    if (!m)
1383       return GL_FALSE;
1384
1385    /* arb_vertex_machine struct should subsume the VB:
1386     */
1387    m->VB = VB;
1388    m->ctx = ctx;
1389
1390    m->File[0] = ALIGN_MALLOC(REG_MAX * sizeof(GLfloat) * 4, 16);
1391
1392    /* Initialize regs where necessary:
1393     */
1394    ASSIGN_4V(m->File[0][REG_ID], 0, 0, 0, 1);
1395    ASSIGN_4V(m->File[0][REG_ONES], 1, 1, 1, 1);
1396    ASSIGN_4V(m->File[0][REG_SWZ], -1, 1, 0, 0);
1397    ASSIGN_4V(m->File[0][REG_NEG], -1, -1, -1, -1);
1398    ASSIGN_4V(m->File[0][REG_LIT], 1, 0, 0, 1);
1399    ASSIGN_4V(m->File[0][REG_LIT2], 1, .5, .2, 1); /* debug value */
1400
1401    if (_mesa_getenv("MESA_EXPERIMENTAL"))
1402       m->try_codegen = 1;
1403
1404    /* Allocate arrays of vertex output values */
1405    for (i = 0; i < VERT_RESULT_MAX; i++) {
1406       _mesa_vector4f_alloc( &m->attribs[i], 0, size, 32 );
1407       m->attribs[i].size = 4;
1408    }
1409
1410    /* a few other misc allocations */
1411    _mesa_vector4f_alloc( &m->ndcCoords, 0, size, 32 );
1412    m->clipmask = (GLubyte *) ALIGN_MALLOC(sizeof(GLubyte)*size, 32 );
1413
1414    if (ctx->_MaintainTnlProgram)
1415       _mesa_allow_light_in_model( ctx, GL_FALSE );
1416
1417    m->fpucntl_rnd_neg = RND_NEG_FPU; /* const value */
1418    m->fpucntl_restore = RESTORE_FPU; /* const value */
1419
1420    return GL_TRUE;
1421 }
1422
1423
1424
1425
1426 /**
1427  * Destructor for this pipeline stage.
1428  */
1429 static void dtr( struct tnl_pipeline_stage *stage )
1430 {
1431    struct arb_vp_machine *m = ARB_VP_MACHINE(stage);
1432
1433    if (m) {
1434       GLuint i;
1435
1436       /* free the vertex program result arrays */
1437       for (i = 0; i < VERT_RESULT_MAX; i++)
1438          _mesa_vector4f_free( &m->attribs[i] );
1439
1440       /* free misc arrays */
1441       _mesa_vector4f_free( &m->ndcCoords );
1442       ALIGN_FREE( m->clipmask );
1443       ALIGN_FREE( m->File[0] );
1444
1445       _mesa_free( m );
1446       stage->privatePtr = NULL;
1447    }
1448 }
1449
1450 /**
1451  * Public description of this pipeline stage.
1452  */
1453 const struct tnl_pipeline_stage _tnl_arb_vertex_program_stage =
1454 {
1455    "vertex-program",
1456    NULL,                        /* private_data */
1457    init_vertex_program,         /* create */
1458    dtr,                         /* destroy */
1459    validate_vertex_program,     /* validate */
1460    run_arb_vertex_program       /* run */
1461 };