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[reactos.git] / reactos / drivers / bus / isapnp / isapnp.h
1 #pragma once
2
3 #include <ntddk.h>
4
5 #ifdef __cplusplus
6 extern "C" {
7 #endif
8
9 #define TAG_ISAPNP 'PNPI'
10
11 #define IO_RESOURCE_REQUIRED 0x00 //ROS Extension
12
13 #define ISAPNP_ADDRESS_PORT 0x0279 // ADDRESS (W)
14 #define ISAPNP_WRITE_PORT 0x0A79 // WRITE_DATA (W)
15 #define ISAPNP_MIN_READ_PORT 0x0203 // READ_DATA (R)
16 #define ISAPNP_MAX_READ_PORT 0x03FF // READ_DATA (R)
17
18 // Card control registers
19 #define ISAPNP_CARD_READ_DATA_PORT 0x00 // Set READ_DATA port
20 #define ISAPNP_CARD_ISOLATION 0x01 // Isolation
21 #define ISAPNP_CARD_CONFIG_COTROL 0x02 // Configuration control
22 #define ISAPNP_CARD_WAKECSN 0x03 // Wake[CSN]
23 #define ISAPNP_CARD_RESOUCE_DATA 0x04 // Resource data port
24 #define ISAPNP_CARD_STATUS 0x05 // Status port
25 #define ISAPNP_CARD_CSN 0x06 // Card Select Number port
26 #define ISAPNP_CARD_LOG_DEVICE_NUM 0x07 // Logical Device Number
27 #define ISAPNP_CARD_RESERVED 0x08 // Card level reserved
28 #define ISAPNP_CARD_VENDOR_DEFINED 0x20 // Vendor defined
29
30 // Logical device control registers
31 #define ISAPNP_CONTROL_ACTIVATE 0x30 // Activate logical device
32 #define ISAPNP_CONTROL_IO_RANGE_CHECK 0x31 // I/O range conflict check
33 #define ISAPNP_CONTROL_LDC_RESERVED 0x32 // Logical Device Control reserved
34 #define ISAPNP_CONTROL_LDCV_RESERVED 0x38 // Logical Device Control Vendor reserved
35
36 // Logical device configuration registers
37 #define ISAPNP_CONFIG_MEMORY_BASE2 0x00 // Memory base address bits 23-16
38 #define ISAPNP_CONFIG_MEMORY_BASE1 0x01 // Memory base address bits 15-8
39 #define ISAPNP_CONFIG_MEMORY_CONTROL 0x02 // Memory control
40 #define ISAPNP_CONFIG_MEMORY_LIMIT2 0x03 // Memory limit bits 23-16
41 #define ISAPNP_CONFIG_MEMORY_LIMIT1 0x04 // Memory limit bits 15-8
42
43 #define ISAPNP_CONFIG_MEMORY_DESC0 0x40 // Memory descriptor 0
44 #define ISAPNP_CONFIG_MEMORY_DESC1 0x48 // Memory descriptor 1
45 #define ISAPNP_CONFIG_MEMORY_DESC2 0x50 // Memory descriptor 2
46 #define ISAPNP_CONFIG_MEMORY_DESC3 0x58 // Memory descriptor 3
47
48 #define ISAPNP_CONFIG_MEMORY32_BASE3 0x00 // 32-bit memory base address bits 31-24
49 #define ISAPNP_CONFIG_MEMORY32_BASE2 0x01 // 32-bit memory base address bits 23-16
50 #define ISAPNP_CONFIG_MEMORY32_BASE1 0x01 // 32-bit memory base address bits 15-8
51 #define ISAPNP_CONFIG_MEMORY32_CONTROL 0x02 // 32-bit memory control
52 #define ISAPNP_CONFIG_MEMORY32_LIMIT3 0x03 // 32-bit memory limit bits 31-24
53 #define ISAPNP_CONFIG_MEMORY32_LIMIT2 0x04 // 32-bit memory limit bits 23-16
54 #define ISAPNP_CONFIG_MEMORY32_LIMIT1 0x05 // 32-bit memory limit bits 15-8
55
56 #define ISAPNP_CONFIG_MEMORY32_DESC0 0x76 // 32-bit memory descriptor 0
57 #define ISAPNP_CONFIG_MEMORY32_DESC1 0x80 // 32-bit memory descriptor 1
58 #define ISAPNP_CONFIG_MEMORY32_DESC2 0x90 // 32-bit memory descriptor 2
59 #define ISAPNP_CONFIG_MEMORY32_DESC3 0xA0 // 32-bit memory descriptor 3
60
61 #define ISAPNP_CONFIG_IO_BASE1 0x00 // I/O port base address bits 15-8
62 #define ISAPNP_CONFIG_IO_BASE0 0x01 // I/O port base address bits 7-0
63
64 #define ISAPNP_CONFIG_IO_DESC0 0x60 // I/O port descriptor 0
65 #define ISAPNP_CONFIG_IO_DESC1 0x62 // I/O port descriptor 1
66 #define ISAPNP_CONFIG_IO_DESC2 0x64 // I/O port descriptor 2
67 #define ISAPNP_CONFIG_IO_DESC3 0x66 // I/O port descriptor 3
68 #define ISAPNP_CONFIG_IO_DESC4 0x68 // I/O port descriptor 4
69 #define ISAPNP_CONFIG_IO_DESC5 0x6A // I/O port descriptor 5
70 #define ISAPNP_CONFIG_IO_DESC6 0x6C // I/O port descriptor 6
71 #define ISAPNP_CONFIG_IO_DESC7 0x6E // I/O port descriptor 7
72
73 #define ISAPNP_CONFIG_IRQ_LEVEL0 0x70 // Interupt level for descriptor 0
74 #define ISAPNP_CONFIG_IRQ_TYPE0 0x71 // Type level for descriptor 0
75 #define ISAPNP_CONFIG_IRQ_LEVEL1 0x72 // Interupt level for descriptor 1
76 #define ISAPNP_CONFIG_IRQ_TYPE1 0x73 // Type level for descriptor 1
77
78 #define ISAPNP_CONFIG_DMA_CHANNEL0 0x74 // DMA channel for descriptor 0
79 #define ISAPNP_CONFIG_DMA_CHANNEL1 0x75 // DMA channel for descriptor 1
80
81
82 typedef struct _PNPISA_SERIAL_ID
83 {
84 UCHAR VendorId[4]; // Vendor Identifier
85 UCHAR SerialId[4]; // Serial number
86 UCHAR Checksum; // Checksum
87 } PNPISA_SERIAL_ID, *PPNPISA_SERIAL_ID;
88
89
90 #define ISAPNP_RES_PRIORITY_PREFERRED 0
91 #define ISAPNP_RES_PRIORITY_ACCEPTABLE 1
92 #define ISAPNP_RES_PRIORITY_FUNCTIONAL 2
93 #define ISAPNP_RES_PRIORITY_INVALID 65535
94
95
96 #define ISAPNP_RESOURCE_ITEM_TYPE 0x80 // 0 = small, 1 = large
97
98 // Small Resource Item Names (SRINs)
99 #define ISAPNP_SRIN_VERSION 0x1 // PnP version number
100 #define ISAPNP_SRIN_LDEVICE_ID 0x2 // Logical device id
101 #define ISAPNP_SRIN_CDEVICE_ID 0x3 // Compatible device id
102 #define ISAPNP_SRIN_IRQ_FORMAT 0x4 // IRQ format
103 #define ISAPNP_SRIN_DMA_FORMAT 0x5 // DMA format
104 #define ISAPNP_SRIN_START_DFUNCTION 0x6 // Start dependant function
105 #define ISAPNP_SRIN_END_DFUNCTION 0x7 // End dependant function
106 #define ISAPNP_SRIN_IO_DESCRIPTOR 0x8 // I/O port descriptor
107 #define ISAPNP_SRIN_FL_IO_DESCRIPOTOR 0x9 // Fixed location I/O port descriptor
108 #define ISAPNP_SRIN_VENDOR_DEFINED 0xE // Vendor defined
109 #define ISAPNP_SRIN_END_TAG 0xF // End tag
110
111 typedef struct _ISAPNP_SRI_VERSION
112 {
113 UCHAR Header;
114 UCHAR Version; // Packed BCD format version number
115 UCHAR VendorVersion; // Vendor specific version number
116 } ISAPNP_SRI_VERSION, *PISAPNP_SRI_VERSION;
117
118 typedef struct _ISAPNP_SRI_LDEVICE_ID
119 {
120 UCHAR Header;
121 USHORT DeviceId; // Logical device id
122 USHORT VendorId; // Manufacturer id
123 UCHAR Flags; // Flags
124 } ISAPNP_SRI_LDEVICE_ID, *PISAPNP_SRI_LDEVICE_ID;
125
126 typedef struct _ISAPNP_SRI_CDEVICE_ID
127 {
128 UCHAR Header;
129 USHORT DeviceId; // Logical device id
130 USHORT VendorId; // Manufacturer id
131 } ISAPNP_SRI_CDEVICE_ID, *PISAPNP_SRI_CDEVICE_ID;
132
133 typedef struct _ISAPNP_SRI_IRQ_FORMAT
134 {
135 UCHAR Header;
136 USHORT Mask; // IRQ mask (bit 0 = irq 0, etc.)
137 UCHAR Information; // IRQ information
138 } ISAPNP_SRI_IRQ_FORMAT, *PISAPNP_SRI_IRQ_FORMAT;
139
140 typedef struct _ISAPNP_SRI_DMA_FORMAT
141 {
142 UCHAR Header;
143 USHORT Mask; // DMA channel mask (bit 0 = channel 0, etc.)
144 UCHAR Information; // DMA information
145 } ISAPNP_SRI_DMA_FORMAT, *PISAPNP_SRI_DMA_FORMAT;
146
147 typedef struct _ISAPNP_SRI_START_DFUNCTION
148 {
149 UCHAR Header;
150 } ISAPNP_SRI_START_DFUNCTION, *PISAPNP_SRI_START_DFUNCTION;
151
152 typedef struct _ISAPNP_SRI_END_DFUNCTION
153 {
154 UCHAR Header;
155 } ISAPNP_SRI_END_DFUNCTION, *PISAPNP_SRI_END_DFUNCTION;
156
157 typedef struct _ISAPNP_SRI_IO_DESCRIPTOR
158 {
159 UCHAR Header;
160 UCHAR Information; // Information
161 USHORT RangeMinBase; // Minimum base address
162 USHORT RangeMaxBase; // Maximum base address
163 UCHAR Alignment; // Base alignment
164 UCHAR RangeLength; // Length of range
165 } ISAPNP_SRI_IO_DESCRIPTOR, *PISAPNP_SRI_IO_DESCRIPTOR;
166
167 typedef struct _ISAPNP_SRI_FL_IO_DESCRIPTOR
168 {
169 UCHAR Header;
170 USHORT RangeBase; // Range base address
171 UCHAR RangeLength; // Length of range
172 } ISAPNP_SRI_FL_IO_DESCRIPTOR, *PISAPNP_SRI_FL_IO_DESCRIPTOR;
173
174 typedef struct _PISAPNP_SRI_VENDOR_DEFINED
175 {
176 UCHAR Header;
177 UCHAR Reserved[0]; // Vendor defined
178 } ISAPNP_SRI_VENDOR_DEFINED, *PISAPNP_SRI_VENDOR_DEFINED;
179
180 typedef struct _ISAPNP_SRI_END_TAG
181 {
182 UCHAR Header;
183 UCHAR Checksum; // Checksum
184 } ISAPNP_SRI_END_TAG, *PISAPNP_SRI_END_TAG;
185
186
187 typedef struct _ISAPNP_LRI
188 {
189 UCHAR Header;
190 USHORT Length; // Length of data items
191 } ISAPNP_LRI, *PISAPNP_LRI;
192
193 // Large Resource Item Names (LRINs)
194 #define ISAPNP_LRIN_MEMORY_RANGE 0x1 // Memory range descriptor
195 #define ISAPNP_LRIN_ID_STRING_ANSI 0x2 // Identifier string (ANSI)
196 #define ISAPNP_LRIN_ID_STRING_UNICODE 0x3 // Identifier string (UNICODE)
197 #define ISAPNP_LRIN_VENDOR_DEFINED 0x4 // Vendor defined
198 #define ISAPNP_LRIN_MEMORY_RANGE32 0x5 // 32-bit memory range descriptor
199 #define ISAPNP_LRIN_FL_MEMORY_RANGE32 0x6 // 32-bit fixed location memory range descriptor
200
201 typedef struct _ISAPNP_LRI_MEMORY_RANGE
202 {
203 UCHAR Header;
204 USHORT Length; // Length of data items
205 UCHAR Information; // Information
206 USHORT RangeMinBase; // Minimum base address
207 USHORT RangeMaxBase; // Maximum base address
208 USHORT Alignment; // Base alignment
209 USHORT RangeLength; // Length of range
210 } ISAPNP_LRI_MEMORY_RANGE, *PISAPNP_LRI_MEMORY_RANGE;
211
212 typedef struct _ISAPNP_LRI_ID_STRING_ANSI
213 {
214 UCHAR Header;
215 USHORT Length; // Length of data items
216 UCHAR String[0]; // Identifier string
217 } ISAPNP_LRI_ID_STRING_ANSI, *PISAPNP_LRI_ID_STRING_ANSI;
218
219 typedef struct _ISAPNP_LRI_ID_STRING_UNICODE
220 {
221 UCHAR Header;
222 USHORT Length; // Length of data items
223 USHORT CountryId; // Country identifier
224 USHORT String[0]; // Identifier string
225 } ISAPNP_LRI_ID_STRING_UNICODE, *PISAPNP_LRI_ID_STRING_UNICODE;
226
227 typedef struct _PISAPNP_LRI_VENDOR_DEFINED
228 {
229 UCHAR Header;
230 USHORT Length; // Length of data items
231 UCHAR Reserved[0]; // Vendor defined
232 } ISAPNP_LRI_VENDOR_DEFINED, *PISAPNP_LRI_VENDOR_DEFINED;
233
234 typedef struct _ISAPNP_LRI_MEMORY_RANGE32
235 {
236 UCHAR Header;
237 USHORT Length; // Length of data items
238 UCHAR Information; // Information
239 ULONG RangeMinBase; // Minimum base address
240 ULONG RangeMaxBase; // Maximum base address
241 ULONG Alignment; // Base alignment
242 ULONG RangeLength; // Length of range
243 } ISAPNP_LRI_MEMORY_RANGE32, *PISAPNP_LRI_MEMORY_RANGE32;
244
245 typedef struct _ISAPNP_LRI_FL_MEMORY_RANGE32
246 {
247 UCHAR Header;
248 USHORT Length; // Length of data items
249 UCHAR Information; // Information
250 ULONG RangeMinBase; // Minimum base address
251 ULONG RangeMaxBase; // Maximum base address
252 ULONG RangeLength; // Length of range
253 } ISAPNP_LRI_FL_MEMORY_RANGE32, *PISAPNP_LRI_FL_MEMORY_RANGE32;
254
255 typedef struct _ISAPNP_CARD
256 {
257 LIST_ENTRY ListEntry;
258 USHORT CardId;
259 USHORT VendorId;
260 USHORT DeviceId;
261 ULONG Serial;
262 UCHAR PNPVersion;
263 UCHAR ProductVersion;
264 UNICODE_STRING Name;
265 LIST_ENTRY LogicalDevices;
266 KSPIN_LOCK LogicalDevicesLock;
267 } ISAPNP_CARD, *PISAPNP_CARD;
268
269
270 typedef struct _ISAPNP_DESCRIPTOR
271 {
272 LIST_ENTRY ListEntry;
273 IO_RESOURCE_DESCRIPTOR Descriptor;
274 } ISAPNP_DESCRIPTOR, *PISAPNP_DESCRIPTOR;
275
276 typedef struct _ISAPNP_CONFIGURATION_LIST
277 {
278 LIST_ENTRY ListEntry;
279 ULONG Priority;
280 LIST_ENTRY ListHead;
281 } ISAPNP_CONFIGURATION_LIST, *PISAPNP_CONFIGURATION_LIST;
282
283
284 #define MAX_COMPATIBLE_ID 32
285
286 typedef struct _ISAPNP_LOGICAL_DEVICE
287 {
288 LIST_ENTRY CardListEntry;
289 LIST_ENTRY DeviceListEntry;
290 USHORT Number;
291 USHORT VendorId;
292 USHORT DeviceId;
293 USHORT CVendorId[MAX_COMPATIBLE_ID];
294 USHORT CDeviceId[MAX_COMPATIBLE_ID];
295 USHORT Regs;
296 PISAPNP_CARD Card;
297 UNICODE_STRING Name;
298 PDEVICE_OBJECT Pdo;
299 PIO_RESOURCE_REQUIREMENTS_LIST ResourceLists;
300 LIST_ENTRY Configuration;
301 ULONG ConfigurationSize;
302 ULONG DescriptorCount;
303 ULONG CurrentDescriptorCount;
304 } ISAPNP_LOGICAL_DEVICE, *PISAPNP_LOGICAL_DEVICE;
305
306
307 typedef enum {
308 dsStopped,
309 dsStarted
310 } ISAPNP_DEVICE_STATE;
311
312 typedef struct _ISAPNP_DEVICE_EXTENSION
313 {
314 // Physical Device Object
315 PDEVICE_OBJECT Pdo;
316 // Lower device object
317 PDEVICE_OBJECT Ldo;
318 // List of ISA PnP cards managed by this driver
319 LIST_ENTRY CardListHead;
320 // List of devices managed by this driver
321 LIST_ENTRY DeviceListHead;
322 // Number of devices managed by this driver
323 ULONG DeviceListCount;
324 // Spinlock for the linked lists
325 KSPIN_LOCK GlobalListLock;
326 // Current state of the driver
327 ISAPNP_DEVICE_STATE State;
328 } ISAPNP_DEVICE_EXTENSION, *PISAPNP_DEVICE_EXTENSION;
329
330 NTSTATUS
331 NTAPI
332 DriverEntry(
333 IN PDRIVER_OBJECT DriverObject,
334 IN PUNICODE_STRING RegistryPath);
335
336 #ifdef __cplusplus
337 }
338 #endif
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