Relative include path fixed to absolute path.
[reactos.git] / reactos / drivers / dd / sound / dsp.c
1 /*
2 * COPYRIGHT: See COPYING in the top level directory
3 * PROJECT: ReactOS kernel
4 * FILE: drivers/dd/sound/dsp.c
5 * PURPOSE: Digital Signal Processing ?
6 * PROGRAMMER: Snatched from ?
7 *
8 * UPDATE HISTORY:
9 * ??/??/??: Created
10 * 10/23/02: Steven Edwards (Steven_Ed4153@yahoo.com)
11 * Minor build fix
12 */
13
14 #include "dsp.h"
15 #include "sb16.h"
16
17 /************************************
18 * unsigned char read_dsp(void)
19 *
20 * Reads the DSP chip
21 * Arguments: none
22 * Returns: Byte read
23 ************************************/
24 unsigned char read_dsp(unsigned short base)
25 {
26 while((inb(base+0x0e)&0x80)==0); //Wait until there is something to read
27 return inb(base+0x0a);
28 }
29
30 /************************************'
31 * sb_status detect_dsp(void);
32 *
33 * Detects if a SB16 is installed
34 * Arguments: None
35 * Returns: Success or failure
36 ************************************/
37 sb_status detect_dsp(SB16* sb16)
38 {
39 for(base=0x200;base<0x280;base+=0x10) //Tries to reset all DSP addresses there is
40 if(reset_dsp(base)==SB_TRUE)
41 {
42 sb16->base=base;
43 return SB_TRUE;
44 }
45 return SB_FALSE;
46 }
47
48 /**************************************
49 * sb_status reset_dsp(unsigned short base_address);
50 *
51 * Tries to reset a DSP chip
52 * Arguments: base address
53 * Returns: Success of failure
54 **************************************/
55 sb_status reset_dsp(unsigned short base_address)
56 {
57 int delay;
58
59 outb(base_address+DSP_RESET_PORT,1);
60 for(delay=0;delay<0xffff;delay++);
61
62 outb(base_address+DSP_RESET_PORT,0);
63 for(delay=0;delay<0xffff;delay++);
64
65 if((inb(base_address+DSP_READ_STATUS_PORT)&0x80)==0) return SB_FALSE;
66
67 if(inb(base_address+DSP_READ_DATA_PORT)!=0xAA) return SB_FALSE;
68
69 return SB_TRUE;
70 }
71
72 void write_dsp(unsigned short base,unsigned char data)
73 {
74 while ((inb(base+DSP_WRITE_PORT) & 0x80) != 0);
75 outb(base+DSP_WRITE_PORT, data);
76 }
77