reactos/drivers/network/dd/rtl8139/include/8139.h

   1 /*
   2  * COPYRIGHT:   See COPYING in the top level directory
   3  * PROJECT:     ReactOS RTL8139 Driver
   4  * FILE:        include/8139.h
   5  * PURPOSE:     8139 NIC definitions
   6  */
   7
   8 #pragma once
   9 //Register addresses
  10 #define R_MAC           0x00    //MAC address uses bytes 0-5, 6 and 7 are reserved
  11 #define R_MCAST0        0x08    //Multicast registers
  12 #define R_MCAST1        0x09    //Multicast registers
  13 #define R_MCAST2        0x0A
  14 #define R_MCAST3        0x0B
  15 #define R_MCAST4        0x0C
  16 #define R_MCAST5        0x0D
  17 #define R_MCAST6        0x0E
  18 #define R_MCAST7        0x0F
  19 #define R_TXSTS0        0x10    //TX status, 0x10-0x13, 4 bytes
  20 #define R_TXSTS1        0x14
  21 #define R_TXSTS2        0x18
  22 #define R_TXSTS3        0x1C
  23 #define R_TXSAD0        0x20    //TX start address of descriptor 0
  24 #define R_TXSAD1        0x24
  25 #define R_TXSAD2        0x28
  26 #define R_TXSAD3        0x2C
  27 #define R_RXSA          0x30    //RX buffer start address
  28 #define R_ERXBC         0x34    //Early RX byte count register
  29 #define R_ERXSTS        0x36    //Early RX status register
  30
  31 #define R_CMD           0x37    //Command register
  32 #define B_CMD_TXE       0x04    //Enable TX
  33 #define B_CMD_RXE       0x08    //Enable RX
  34 #define B_CMD_RST       0x10    //Reset bit
  35
  36 #define R_CAPR          0x38    //Current address of packet read
  37 #define R_CBA           0x3A    //Current buffer address
  38 #define R_IM            0x3C    //Interrupt mask register
  39 #define R_IS            0x3E    //Interrupt status register
  40 #define R_TC            0x40    //Transmit configuration register
  41
  42 #define R_RC            0x44    //Receive configuration register
  43 #define B_RC_AAP        0x01    //Accept all packets
  44 #define B_RC_APM        0x02    //Accept packets sent to device MAC
  45 #define B_RC_AM         0x04    //Accept multicast packets
  46 #define B_RC_AB         0x08    //Accept broadcast packets
  47 #define B_RC_AR         0x10    //Accept runt (smaller than 64bytes) packets
  48
  49 #define R_TCTR          0x48    //Timer counter register
  50 #define R_MPC           0x4C    //Missed packet counter
  51 #define R_9346CR        0x50    //93C46 command register
  52 #define R_CFG0          0x51    //Configuration register 0
  53 #define R_CFG1          0x52
  54 #define R_TINTR         0x54    //Timer interrupt register
  55 #define R_MS            0x58    //Media status register
  56 #define R_CFG3          0x59    //Configuration register 3
  57 #define R_CFG4          0x5A    //Configuration register 4
  58 #define R_MINTS         0x5C    //Multiple interrupt select
  59 #define R_PCIID         0x5E    //PCI Revision ID = 0x10
  60 #define R_DTSTS         0x60    //TX status of all descriptors
  61 #define R_BMC           0x62    //Basic mode control register
  62 #define R_BMSTS         0x64    //Basic mode status register
  63 #define R_ANA           0x66    //Auto-negotiation advertisement
  64 #define R_ANLP          0x68    //Auto-negotiation link partner
  65 #define R_ANEX          0x6A    //Auto-negotiation expansion
  66 #define R_DCTR          0x6C    //Disconnect counter
  67 #define R_FCSCTR        0x6E    //False carrier sense counter
  68 #define R_NWT           0x70    //N-way test register
  69 #define R_RXERRCTR      0x72    //RX error counter
  70 #define R_CSCFG         0x74    //CS configuration register
  71 #define R_PHYP1         0x78    //PHY parameter 1
  72 #define R_TWP           0x7C    //Twister parameter
  73 #define R_PHYP2         0x80    //PHY parameter 2
  74 #define R_PCRC0         0x84    //Power management CRC for wakeup frame 0
  75 #define R_PCRC1         0x85
  76 #define R_PCRC2         0x86
  77 #define R_PCRC3         0x87
  78 #define R_PCRC4         0x88
  79 #define R_PCRC5         0x89
  80 #define R_PCRC6         0x8A
  81 #define R_PCRC7         0x8B
  82 #define R_WAKE0         0x8C    //Power management wakeup frame 0
  83 #define R_WAKE1         0x94
  84 #define R_WAKE2         0x9C
  85 #define R_WAKE3         0xA4
  86 #define R_WAKE4         0xAC
  87 #define R_WAKE5         0xB4
  88 #define R_WAKE6         0xBC
  89 #define R_WAKE7         0xC4
  90 #define R_LSBCRC0       0xCC    //LSB of the mask byte of wakeup frame 0 within offset 12 to 75
  91 #define R_LSBCRC0       0xCD
  92 #define R_LSBCRC0       0xCE
  93 #define R_LSBCRC0       0xCF
  94 #define R_LSBCRC0       0xD0
  95 #define R_LSBCRC0       0xD1
  96 #define R_LSBCRC0       0xD2
  97 #define R_LSBCRC0       0xD3
  98 #define R_CFG5          0xD8    //Configuration register 5
  99
 100 //EEPROM Control Bytes
 101 #define EE_DATA_READ    0x01    //Chip data out
 102 #define EE_DATA_WRITE   0x02    //Chip data in
 103 #define EE_SHIFT_CLK    0x04    //Chip shift clock
 104 #define EE_CS           0x08    //Chip select
 105 #define EE_ENB          0x88    //Chip enable
 106
 107
 108 //EEPROM Commands
 109 #define EE_READ_CMD     0x06
 110
 111
 112 /* NIC prepended structure to a received packet */
 113 typedef struct _PACKET_HEADER {
 114     UCHAR Status;           /* See RSR_* constants */
 115     UCHAR NextPacket;       /* Pointer to next packet in chain */
 116     USHORT PacketLength;    /* Length of packet including this header */
 117 } PACKET_HEADER, *PPACKET_HEADER;
 118
 119 #define IEEE_802_ADDR_LENGTH 6
 120
 121 /* Ethernet frame header */
 122 typedef struct _ETH_HEADER {
 123     UCHAR Destination[IEEE_802_ADDR_LENGTH];
 124     UCHAR Source[IEEE_802_ADDR_LENGTH];
 125     USHORT PayloadType;
 126 } ETH_HEADER, *PETH_HEADER;
 127
 128 typedef struct _DISCARD_HEADER {
 129     PACKET_HEADER HWHeader;
 130     ETH_HEADER EthernetHeader;
 131 } DISCARD_HEADER, *PDISCARD_HEADER;
 132
 133 #define NICDisableInterrupts(Adapter) { \
 134     NDIS_DbgPrint(MAX_TRACE, ("NICDisableInterrupts()\n")); \
 135     NdisRawWritePortUchar((Adapter)->IOBase + PG0_IMR, 0x00); \
 136 }
 137
 138 #define NICEnableInterrupts(Adapter) { \
 139     NDIS_DbgPrint(MAX_TRACE, ("NICEnableInterrupts() Mask (0x%X)\n", (Adapter)->InterruptMask)); \
 140     NdisRawWritePortUchar((Adapter)->IOBase + PG0_IMR, (Adapter)->InterruptMask); \
 141 }
 142
 143 VOID NTAPI MiniportHandleInterrupt(
 144     IN  NDIS_HANDLE MiniportAdapterContext);
 145
 146 /* EOF */