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[reactos.git] / reactos / drivers / storage / ide / uniata / atapi.h
1 /*++
2
3 Copyright (c) 2002-2005 Alexandr A. Telyatnikov (Alter)
4
5 Module Name:
6 atapi.h
7
8 Abstract:
9 This file contains IDE, ATA, ATAPI and SCSI Miniport definitions
10 and function prototypes.
11
12 Author:
13 Alexander A. Telyatnikov (Alter)
14
15 Environment:
16 kernel mode only
17
18 Notes:
19
20 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30
31 Revision History:
32
33 Some definitions were taken from standard ATAPI.SYS sources from NT4 DDK by
34 Mike Glass (MGlass)
35
36 Some definitions were taken from FreeBSD 4.3-4.6 ATA driver by
37 Søren Schmidt, Copyright (c) 1998,1999,2000,2001
38
39 Code was changed/updated by
40 Alter, Copyright (c) 2002-2004
41
42
43 --*/
44 #ifndef __GLOBAL_H__
45 #define __GLOBAL_H__
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif //__cplusplus
50
51 #ifndef USER_MODE
52 #include "config.h"
53 #endif //USER_MODE
54
55 #include "scsi.h"
56 #include "stdio.h"
57 #include "string.h"
58
59 #ifdef _DEBUG
60
61
62 #ifndef _DBGNT_
63
64 #ifdef KdPrint
65 #undef KdPrint
66 #endif
67
68 #ifdef USE_DBGPRINT_LOGGER
69 #include "inc\PostDbgMesg.h"
70 #define DbgPrint DbgDump_Printf
71 #define Connect_DbgPrint() {DbgDump_SetAutoReconnect(TRUE); DbgDump_Reconnect();}
72 #else // USE_DBGPRINT_LOGGER
73 #define Connect_DbgPrint() {;}
74 #endif // USE_DBGPRINT_LOGGER
75
76 #ifdef SCSI_PORT_DBG_PRINT
77
78 SCSIPORT_API
79 VOID
80 __cdecl
81 ScsiDebugPrint(
82 ULONG DebugPrintLevel,
83 PCCHAR DebugMessage,
84 ...
85 );
86
87 #define PRINT_PREFIX 0,
88
89 #define KdPrint3(_x_) ScsiDebugPrint _x_ {;}
90 #define KdPrint2(_x_) {ScsiDebugPrint("%x: ", PsGetCurrentThread()) ; ScsiDebugPrint _x_ ; }
91 #define KdPrint(_x_) ScsiDebugPrint _x_ {;}
92
93 #else // SCSI_PORT_DBG_PRINT
94
95 //#ifndef USE_DBGPRINT_LOGGER
96 //ULONG
97 //_cdecl
98 //DbgPrint(
99 // PCH Format,
100 // ...
101 // );
102 //#endif // USE_DBGPRINT_LOGGER
103
104 #define PRINT_PREFIX
105
106 // Note, that using DbgPrint on raised IRQL will crash w2k
107 // tis will not happen immediately, so we shall see some logs
108 //#define LOG_ON_RAISED_IRQL_W2K TRUE
109 //#define LOG_ON_RAISED_IRQL_W2K FALSE
110
111 #define KdPrint3(_x_) {if(LOG_ON_RAISED_IRQL_W2K || MajorVersion < 0x05 || KeGetCurrentIrql() <= 2){/*DbgPrint("%x: ", PsGetCurrentThread()) ;*/ DbgPrint _x_ ; if(g_LogToDisplay){ PrintNtConsole _x_ ;} }}
112 #define KdPrint2(_x_) {if(LOG_ON_RAISED_IRQL_W2K || MajorVersion < 0x05 || KeGetCurrentIrql() <= 2){/*DbgPrint("%x: ", PsGetCurrentThread()) ;*/ DbgPrint _x_ ; if(g_LogToDisplay){ PrintNtConsole _x_ ;} }}
113 #define KdPrint(_x_) {if(LOG_ON_RAISED_IRQL_W2K || MajorVersion < 0x05 || KeGetCurrentIrql() <= 2){/*DbgPrint("%x: ", PsGetCurrentThread()) ;*/ DbgPrint _x_ ; if(g_LogToDisplay){ PrintNtConsole _x_ ;} }}
114 /*
115 #define PRINT_PREFIX_PTR ((PCHAR)&__tmp__kdprint__buff__)
116 #define PRINT_UPREFIX_PTR ((PWCHAR)&__tmp__kdprint__ubuff__)
117 #define PRINT_PREFIX PRINT_PREFIX_PTR,
118 #define KdPrint2(_x_) \
119 { \
120 WCHAR __tmp__kdprint__ubuff__[256]; \
121 CHAR __tmp__kdprint__buff__[256]; \
122 UNICODE_STRING __tmp__usrt__buff__; \
123 sprintf _x_; \
124 swprintf (PRINT_UPREFIX_PTR, L"%hs", PRINT_PREFIX_PTR); \
125 __tmp__usrt__buff__.Buffer = PRINT_UPREFIX_PTR; \
126 __tmp__usrt__buff__.Length = \
127 __tmp__usrt__buff__.MaximumLength = strlen(PRINT_PREFIX_PTR); \
128 NtDisplayString(&__tmp__usrt__buff__); \
129 };
130 #define KdPrint(_x_) DbgPrint _x_
131 */
132 #endif // SCSI_PORT_DBG_PRINT
133
134 //#define AtapiStallExecution(dt) { KdPrint2((" AtapiStallExecution(%d)\n", dt)); ScsiPortStallExecution(dt); }
135 #define AtapiStallExecution(dt) { ScsiPortStallExecution(dt); }
136
137 #endif // _DBGNT_
138
139 #else // _DEBUG
140
141 #ifdef KdPrint
142 #undef KdPrint
143 #endif
144
145 #define PRINT_PREFIX "UniATA: "
146
147 //#define KdPrint3(_x_) {if(LOG_ON_RAISED_IRQL_W2K || MajorVersion < 0x05 || KeGetCurrentIrql() <= 2){/*DbgPrint("%x: ", PsGetCurrentThread()) ;*/ DbgPrint _x_ ; if(g_LogToDisplay){ PrintNtConsole _x_ ;} }}
148 #define KdPrint3(_x_) {;}
149 #define KdPrint2(_x_) {;}
150 #define KdPrint(_x_) {;}
151 #define Connect_DbgPrint() {;}
152
153 #define AtapiStallExecution(dt) ScsiPortStallExecution(dt)
154
155 #endif // _DEBUG
156
157 // IDE register definition
158
159 #pragma pack(push, 1)
160
161 typedef union _IDE_REGISTERS_1 {
162 struct _o {
163 UCHAR Data;
164 UCHAR Feature;
165 UCHAR BlockCount;
166 UCHAR BlockNumber;
167 UCHAR CylinderLow;
168 UCHAR CylinderHigh;
169 UCHAR DriveSelect;
170 UCHAR Command;
171 } o;
172
173 struct _i {
174 UCHAR Data;
175 UCHAR Error;
176 UCHAR BlockCount;
177 UCHAR BlockNumber;
178 UCHAR CylinderLow;
179 UCHAR CylinderHigh;
180 UCHAR DriveSelect;
181 UCHAR Status;
182 } i;
183
184 } IDE_REGISTERS_1, *PIDE_REGISTERS_1;
185
186 #define IDX_IO1 0
187 #define IDX_IO1_SZ sizeof(IDE_REGISTERS_1)
188
189 #define IDX_IO1 0
190 #define IDX_IO1_SZ sizeof(IDE_REGISTERS_1)
191 #define IDX_IO1_i_Data (FIELD_OFFSET(IDE_REGISTERS_1, i.Data )+IDX_IO1)
192 #define IDX_IO1_i_Error (FIELD_OFFSET(IDE_REGISTERS_1, i.Error )+IDX_IO1)
193 #define IDX_IO1_i_BlockCount (FIELD_OFFSET(IDE_REGISTERS_1, i.BlockCount )+IDX_IO1)
194 #define IDX_IO1_i_BlockNumber (FIELD_OFFSET(IDE_REGISTERS_1, i.BlockNumber )+IDX_IO1)
195 #define IDX_IO1_i_CylinderLow (FIELD_OFFSET(IDE_REGISTERS_1, i.CylinderLow )+IDX_IO1)
196 #define IDX_IO1_i_CylinderHigh (FIELD_OFFSET(IDE_REGISTERS_1, i.CylinderHigh)+IDX_IO1)
197 #define IDX_IO1_i_DriveSelect (FIELD_OFFSET(IDE_REGISTERS_1, i.DriveSelect )+IDX_IO1)
198 #define IDX_IO1_i_Status (FIELD_OFFSET(IDE_REGISTERS_1, i.Status )+IDX_IO1)
199
200 #define IDX_IO1_o IDX_IO1_SZ
201 #define IDX_IO1_o_SZ sizeof(IDE_REGISTERS_1)
202
203 #define IDX_IO1_o_Data (FIELD_OFFSET(IDE_REGISTERS_1, o.Data )+IDX_IO1_o)
204 #define IDX_IO1_o_Feature (FIELD_OFFSET(IDE_REGISTERS_1, o.Feature )+IDX_IO1_o)
205 #define IDX_IO1_o_BlockCount (FIELD_OFFSET(IDE_REGISTERS_1, o.BlockCount )+IDX_IO1_o)
206 #define IDX_IO1_o_BlockNumber (FIELD_OFFSET(IDE_REGISTERS_1, o.BlockNumber )+IDX_IO1_o)
207 #define IDX_IO1_o_CylinderLow (FIELD_OFFSET(IDE_REGISTERS_1, o.CylinderLow )+IDX_IO1_o)
208 #define IDX_IO1_o_CylinderHigh (FIELD_OFFSET(IDE_REGISTERS_1, o.CylinderHigh)+IDX_IO1_o)
209 #define IDX_IO1_o_DriveSelect (FIELD_OFFSET(IDE_REGISTERS_1, o.DriveSelect )+IDX_IO1_o)
210 #define IDX_IO1_o_Command (FIELD_OFFSET(IDE_REGISTERS_1, o.Command )+IDX_IO1_o)
211
212 typedef struct _IDE_REGISTERS_2 {
213 UCHAR AltStatus;
214 UCHAR DriveAddress;
215 } IDE_REGISTERS_2, *PIDE_REGISTERS_2;
216
217 #define IDX_IO2 (IDX_IO1_o+IDX_IO1_o_SZ)
218 #define IDX_IO2_SZ sizeof(IDE_REGISTERS_2)
219
220 #define IDX_IO2_AltStatus (FIELD_OFFSET(IDE_REGISTERS_2, AltStatus )+IDX_IO2)
221 #define IDX_IO2_DriveAddress (FIELD_OFFSET(IDE_REGISTERS_2, DriveAddress)+IDX_IO2)
222
223 #define IDX_IO2_o (IDX_IO2+IDX_IO2_SZ)
224 #define IDX_IO2_o_SZ sizeof(IDE_REGISTERS_2)
225
226 #define IDX_IO2_o_Control (FIELD_OFFSET(IDE_REGISTERS_2, AltStatus )+IDX_IO2_o)
227 //
228 // Device Extension Device Flags
229 //
230
231 #define DFLAGS_DEVICE_PRESENT 0x0001 // Indicates that some device is present.
232 #define DFLAGS_ATAPI_DEVICE 0x0002 // Indicates whether ATAPI commands can be used.
233 #define DFLAGS_TAPE_DEVICE 0x0004 // Indicates whether this is a tape device.
234 #define DFLAGS_INT_DRQ 0x0008 // Indicates whether device interrupts as DRQ is set after
235 // receiving ATAPI Packet Command
236 #define DFLAGS_REMOVABLE_DRIVE 0x0010 // Indicates that the drive has the 'removable' bit set in
237 // identify data (offset 128)
238 #define DFLAGS_MEDIA_STATUS_ENABLED 0x0020 // Media status notification enabled
239 #define DFLAGS_ATAPI_CHANGER 0x0040 // Indicates atapi 2.5 changer present.
240 #define DFLAGS_SANYO_ATAPI_CHANGER 0x0080 // Indicates multi-platter device, not conforming to the 2.5 spec.
241 #define DFLAGS_CHANGER_INITED 0x0100 // Indicates that the init path for changers has already been done.
242 #define DFLAGS_LBA_ENABLED 0x0200 // Indicates that we should use LBA addressing rather than CHS
243 #define DFLAGS_DWORDIO_ENABLED 0x0400 // Indicates that we should use 32-bit IO
244 #define DFLAGS_WCACHE_ENABLED 0x0800 // Indicates that we use write cache
245 #define DFLAGS_RCACHE_ENABLED 0x1000 // Indicates that we use read cache
246 #define DFLAGS_ORIG_GEOMETRY 0x2000 //
247 #define DFLAGS_REINIT_DMA 0x4000 //
248 #define DFLAGS_HIDDEN 0x8000 // Hidden device, available only with special IOCTLs
249 // via communication virtual device
250 //#define DFLAGS_ 0x10000 //
251 //
252 // Used to disable 'advanced' features.
253 //
254
255 #define MAX_ERRORS 4
256
257 //
258 // ATAPI command definitions
259 //
260
261 #define ATAPI_MODE_SENSE 0x5A
262 #define ATAPI_MODE_SELECT 0x55
263 #define ATAPI_FORMAT_UNIT 0x24
264
265 // ATAPI Command Descriptor Block
266
267 typedef struct _MODE_SENSE_10 {
268 UCHAR OperationCode;
269 UCHAR Reserved1;
270 UCHAR PageCode : 6;
271 UCHAR Pc : 2;
272 UCHAR Reserved2[4];
273 UCHAR ParameterListLengthMsb;
274 UCHAR ParameterListLengthLsb;
275 UCHAR Reserved3[3];
276 } MODE_SENSE_10, *PMODE_SENSE_10;
277
278 typedef struct _MODE_SELECT_10 {
279 UCHAR OperationCode;
280 UCHAR Reserved1 : 4;
281 UCHAR PFBit : 1;
282 UCHAR Reserved2 : 3;
283 UCHAR Reserved3[5];
284 UCHAR ParameterListLengthMsb;
285 UCHAR ParameterListLengthLsb;
286 UCHAR Reserved4[3];
287 } MODE_SELECT_10, *PMODE_SELECT_10;
288
289 typedef struct _MODE_PARAMETER_HEADER_10 {
290 UCHAR ModeDataLengthMsb;
291 UCHAR ModeDataLengthLsb;
292 UCHAR MediumType;
293 UCHAR Reserved[5];
294 }MODE_PARAMETER_HEADER_10, *PMODE_PARAMETER_HEADER_10;
295
296 //
297 // IDE command definitions
298 //
299
300 #define IDE_COMMAND_ATAPI_RESET 0x08
301 #define IDE_COMMAND_RECALIBRATE 0x10
302 #define IDE_COMMAND_READ 0x20
303 #define IDE_COMMAND_READ_NO_RETR 0x21
304 #define IDE_COMMAND_READ48 0x24
305 #define IDE_COMMAND_READ_DMA48 0x25
306 #define IDE_COMMAND_READ_DMA_Q48 0x26
307 #define IDE_COMMAND_READ_NATIVE_SIZE48 0x27
308 #define IDE_COMMAND_READ_MUL48 0x29
309 #define IDE_COMMAND_READ_STREAM_DMA48 0x2A
310 #define IDE_COMMAND_READ_STREAM48 0x2B
311 #define IDE_COMMAND_READ_LOG48 0x2f
312 #define IDE_COMMAND_WRITE 0x30
313 #define IDE_COMMAND_WRITE_NO_RETR 0x31
314 #define IDE_COMMAND_WRITE48 0x34
315 #define IDE_COMMAND_WRITE_DMA48 0x35
316 #define IDE_COMMAND_WRITE_DMA_Q48 0x36
317 #define IDE_COMMAND_SET_NATIVE_SIZE48 0x37
318 #define IDE_COMMAND_WRITE_MUL48 0x39
319 #define IDE_COMMAND_WRITE_STREAM_DMA48 0x3a
320 #define IDE_COMMAND_WRITE_STREAM48 0x3b
321 #define IDE_COMMAND_WRITE_FUA_DMA48 0x3d
322 #define IDE_COMMAND_WRITE_FUA_DMA_Q48 0x3e
323 #define IDE_COMMAND_WRITE_LOG48 0x3f
324 #define IDE_COMMAND_VERIFY 0x40
325 #define IDE_COMMAND_VERIFY48 0x42
326 #define IDE_COMMAND_READ_LOG_DMA48 0x47
327 #define IDE_COMMAND_WRITE_LOG_DMA48 0x57
328 #define IDE_COMMAND_TRUSTED_RCV 0x5c
329 #define IDE_COMMAND_TRUSTED_RCV_DMA 0x5d
330 #define IDE_COMMAND_TRUSTED_SEND 0x5e
331 #define IDE_COMMAND_TRUSTED_SEND_DMA 0x5f
332 #define IDE_COMMAND_SEEK 0x70
333 #define IDE_COMMAND_SET_DRIVE_PARAMETERS 0x91
334 #define IDE_COMMAND_ATAPI_PACKET 0xA0
335 #define IDE_COMMAND_ATAPI_IDENTIFY 0xA1
336 #define IDE_COMMAND_READ_MULTIPLE 0xC4
337 #define IDE_COMMAND_WRITE_MULTIPLE 0xC5
338 #define IDE_COMMAND_SET_MULTIPLE 0xC6
339 #define IDE_COMMAND_READ_DMA_Q 0xC7
340 #define IDE_COMMAND_READ_DMA 0xC8
341 #define IDE_COMMAND_WRITE_DMA 0xCA
342 #define IDE_COMMAND_WRITE_DMA_Q 0xCC
343 #define IDE_COMMAND_WRITE_MUL_FUA48 0xCE
344 #define IDE_COMMAND_GET_MEDIA_STATUS 0xDA
345 #define IDE_COMMAND_DOOR_LOCK 0xDE
346 #define IDE_COMMAND_DOOR_UNLOCK 0xDF
347 #define IDE_COMMAND_STANDBY_IMMED 0xE0 // flush and spin down
348 #define IDE_COMMAND_STANDBY 0xE2 // flush and spin down and enable autopowerdown timer
349 #define IDE_COMMAND_SLEEP 0xE6 // flush, spin down and deactivate interface
350 #define IDE_COMMAND_FLUSH_CACHE 0xE7
351 #define IDE_COMMAND_IDENTIFY 0xEC
352 #define IDE_COMMAND_MEDIA_EJECT 0xED
353 #define IDE_COMMAND_FLUSH_CACHE48 0xEA
354 #define IDE_COMMAND_ENABLE_MEDIA_STATUS 0xEF
355 #define IDE_COMMAND_SET_FEATURES 0xEF /* features command,
356 IDE_COMMAND_ENABLE_MEDIA_STATUS */
357 #define IDE_COMMAND_READ_NATIVE_SIZE 0xF8
358 #define IDE_COMMAND_SET_NATIVE_SIZE 0xF9
359
360 #define SCSIOP_ATA_PASSTHROUGH 0xCC //
361
362 //
363 // IDE status definitions
364 //
365
366 #define IDE_STATUS_SUCCESS 0x00
367 #define IDE_STATUS_ERROR 0x01
368 #define IDE_STATUS_INDEX 0x02
369 #define IDE_STATUS_CORRECTED_ERROR 0x04
370 #define IDE_STATUS_DRQ 0x08
371 #define IDE_STATUS_DSC 0x10
372 //#define IDE_STATUS_DWF 0x10 /* drive write fault */
373 #define IDE_STATUS_DMA 0x20 /* DMA ready */
374 #define IDE_STATUS_DWF 0x20 /* drive write fault */
375 #define IDE_STATUS_DRDY 0x40
376 #define IDE_STATUS_IDLE 0x50
377 #define IDE_STATUS_BUSY 0x80
378
379
380 //
381 // IDE drive select/head definitions
382 //
383
384 #define IDE_DRIVE_SELECT 0xA0
385 #define IDE_DRIVE_1 0x00
386 #define IDE_DRIVE_2 0x10
387 #define IDE_DRIVE_SELECT_1 (IDE_DRIVE_SELECT | IDE_DRIVE_1)
388 #define IDE_DRIVE_SELECT_2 (IDE_DRIVE_SELECT | IDE_DRIVE_2)
389
390 #define IDE_USE_LBA 0x40
391
392 //
393 // IDE drive control definitions
394 //
395
396 #define IDE_DC_DISABLE_INTERRUPTS 0x02
397 #define IDE_DC_RESET_CONTROLLER 0x04
398 #define IDE_DC_A_4BIT 0x80
399 #define IDE_DC_USE_HOB 0x80 // use high-order byte(s)
400 #define IDE_DC_REENABLE_CONTROLLER 0x00
401
402 // IDE error definitions
403 //
404
405 #define IDE_ERROR_ICRC 0x80
406 #define IDE_ERROR_BAD_BLOCK 0x80
407 #define IDE_ERROR_DATA_ERROR 0x40
408 #define IDE_ERROR_MEDIA_CHANGE 0x20
409 #define IDE_ERROR_ID_NOT_FOUND 0x10
410 #define IDE_ERROR_MEDIA_CHANGE_REQ 0x08
411 #define IDE_ERROR_COMMAND_ABORTED 0x04
412 #define IDE_ERROR_END_OF_MEDIA 0x02
413 #define IDE_ERROR_NO_MEDIA 0x02
414 #define IDE_ERROR_ILLEGAL_LENGTH 0x01
415
416 //
417 // ATAPI register definition
418 //
419
420 typedef union _ATAPI_REGISTERS_1 {
421 struct _o {
422 UCHAR Data;
423 UCHAR Feature;
424 UCHAR Unused0;
425 UCHAR Unused1;
426 UCHAR ByteCountLow;
427 UCHAR ByteCountHigh;
428 UCHAR DriveSelect;
429 UCHAR Command;
430 } o;
431
432 struct _i {
433 UCHAR Data;
434 UCHAR Error;
435 UCHAR InterruptReason;
436 UCHAR Unused1;
437 UCHAR ByteCountLow;
438 UCHAR ByteCountHigh;
439 UCHAR DriveSelect;
440 UCHAR Status;
441 } i;
442
443 //IDE_REGISTERS_1 ide;
444
445 } ATAPI_REGISTERS_1, *PATAPI_REGISTERS_1;
446
447 #define IDX_ATAPI_IO1 IDX_IO1
448 #define IDX_ATAPI_IO1_SZ sizeof(ATAPI_REGISTERS_1)
449
450 #define IDX_ATAPI_IO1_i_Data (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Data )+IDX_ATAPI_IO1)
451 #define IDX_ATAPI_IO1_i_Error (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Error )+IDX_ATAPI_IO1)
452 #define IDX_ATAPI_IO1_i_InterruptReason (FIELD_OFFSET(ATAPI_REGISTERS_1, i.InterruptReason)+IDX_ATAPI_IO1)
453 #define IDX_ATAPI_IO1_i_Unused1 (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Unused1 )+IDX_ATAPI_IO1)
454 #define IDX_ATAPI_IO1_i_ByteCountLow (FIELD_OFFSET(ATAPI_REGISTERS_1, i.ByteCountLow )+IDX_ATAPI_IO1)
455 #define IDX_ATAPI_IO1_i_ByteCountHigh (FIELD_OFFSET(ATAPI_REGISTERS_1, i.ByteCountHigh )+IDX_ATAPI_IO1)
456 #define IDX_ATAPI_IO1_i_DriveSelect (FIELD_OFFSET(ATAPI_REGISTERS_1, i.DriveSelect )+IDX_ATAPI_IO1)
457 #define IDX_ATAPI_IO1_i_Status (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Status )+IDX_ATAPI_IO1)
458
459 #define IDX_ATAPI_IO1_o_Data (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Data )+IDX_ATAPI_IO1)
460 #define IDX_ATAPI_IO1_o_Feature (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Feature )+IDX_ATAPI_IO1)
461 #define IDX_ATAPI_IO1_o_Unused0 (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Unused0 )+IDX_ATAPI_IO1)
462 #define IDX_ATAPI_IO1_o_Unused1 (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Unused1 )+IDX_ATAPI_IO1)
463 #define IDX_ATAPI_IO1_o_ByteCountLow (FIELD_OFFSET(ATAPI_REGISTERS_1, o.ByteCountLow )+IDX_ATAPI_IO1)
464 #define IDX_ATAPI_IO1_o_ByteCountHigh (FIELD_OFFSET(ATAPI_REGISTERS_1, o.ByteCountHigh)+IDX_ATAPI_IO1)
465 #define IDX_ATAPI_IO1_o_DriveSelect (FIELD_OFFSET(ATAPI_REGISTERS_1, o.DriveSelect )+IDX_ATAPI_IO1)
466 #define IDX_ATAPI_IO1_o_Command (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Command )+IDX_ATAPI_IO1)
467
468 /*
469 typedef union _ATAPI_REGISTERS_2 {
470 struct {
471 UCHAR AltStatus;
472 UCHAR DriveAddress;
473 };
474
475 //IDE_REGISTERS_2 ide;
476
477 } ATAPI_REGISTERS_2, *PATAPI_REGISTERS_2;
478
479 #define IDX_ATAPI_IO2 IDX_ATAPI_IO2_SZ
480 #define IDX_ATAPI_IO2_SZ sizeof(ATAPI_REGISTERS_2)
481 */
482
483 //
484 // ATAPI interrupt reasons
485 //
486
487 #define ATAPI_IR_COD 0x01
488 #define ATAPI_IR_IO 0x02
489
490 //
491 // ATA Features
492 //
493
494 #define ATA_F_DMA 0x01 /* enable DMA */
495 #define ATA_F_OVL 0x02 /* enable overlap */
496
497 #define ATA_C_F_SETXFER 0x03 /* set transfer mode */
498
499 #define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */
500 #define ATA_C_F_DIS_WCACHE 0x82 /* disable write cache */
501
502 #define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */
503 #define ATA_C_F_DIS_RCACHE 0x55 /* disable readahead cache */
504
505 #define ATA_C_F_ENAB_RELIRQ 0x5d /* enable release interrupt */
506 #define ATA_C_F_DIS_RELIRQ 0xdd /* disable release interrupt */
507
508 #define ATA_C_F_ENAB_SRVIRQ 0x5e /* enable service interrupt */
509 #define ATA_C_F_DIS_SRVIRQ 0xde /* disable service interrupt */
510
511 #define ATA_C_F_ENAB_MEDIASTAT 0x95 /* enable media status */
512 #define ATA_C_F_DIS_MEDIASTAT 0x31 /* disable media status */
513
514 //
515 // ATAPI interrupt reasons
516 //
517
518 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
519 #define ATA_I_IN 0x02 /* read (1) | write (0) */
520 #define ATA_I_RELEASE 0x04 /* released bus (1) */
521 #define ATA_I_TAGMASK 0xf8 /* tag mask */
522
523 // IDENTIFY data
524 //
525
526 typedef struct _IDENTIFY_DATA {
527 UCHAR AtapiCmdSize:2; // 00 00
528 #define ATAPI_PSIZE_12 0 /* 12 bytes */
529 #define ATAPI_PSIZE_16 1 /* 16 bytes */
530 UCHAR :3;
531 UCHAR DrqType:2; // 00 00
532 #define ATAPI_DRQT_MPROC 0 /* cpu 3 ms delay */
533 #define ATAPI_DRQT_INTR 1 /* intr 10 ms delay */
534 #define ATAPI_DRQT_ACCEL 2 /* accel 50 us delay */
535 UCHAR Removable:1;
536
537 UCHAR DeviceType:5;
538 #define ATAPI_TYPE_DIRECT 0 /* disk/floppy */
539 #define ATAPI_TYPE_TAPE 1 /* streaming tape */
540 #define ATAPI_TYPE_CDROM 5 /* CD-ROM device */
541 #define ATAPI_TYPE_OPTICAL 7 /* optical disk */
542 UCHAR :1;
543 UCHAR CmdProtocol:2; // 00 00
544 #define ATAPI_PROTO_ATAPI 2
545 // USHORT GeneralConfiguration; // 00 00
546
547 USHORT NumberOfCylinders; // 02 1
548 USHORT Reserved1; // 04 2
549 USHORT NumberOfHeads; // 06 3
550 USHORT UnformattedBytesPerTrack; // 08 4 // Now obsolete
551 USHORT UnformattedBytesPerSector; // 0A 5 // Now obsolete
552 USHORT SectorsPerTrack; // 0C 6
553
554 USHORT VendorUnique1[3]; // 0E 7-9
555 UCHAR SerialNumber[20]; // 14 10-19
556
557 USHORT BufferType; // 28 20
558 #define ATA_BT_SINGLEPORTSECTOR 1 /* 1 port, 1 sector buffer */
559 #define ATA_BT_DUALPORTMULTI 2 /* 2 port, mult sector buffer */
560 #define ATA_BT_DUALPORTMULTICACHE 3 /* above plus track cache */
561
562 USHORT BufferSectorSize; // 2A 21
563 USHORT NumberOfEccBytes; // 2C 22
564 USHORT FirmwareRevision[4]; // 2E 23-26
565 USHORT ModelNumber[20]; // 36 27-46
566 UCHAR MaximumBlockTransfer; // 5E 47
567 UCHAR VendorUnique2; // 5F
568
569 USHORT DoubleWordIo; // 60 48
570
571 USHORT Reserved62_0:8; // 62 49
572 USHORT SupportDma:1;
573 USHORT SupportLba:1;
574 USHORT DisableIordy:1;
575 USHORT SupportIordy:1;
576 USHORT SoftReset:1;
577 USHORT StandbyOverlap:1;
578 USHORT SupportQTag:1; /* supports queuing overlap */
579 USHORT SupportIDma:1; /* interleaved DMA supported */
580 /* USHORT Capabilities; // 62 49
581 #define IDENTIFY_CAPABILITIES_SUPPORT_DMA 0x0100
582 #define IDENTIFY_CAPABILITIES_SUPPORT_LBA 0x0200
583 #define IDENTIFY_CAPABILITIES_DISABLE_IORDY 0x0400
584 #define IDENTIFY_CAPABILITIES_SUPPORT_IORDY 0x0800
585 #define IDENTIFY_CAPABILITIES_SOFT_RESET 0x1000
586 #define IDENTIFY_CAPABILITIES_STDBY_OVLP 0x2000
587 #define IDENTIFY_CAPABILITIES_SUPPORT_QTAG 0x4000
588 #define IDENTIFY_CAPABILITIES_SUPPORT_IDMA 0x8000*/
589
590 USHORT DeviceStandbyMin:1; // 64 50
591 USHORT Reserved50_1:13;
592 USHORT DeviceCapability1:1;
593 USHORT DeviceCapability0:1;
594 // USHORT Reserved2;
595
596 UCHAR Vendor51; // 66 51
597 UCHAR PioCycleTimingMode; // 67
598
599 UCHAR Vendor52; // 68 52
600 UCHAR DmaCycleTimingMode; // 69
601
602 USHORT TranslationFieldsValid:1; // 6A 53 /* 54-58 */
603 USHORT PioTimingsValid:1; /* 64-70 */
604 USHORT UdmaModesValid:1; /* 88 */
605 USHORT Reserved3:13;
606
607 USHORT NumberOfCurrentCylinders; // 6C 54 \-
608 USHORT NumberOfCurrentHeads; // 6E 55 \-
609 USHORT CurrentSectorsPerTrack; // 70 56 /- obsolete USHORT[5]
610 ULONG CurrentSectorCapacity; // 72 57-58 /-
611
612 USHORT CurrentMultiSector:8; // 59
613 USHORT CurrentMultiSectorValid:1;
614 USHORT Reserved59_9:7;
615
616 ULONG UserAddressableSectors; // 60-61
617
618 USHORT SingleWordDMASupport : 8; // 62 \- obsolete
619 USHORT SingleWordDMAActive : 8; // /-
620
621 USHORT MultiWordDMASupport : 8; // 63
622 USHORT MultiWordDMAActive : 8;
623
624 USHORT AdvancedPIOModes : 8; // 64
625 USHORT Reserved4 : 8;
626
627 #define AdvancedPIOModes_3 1
628 #define AdvancedPIOModes_4 2
629 #define AdvancedPIOModes_5 4 // non-standard
630
631 USHORT MinimumMWXferCycleTime; // 65
632 USHORT RecommendedMWXferCycleTime; // 66
633 USHORT MinimumPIOCycleTime; // 67
634 USHORT MinimumPIOCycleTimeIORDY; // 68
635
636 USHORT Reserved69_70[2]; // 69-70
637 USHORT ReleaseTimeOverlapped; // 71
638 USHORT ReleaseTimeServiceCommand; // 72
639 USHORT Reserved73_74[2]; // 73-74
640
641 USHORT QueueLength : 5; // 75
642 USHORT Reserved75_6 : 11;
643
644 USHORT SataCapabilities; // 76
645 #define ATA_SATA_GEN1 0x0002
646 #define ATA_SATA_GEN2 0x0004
647 #define ATA_SUPPORT_NCQ 0x0100
648 #define ATA_SUPPORT_IFPWRMNGTRCV 0x0200
649
650 USHORT Reserved77; // 77
651
652 USHORT SataSupport; // 78
653 #define ATA_SUPPORT_NONZERO 0x0002
654 #define ATA_SUPPORT_AUTOACTIVATE 0x0004
655 #define ATA_SUPPORT_IFPWRMNGT 0x0008
656 #define ATA_SUPPORT_INORDERDATA 0x0010
657
658 USHORT SataEnable; // 79
659 USHORT MajorRevision; // 80
660 USHORT MinorRevision; // 81
661
662 struct {
663 USHORT Smart:1; // 82/85
664 USHORT Security:1;
665 USHORT Removable:1;
666 USHORT PowerMngt:1;
667 USHORT Packet:1;
668 USHORT WriteCache:1;
669 USHORT LookAhead:1;
670 USHORT ReleaseDRQ:1;
671 USHORT ServiceDRQ:1;
672 USHORT Reset:1;
673 USHORT Protected:1;
674 USHORT Reserved_82_11:1;
675 USHORT WriteBuffer:1;
676 USHORT ReadBuffer:1;
677 USHORT Nop:1;
678 USHORT Reserved_82_15:1;
679
680 USHORT Microcode:1; // 83/86
681 USHORT Queued:1; //
682 USHORT CFA:1; //
683 USHORT APM:1; //
684 USHORT Notify:1; //
685 USHORT Standby:1; //
686 USHORT Spinup:1; //
687 USHORT Reserver_83_7:1;
688 USHORT MaxSecurity:1; //
689 USHORT AutoAcoustic:1; //
690 USHORT Address48:1; //
691 USHORT ConfigOverlay:1; //
692 USHORT FlushCache:1; //
693 USHORT FlushCache48:1; //
694 USHORT SupportOne:1; //
695 USHORT SupportZero:1; //
696
697 USHORT SmartErrorLog:1; // 84/87
698 USHORT SmartSelfTest:1;
699 USHORT MediaSerialNo:1;
700 USHORT MediaCardPass:1;
701 USHORT Streaming:1;
702 USHORT Logging:1;
703 USHORT Reserver_84_6:8;
704 USHORT ExtendedOne:1; //
705 USHORT ExtendedZero:1; //
706 } FeaturesSupport, FeaturesEnabled;
707
708 USHORT UltraDMASupport : 8; // 88
709 USHORT UltraDMAActive : 8;
710
711 USHORT EraseTime; // 89
712 USHORT EnhancedEraseTime; // 90
713 USHORT CurentAPMLevel; // 91
714
715 USHORT MasterPasswdRevision; // 92
716
717 USHORT HwResMaster : 8; // 93
718 USHORT HwResSlave : 5;
719 USHORT HwResCableId : 1;
720 USHORT HwResValid : 2;
721
722 USHORT CurrentAcoustic : 8; // 94
723 USHORT VendorAcoustic : 8;
724
725 USHORT StreamMinReqSize; // 95
726 USHORT StreamTransferTime; // 96
727 USHORT StreamAccessLatency; // 97
728 ULONG StreamGranularity; // 98-99
729
730 ULONGLONG UserAddressableSectors48; // 100-103
731
732 USHORT Reserved104[2]; // 104-105
733 union {
734 USHORT PhysLogSectorSize; // 106
735 struct {
736 USHORT PLSS_Size:4;
737 USHORT PLSS_Reserved:8;
738 USHORT PLSS_LargeL:1; // =1 if 117-118 are valid
739 USHORT PLSS_LargeP:1;
740 USHORT PLSS_Signature:2; // = 0x01 = 01b
741 };
742 };
743 USHORT Reserved107[10]; // 107-116
744
745 ULONG LargeSectorSize; // 117-118
746
747 USHORT Reserved117[8]; // 119-126
748
749 USHORT RemovableStatus; // 127
750 USHORT SecurityStatus; // 128
751
752 USHORT FeaturesSupport4; // 129
753 USHORT Reserved130[30]; // 130-159
754 USHORT CfAdvPowerMode; // 160
755 USHORT Reserved161[14]; // 161-175
756 USHORT MediaSerial[30]; // 176-205
757 USHORT Reserved206[49]; // 205-254
758 USHORT Integrity; // 255
759 } IDENTIFY_DATA, *PIDENTIFY_DATA;
760
761 //
762 // Identify data without the Reserved4.
763 //
764
765 #define IDENTIFY_DATA2 IDENTIFY_DATA
766 #define PIDENTIFY_DATA2 PIDENTIFY_DATA
767
768 /*typedef struct _IDENTIFY_DATA2 {
769 UCHAR AtapiCmdSize:2; // 00 00
770 UCHAR :3;
771 UCHAR DrqType:2; // 00 00
772 UCHAR Removable:1;
773
774 UCHAR DeviceType:5;
775 UCHAR :1;
776 UCHAR CmdProtocol:2; // 00 00
777 // USHORT GeneralConfiguration; // 00
778
779 USHORT NumberOfCylinders; // 02
780 USHORT Reserved1; // 04
781 USHORT NumberOfHeads; // 06
782 USHORT UnformattedBytesPerTrack; // 08
783 USHORT UnformattedBytesPerSector; // 0A
784 USHORT SectorsPerTrack; // 0C
785 USHORT VendorUnique1[3]; // 0E
786 UCHAR SerialNumber[20]; // 14
787 USHORT BufferType; // 28
788 USHORT BufferSectorSize; // 2A
789 USHORT NumberOfEccBytes; // 2C
790 USHORT FirmwareRevision[4]; // 2E
791 USHORT ModelNumber[20]; // 36
792 UCHAR MaximumBlockTransfer; // 5E
793 UCHAR VendorUnique2; // 5F
794 USHORT DoubleWordIo; // 60
795 USHORT Capabilities; // 62
796 USHORT Reserved2; // 64
797 UCHAR VendorUnique3; // 66
798 UCHAR PioCycleTimingMode; // 67
799 UCHAR VendorUnique4; // 68
800 UCHAR DmaCycleTimingMode; // 69
801 USHORT TranslationFieldsValid:1; // 6A
802 USHORT Reserved3:15;
803 USHORT NumberOfCurrentCylinders; // 6C
804 USHORT NumberOfCurrentHeads; // 6E
805 USHORT CurrentSectorsPerTrack; // 70
806 ULONG CurrentSectorCapacity; // 72
807 } IDENTIFY_DATA2, *PIDENTIFY_DATA2;*/
808
809 #define IDENTIFY_DATA_SIZE sizeof(IDENTIFY_DATA)
810
811 // IDENTIFY DMA timing cycle modes.
812 #define IDENTIFY_DMA_CYCLES_MODE_0 0x00
813 #define IDENTIFY_DMA_CYCLES_MODE_1 0x01
814 #define IDENTIFY_DMA_CYCLES_MODE_2 0x02
815 /*
816 #define PCI_DEV_HW_SPEC(idhi, idlo) \
817 { #idlo, 4, #idhi, 4}
818
819 typedef struct _BROKEN_CONTROLLER_INFORMATION {
820 PCHAR VendorId;
821 ULONG VendorIdLength;
822 PCHAR DeviceId;
823 ULONG DeviceIdLength;
824 }BROKEN_CONTROLLER_INFORMATION, *PBROKEN_CONTROLLER_INFORMATION;
825
826 BROKEN_CONTROLLER_INFORMATION const BrokenAdapters[] = {
827 // CMD 640 ATA controller !WARNING! buggy chip data loss possible
828 PCI_DEV_HW_SPEC( 0640, 1095 ), //{ "1095", 4, "0640", 4},
829 // ??
830 PCI_DEV_HW_SPEC( 0601, 1039 ), //{ "1039", 4, "0601", 4}
831 // RZ 100? ATA controller !WARNING! buggy chip data loss possible
832 PCI_DEV_HW_SPEC( 1000, 1042 ),
833 PCI_DEV_HW_SPEC( 1001, 1042 )
834 };
835
836 #define BROKEN_ADAPTERS (sizeof(BrokenAdapters) / sizeof(BROKEN_CONTROLLER_INFORMATION))
837
838 typedef struct _NATIVE_MODE_CONTROLLER_INFORMATION {
839 PCHAR VendorId;
840 ULONG VendorIdLength;
841 PCHAR DeviceId;
842 ULONG DeviceIdLength;
843 }NATIVE_MODE_CONTROLLER_INFORMATION, *PNATIVE_MODE_CONTROLLER_INFORMATION;
844
845 NATIVE_MODE_CONTROLLER_INFORMATION const NativeModeAdapters[] = {
846 PCI_DEV_HW_SPEC( 0105, 10ad ) //{ "10ad", 4, "0105", 4}
847 };
848
849 #define NUM_NATIVE_MODE_ADAPTERS (sizeof(NativeModeAdapters) / sizeof(NATIVE_MODE_CONTROLLER_INFORMATION))
850 */
851 //
852 // Beautification macros
853 //
854
855 #ifndef USER_MODE
856
857 #define GetStatus(chan, Status) \
858 Status = AtapiReadPort1(chan, IDX_IO2_AltStatus);
859
860 #define GetBaseStatus(chan, pStatus) \
861 pStatus = AtapiReadPort1(chan, IDX_IO1_i_Status);
862
863 #define WriteCommand(chan, _Command) \
864 AtapiWritePort1(chan, IDX_IO1_o_Command, _Command);
865
866
867 #define SelectDrive(chan, unit) { \
868 if(chan && chan->lun[unit] && chan->lun[unit]->DeviceFlags & DFLAGS_ATAPI_CHANGER) KdPrint3((" Select %d\n", unit)); \
869 AtapiWritePort1(chan, IDX_IO1_o_DriveSelect, (unit) ? IDE_DRIVE_SELECT_2 : IDE_DRIVE_SELECT_1); \
870 }
871
872
873 #define ReadBuffer(chan, Buffer, Count, timing) \
874 AtapiReadBuffer2(chan, IDX_IO1_i_Data, \
875 Buffer, \
876 Count, \
877 timing);
878
879 #define WriteBuffer(chan, Buffer, Count, timing) \
880 AtapiWriteBuffer2(chan, IDX_IO1_o_Data, \
881 Buffer, \
882 Count, \
883 timing);
884
885 #define ReadBuffer2(chan, Buffer, Count, timing) \
886 AtapiReadBuffer4(chan, IDX_IO1_i_Data, \
887 Buffer, \
888 Count, \
889 timing);
890
891 #define WriteBuffer2(chan, Buffer, Count, timing) \
892 AtapiWriteBuffer4(chan, IDX_IO1_o_Data, \
893 Buffer, \
894 Count, \
895 timing);
896
897 UCHAR
898 DDKFASTAPI
899 WaitOnBusy(
900 IN struct _HW_CHANNEL* chan/*,
901 PIDE_REGISTERS_2 BaseIoAddress*/
902 );
903
904 UCHAR
905 DDKFASTAPI
906 WaitOnBusyLong(
907 IN struct _HW_CHANNEL* chan/*,
908 PIDE_REGISTERS_2 BaseIoAddress*/
909 );
910
911 UCHAR
912 DDKFASTAPI
913 WaitOnBaseBusy(
914 IN struct _HW_CHANNEL* chan/*,
915 PIDE_REGISTERS_1 BaseIoAddress*/
916 );
917
918 UCHAR
919 DDKFASTAPI
920 WaitOnBaseBusyLong(
921 IN struct _HW_CHANNEL* chan/*,
922 PIDE_REGISTERS_1 BaseIoAddress*/
923 );
924
925 UCHAR
926 DDKFASTAPI
927 WaitForDrq(
928 IN struct _HW_CHANNEL* chan/*,
929 PIDE_REGISTERS_2 BaseIoAddress*/
930 );
931
932 UCHAR
933 DDKFASTAPI
934 WaitShortForDrq(
935 IN struct _HW_CHANNEL* chan/*,
936 PIDE_REGISTERS_2 BaseIoAddress*/
937 );
938
939 VOID
940 DDKFASTAPI
941 AtapiSoftReset(
942 IN struct _HW_CHANNEL* chan,/*
943 PIDE_REGISTERS_1 BaseIoAddress*/
944 ULONG DeviceNumber
945 );
946
947 /*#define IdeHardReset(BaseIoAddress,result) \
948 {\
949 UCHAR statusByte;\
950 ULONG i;\
951 SelectDrive(BaseIoAddress,DeviceNumber); \
952 AtapiWritePort1(&BaseIoAddress->AltStatus,IDE_DC_DISABLE_INTERRUPTS | IDE_DC_RESET_CONTROLLER );\
953 ScsiPortStallExecution(50 * 1000);\
954 AtapiWritePort1(&BaseIoAddress->AltStatus,IDE_DC_REENABLE_CONTROLLER);\
955 5 seconds for reset \
956 for (i = 0; i < 1000 * (1+11); i++) {\
957 statusByte = AtapiReadPort1(&BaseIoAddress->AltStatus);\
958 if (statusByte != IDE_STATUS_IDLE && statusByte != IDE_STATUS_SUCCESS) {\
959 ScsiPortStallExecution((i<1000) ? 5 : 500);\
960 } else {\
961 break;\
962 }\
963 }\
964 KdPrint2((PRINT_PREFIX "IdeHardReset: Status %x\n", statusByte)); \
965 if (i == 1000*1000) {\
966 result = FALSE;\
967 }\
968 result = TRUE;\
969 }*/
970
971 #endif //USER_MODE
972
973 #define IS_RDP(OperationCode)\
974 ((OperationCode == SCSIOP_ERASE)||\
975 (OperationCode == SCSIOP_LOAD_UNLOAD)||\
976 (OperationCode == SCSIOP_LOCATE)||\
977 (OperationCode == SCSIOP_REWIND) ||\
978 (OperationCode == SCSIOP_SPACE)||\
979 (OperationCode == SCSIOP_SEEK)||\
980 /* (OperationCode == SCSIOP_FORMAT_UNIT)||\
981 (OperationCode == SCSIOP_BLANK)||*/ \
982 (OperationCode == SCSIOP_WRITE_FILEMARKS))
983
984 #ifndef USER_MODE
985
986 PSCSI_REQUEST_BLOCK
987 NTAPI
988 BuildMechanismStatusSrb (
989 IN PVOID HwDeviceExtension,
990 IN PSCSI_REQUEST_BLOCK Srb
991 );
992
993 PSCSI_REQUEST_BLOCK
994 NTAPI
995 BuildRequestSenseSrb (
996 IN PVOID HwDeviceExtension,
997 IN PSCSI_REQUEST_BLOCK Srb
998 );
999
1000 VOID
1001 NTAPI
1002 AtapiHwInitializeChanger (
1003 IN PVOID HwDeviceExtension,
1004 IN ULONG TargetId,
1005 IN PMECHANICAL_STATUS_INFORMATION_HEADER MechanismStatus
1006 );
1007
1008 ULONG
1009 NTAPI
1010 AtapiSendCommand(
1011 IN PVOID HwDeviceExtension,
1012 IN PSCSI_REQUEST_BLOCK Srb,
1013 IN ULONG CmdAction
1014 );
1015
1016 ULONG
1017 NTAPI
1018 IdeSendCommand(
1019 IN PVOID HwDeviceExtension,
1020 IN PSCSI_REQUEST_BLOCK Srb,
1021 IN ULONG CmdAction
1022 );
1023
1024 #define AtapiCopyMemory RtlCopyMemory
1025
1026 VOID
1027 NTAPI
1028 AtapiHexToString (
1029 ULONG Value,
1030 PCHAR *Buffer
1031 );
1032
1033 #define AtapiStringCmp(s1, s2, n) _strnicmp(s1, s2, n)
1034
1035 BOOLEAN
1036 NTAPI
1037 AtapiInterrupt(
1038 IN PVOID HwDeviceExtension
1039 );
1040
1041 BOOLEAN
1042 NTAPI
1043 AtapiInterrupt__(
1044 IN PVOID HwDeviceExtension,
1045 IN UCHAR c
1046 );
1047
1048 BOOLEAN
1049 NTAPI
1050 AtapiHwInitialize(
1051 IN PVOID HwDeviceExtension
1052 );
1053
1054 ULONG
1055 NTAPI
1056 IdeBuildSenseBuffer(
1057 IN PVOID HwDeviceExtension,
1058 IN PSCSI_REQUEST_BLOCK Srb
1059 );
1060
1061 VOID
1062 NTAPI
1063 IdeMediaStatus(
1064 IN BOOLEAN EnableMSN,
1065 IN PVOID HwDeviceExtension,
1066 IN UCHAR Channel
1067 );
1068
1069 ULONG NTAPI
1070 AtapiFindController(
1071 IN PVOID HwDeviceExtension,
1072 IN PVOID Context,
1073 IN PVOID BusInformation,
1074 IN PCHAR ArgumentString,
1075 IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo,
1076 OUT PBOOLEAN Again
1077 );
1078
1079 ULONG
1080 NTAPI
1081 AtapiParseArgumentString(
1082 IN PCCH String,
1083 IN PCCH KeyWord
1084 );
1085
1086 BOOLEAN
1087 NTAPI
1088 IssueIdentify(
1089 IN PVOID HwDeviceExtension,
1090 IN ULONG DeviceNumber,
1091 IN ULONG Channel,
1092 IN UCHAR Command,
1093 IN BOOLEAN NoSetup
1094 );
1095
1096 BOOLEAN
1097 NTAPI
1098 SetDriveParameters(
1099 IN PVOID HwDeviceExtension,
1100 IN ULONG DeviceNumber,
1101 IN ULONG Channel
1102 );
1103
1104 ULONG
1105 NTAPI
1106 CheckDevice(
1107 IN PVOID HwDeviceExtension,
1108 IN ULONG Channel,
1109 IN ULONG deviceNumber,
1110 IN BOOLEAN ResetBus
1111 );
1112
1113 #define UNIATA_FIND_DEV_UNHIDE 0x01
1114
1115 BOOLEAN
1116 NTAPI
1117 FindDevices(
1118 IN PVOID HwDeviceExtension,
1119 IN ULONG Flags,
1120 IN ULONG Channel
1121 );
1122
1123 #endif //USER_MODE
1124
1125 #ifdef __cplusplus
1126 };
1127 #endif //__cplusplus
1128
1129 #ifndef USER_MODE
1130
1131 BOOLEAN
1132 NTAPI
1133 AtapiResetController(
1134 IN PVOID HwDeviceExtension,
1135 IN ULONG PathId
1136 );
1137
1138 BOOLEAN
1139 NTAPI
1140 AtapiStartIo(
1141 IN PVOID HwDeviceExtension,
1142 IN PSCSI_REQUEST_BLOCK Srb
1143 );
1144
1145 BOOLEAN
1146 NTAPI
1147 AtapiStartIo__(
1148 IN PVOID HwDeviceExtension,
1149 IN PSCSI_REQUEST_BLOCK Srb,
1150 IN BOOLEAN TopLevel
1151 );
1152
1153 extern UCHAR
1154 NTAPI
1155 AtaCommand48(
1156 // IN PVOID HwDeviceExtension,
1157 IN struct _HW_DEVICE_EXTENSION* deviceExtension,
1158 IN ULONG DeviceNumber,
1159 IN ULONG Channel,
1160 IN UCHAR command,
1161 IN ULONGLONG lba,
1162 IN USHORT count,
1163 IN USHORT feature,
1164 IN ULONG flags
1165 );
1166
1167 extern UCHAR
1168 NTAPI
1169 AtaCommand(
1170 // IN PVOID HwDeviceExtension,
1171 IN struct _HW_DEVICE_EXTENSION* deviceExtension,
1172 IN ULONG DeviceNumber,
1173 IN ULONG Channel,
1174 IN UCHAR command,
1175 IN USHORT cylinder,
1176 IN UCHAR head,
1177 IN UCHAR sector,
1178 IN UCHAR count,
1179 IN UCHAR feature,
1180 IN ULONG flags
1181 );
1182
1183 extern LONG
1184 NTAPI
1185 AtaPioMode(PIDENTIFY_DATA2 ident);
1186
1187 extern LONG
1188 NTAPI
1189 AtaWmode(PIDENTIFY_DATA2 ident);
1190
1191 extern LONG
1192 NTAPI
1193 AtaUmode(PIDENTIFY_DATA2 ident);
1194
1195 extern VOID
1196 NTAPI
1197 AtapiDpcDispatch(
1198 IN PKDPC Dpc,
1199 IN PVOID DeferredContext,
1200 IN PVOID SystemArgument1,
1201 IN PVOID SystemArgument2
1202 );
1203
1204 //#define AtaCommand(de, devn, chan, cmd, cyl, hd, sec, cnt, feat, flg)
1205
1206 extern LONG
1207 NTAPI
1208 AtaPio2Mode(LONG pio);
1209
1210 extern LONG
1211 NTAPI
1212 AtaPioMode(PIDENTIFY_DATA2 ident);
1213
1214 extern VOID
1215 NTAPI
1216 AtapiEnableInterrupts(
1217 IN PVOID HwDeviceExtension,
1218 IN ULONG c
1219 );
1220
1221 extern VOID
1222 NTAPI
1223 AtapiDisableInterrupts(
1224 IN PVOID HwDeviceExtension,
1225 IN ULONG c
1226 );
1227
1228 #define CHAN_NOT_SPECIFIED (0xffffffffL)
1229 #define CHAN_NOT_SPECIFIED_CHECK_CABLE (0xfffffffeL)
1230 #define DEVNUM_NOT_SPECIFIED (0xffffffffL)
1231 #define IOMODE_NOT_SPECIFIED (0xffffffffL)
1232
1233 extern ULONG
1234 NTAPI
1235 AtapiRegCheckDevValue(
1236 IN PVOID HwDeviceExtension,
1237 IN ULONG chan,
1238 IN ULONG dev,
1239 IN PCWSTR Name,
1240 IN ULONG Default
1241 );
1242
1243 extern ULONG
1244 NTAPI
1245 AtapiRegCheckParameterValue(
1246 IN PVOID HwDeviceExtension,
1247 IN PCWSTR PathSuffix,
1248 IN PCWSTR Name,
1249 IN ULONG Default
1250 );
1251
1252 extern ULONG g_LogToDisplay;
1253
1254 extern "C"
1255 VOID
1256 _cdecl
1257 _PrintNtConsole(
1258 PCCH DebugMessage,
1259 ...
1260 );
1261
1262 VOID
1263 NTAPI
1264 UniataInitMapBM(
1265 IN struct _HW_DEVICE_EXTENSION* deviceExtension,
1266 IN struct _IDE_BUSMASTER_REGISTERS* BaseIoAddressBM_0,
1267 IN BOOLEAN MemIo
1268 );
1269
1270 VOID
1271 NTAPI
1272 UniataInitMapBase(
1273 IN struct _HW_CHANNEL* chan,
1274 IN PIDE_REGISTERS_1 BaseIoAddress1,
1275 IN PIDE_REGISTERS_2 BaseIoAddress2
1276 );
1277
1278 VOID
1279 NTAPI
1280 UniataInitSyncBaseIO(
1281 IN struct _HW_CHANNEL* chan
1282 );
1283
1284 UCHAR
1285 DDKFASTAPI
1286 UniataIsIdle(
1287 IN struct _HW_DEVICE_EXTENSION* deviceExtension,
1288 IN UCHAR Status
1289 );
1290
1291 VOID
1292 NTAPI
1293 UniataDumpATARegs(
1294 IN struct _HW_CHANNEL* chan
1295 );
1296
1297 ULONG
1298 NTAPI
1299 EncodeVendorStr(
1300 OUT PWCHAR Buffer,
1301 IN PUCHAR Str,
1302 IN ULONG Length
1303 );
1304
1305 ULONGLONG
1306 NTAPI
1307 UniAtaCalculateLBARegsBack(
1308 struct _HW_LU_EXTENSION* LunExt,
1309 ULONGLONG lba
1310 );
1311
1312 BOOLEAN
1313 NTAPI
1314 UniataAnybodyHome(
1315 IN PVOID HwDeviceExtension,
1316 IN ULONG Channel,
1317 IN ULONG deviceNumber
1318 );
1319
1320 #define ATA_CMD_FLAG_LBAIOsupp 0x01
1321 #define ATA_CMD_FLAG_48supp 0x02
1322 #define ATA_CMD_FLAG_48 0x04
1323 #define ATA_CMD_FLAG_DMA 0x08
1324
1325 extern UCHAR AtaCommands48[256];
1326 extern UCHAR AtaCommandFlags[256];
1327
1328 #ifdef _DEBUG
1329 #define PrintNtConsole _PrintNtConsole
1330 #else //_DEBUG
1331 #define PrintNtConsole(x) {;}
1332 #endif //_DEBUG
1333
1334 #endif //USER_MODE
1335
1336 #pragma pack(pop)
1337
1338 #endif // __GLOBAL_H__
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