3 Copyright (c) 2002-2011 Alexander A. Telyatnikov (Alter)
9 This is the miniport driver for ATAPI IDE controllers
10 With Busmaster DMA support
13 Alexander A. Telyatnikov (Alter)
20 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 This module is a port from FreeBSD 4.3-6.1 ATA driver (ata-dma.c, ata-chipset.c) by
34 Søren Schmidt, Copyright (c) 1998-2008
36 Changed defaulting-to-generic-PIO/DMA policy
37 Added PIO settings for VIA
38 Optimized VIA/AMD/nVidia init part
39 Optimized Promise TX2 init part
40 Optimized Intel init part
41 by Alex A. Telyatnikov (Alter) (c) 2002-2007
48 static const ULONG valid_udma
[7] = {0,0,2,0,4,5,6};
50 static const CHAR retry_Wdma
[MAX_RETRIES
+1] = {2, 2, 2,-1,-1,-1};
51 static const CHAR retry_Udma
[MAX_RETRIES
+1] = {6, 2,-1,-1,-1,-1};
53 PHYSICAL_ADDRESS ph4gb
= {{0xFFFFFFFF, 0}};
58 IN PHW_DEVICE_EXTENSION deviceExtension
,
59 IN ULONG dev
, // physical device number (0-3)
66 IN PHW_DEVICE_EXTENSION deviceExtension
,
67 IN ULONG dev
, // physical device number (0-3)
74 IN PHW_DEVICE_EXTENSION deviceExtension
,
75 IN ULONG dev
, // physical device number (0-3)
82 IN PHW_DEVICE_EXTENSION deviceExtension
,
83 IN ULONG dev
, // physical device number (0-3)
90 IN PHW_DEVICE_EXTENSION deviceExtension
,
91 IN ULONG channel
// physical channel number (0-1)
94 #define ATAPI_DEVICE(de, ldev) (de->lun[ldev].DeviceFlags & DFLAGS_ATAPI_DEVICE)
99 IN PVOID HwDeviceExtension
,
100 IN PSCSI_REQUEST_BLOCK Srb
,
106 PHYSICAL_ADDRESS ph_addr
;
109 ph_addr
= MmGetPhysicalAddress(data
);
110 if(!ph_addru
&& ph_addr
.HighPart
) {
111 // do so until we add 64bit address support
112 // or some workaround
117 (*ph_addru
) = ph_addr
.HighPart
;
118 //addr = ScsiPortConvertPhysicalAddressToUlong(ph_addr);
119 addr
= ph_addr
.LowPart
;
120 if(!addr
&& !ph_addr
.HighPart
) {
125 *count
= sizeof(BM_DMA_ENTRY
)*ATA_DMA_ENTRIES
;
127 *count
= PAGE_SIZE
- (addr
& (PAGE_SIZE
-1));
130 } // end AtapiVirtToPhysAddr_()
135 IN PVOID HwDeviceExtension
,
136 IN PPORT_CONFIGURATION_INFORMATION ConfigInfo
,
137 IN ULONG lChannel
// logical channel,
141 PHW_DEVICE_EXTENSION deviceExtension
= (PHW_DEVICE_EXTENSION
)HwDeviceExtension
;
142 PHW_CHANNEL chan
= &(deviceExtension
->chan
[lChannel
]);
147 deviceExtension
->chan
[c
].CopyDmaBuffer
= FALSE
;
149 if(!deviceExtension
->Host64
&& (WinVer_Id() > WinVer_NT
)) {
150 KdPrint2((PRINT_PREFIX
"AtapiDmaAlloc: allocate tmp buffers below 4Gb\n"));
151 chan
->DB_PRD
= MmAllocateContiguousMemory(sizeof(((PATA_REQ
)NULL
)->dma_tab
), ph4gb
);
153 chan
->DB_PRD_PhAddr
= AtapiVirtToPhysAddr(HwDeviceExtension
, NULL
, (PUCHAR
)(chan
->DB_PRD
), &i
, &ph_addru
);
154 if(!chan
->DB_PRD_PhAddr
|| !i
|| ((LONG
)(chan
->DB_PRD_PhAddr
) == -1)) {
155 KdPrint2((PRINT_PREFIX
"AtapiDmaAlloc: No DB PRD BASE\n" ));
157 chan
->DB_PRD_PhAddr
= 0;
161 KdPrint2((PRINT_PREFIX
"AtapiDmaAlloc: No DB PRD below 4Gb\n" ));
165 chan
->DB_IO
= MmAllocateContiguousMemory(deviceExtension
->MaximumDmaTransferLength
, ph4gb
);
167 chan
->DB_IO_PhAddr
= AtapiVirtToPhysAddr(HwDeviceExtension
, NULL
, (PUCHAR
)(chan
->DB_IO
), &i
, &ph_addru
);
168 if(!chan
->DB_IO_PhAddr
|| !i
|| ((LONG
)(chan
->DB_IO_PhAddr
) == -1)) {
169 KdPrint2((PRINT_PREFIX
"AtapiDmaAlloc: No DB IO BASE\n" ));
171 MmFreeContiguousMemory(chan
->DB_PRD
);
173 chan
->DB_PRD_PhAddr
= 0;
175 chan
->DB_IO_PhAddr
= 0;
179 KdPrint2((PRINT_PREFIX
"AtapiDmaAlloc: No DB IO below 4Gb\n" ));
180 MmFreeContiguousMemory(chan
->DB_IO
);
187 if(deviceExtension
->HwFlags
& UNIATA_AHCI
) {
188 KdPrint2((PRINT_PREFIX
"AtapiDmaAlloc: AHCI\n" ));
189 if(chan
->AhciCtlBlock
) {
190 KdPrint2((PRINT_PREFIX
" already initialized %x\n", chan
->AhciCtlBlock
));
193 // Need 1K-byte alignment
194 chan
->AhciCtlBlock0
= (PIDE_AHCI_CHANNEL_CTL_BLOCK
)MmAllocateContiguousMemory(
195 sizeof(IDE_AHCI_CHANNEL_CTL_BLOCK
)+AHCI_CLB_ALIGNEMENT_MASK
,
197 if(chan
->AhciCtlBlock0
) {
200 ULONGLONG AhciCtlBlock64
;
203 AhciCtlBlock
= (PUCHAR
)chan
->AhciCtlBlock0
;
205 KdPrint2((PRINT_PREFIX
"AtapiDmaAlloc: CLP BASE %I64x\n", AhciCtlBlock64
));
207 AhciCtlBlock64
+= AHCI_CLB_ALIGNEMENT_MASK
;
208 AhciCtlBlock64
&= ~AHCI_CLB_ALIGNEMENT_MASK
;
210 KdPrint2((PRINT_PREFIX
"AtapiDmaAlloc: CLP BASE 1k-aligned %I64x\n", AhciCtlBlock64
));
212 chan
->AhciCtlBlock
= (PIDE_AHCI_CHANNEL_CTL_BLOCK
)AhciCtlBlock
;
214 chan
->AHCI_CTL_PhAddr
= AtapiVirtToPhysAddr(HwDeviceExtension
, NULL
, (PUCHAR
)(chan
->AhciCtlBlock
), &i
, &ph_addru
);
215 KdPrint2((PRINT_PREFIX
"AtapiDmaAlloc: CLP Phys BASE %I64x\n", chan
->AHCI_CTL_PhAddr
));
216 if(!chan
->AHCI_CTL_PhAddr
|| !i
|| ((LONG
)(chan
->AHCI_CTL_PhAddr
) == -1)) {
217 KdPrint2((PRINT_PREFIX
"AtapiDmaAlloc: No AHCI CLP BASE\n" ));
218 chan
->AhciCtlBlock
= NULL
;
219 chan
->AHCI_CTL_PhAddr
= 0;
223 KdPrint2((PRINT_PREFIX
"AtapiDmaAlloc: No AHCI CLP below 4Gb\n" ));
224 MmFreeContiguousMemory(chan
->AhciCtlBlock0
);
225 chan
->AhciCtlBlock
= NULL
;
226 chan
->AHCI_CTL_PhAddr
= 0;
230 KdPrint2((PRINT_PREFIX
"AtapiDmaAlloc: Can't alloc AHCI CLP\n"));
235 } // end AtapiDmaAlloc()
240 IN PVOID HwDeviceExtension
,
241 IN ULONG DeviceNumber
,
242 IN ULONG lChannel
, // logical channel,
243 IN PSCSI_REQUEST_BLOCK Srb
,
248 PHW_DEVICE_EXTENSION deviceExtension
= (PHW_DEVICE_EXTENSION
)HwDeviceExtension
;
249 ULONG dma_count
, dma_base
, dma_baseu
;
251 PHW_CHANNEL chan
= &(deviceExtension
->chan
[lChannel
]);
252 PATA_REQ AtaReq
= (PATA_REQ
)(Srb
->SrbExtension
);
253 BOOLEAN use_DB_IO
= FALSE
;
254 BOOLEAN use_AHCI
= (deviceExtension
->HwFlags
& UNIATA_AHCI
) ? TRUE
: FALSE
;
255 ULONG orig_count
= count
;
256 ULONG max_entries
= use_AHCI
? ATA_AHCI_DMA_ENTRIES
: ATA_DMA_ENTRIES
;
258 AtaReq
->Flags
&= ~REQ_FLAG_DMA_OPERATION
;
260 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: mode %#x, data %x, count %x, lCh %x, dev %x\n",
261 chan
->lun
[DeviceNumber
]->TransferMode
,
262 data
, count
, lChannel
, DeviceNumber
));
263 if(chan
->lun
[DeviceNumber
]->TransferMode
< ATA_DMA
) {
264 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: Not DMA mode, assume this is just preparation\n" ));
267 //KdPrint2((PRINT_PREFIX " checkpoint 1\n" ));
269 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: count=0\n" ));
272 //KdPrint2((PRINT_PREFIX " checkpoint 2\n" ));
273 if(count
> deviceExtension
->MaximumDmaTransferLength
) {
274 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: deviceExtension->MaximumDmaTransferLength > count\n" ));
277 //KdPrint2((PRINT_PREFIX " checkpoint 3\n" ));
278 if((ULONG
)data
& deviceExtension
->AlignmentMask
) {
279 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: unaligned data: %#x (%#x)\n", data
, deviceExtension
->AlignmentMask
));
283 //KdPrint2((PRINT_PREFIX " checkpoint 4\n" ));
285 KdPrint2((PRINT_PREFIX
" get Phys(AHCI_CMD=%x)\n", &(AtaReq
->ahci
.ahci_cmd_ptr
->prd_tab
) ));
286 dma_base
= AtapiVirtToPhysAddr(HwDeviceExtension
, NULL
, (PUCHAR
)&(AtaReq
->ahci
.ahci_cmd_ptr
->prd_tab
), &i
, &dma_baseu
);
287 AtaReq
->ahci
.ahci_base64
= NULL
; // clear before setup
289 KdPrint2((PRINT_PREFIX
" get Phys(PRD=%x)\n", &(AtaReq
->dma_tab
) ));
290 dma_base
= AtapiVirtToPhysAddr(HwDeviceExtension
, NULL
, (PUCHAR
)&(AtaReq
->dma_tab
) /*chan->dma_tab*/, &i
, &dma_baseu
);
293 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: SRB built-in PRD above 4Gb: %8.8x%8.8x\n", dma_baseu
, dma_base
));
294 if(!deviceExtension
->Host64
) {
295 dma_base
= chan
->DB_PRD_PhAddr
;
296 AtaReq
->Flags
|= REQ_FLAG_DMA_DBUF_PRD
;
300 if(!dma_base
|| !i
|| ((LONG
)(dma_base
) == -1)) {
301 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: No BASE\n" ));
304 AtaReq
->ata
.dma_base
= dma_base
; // aliased to ahci_base64
306 KdPrint2((PRINT_PREFIX
" get Phys(data=%x)\n", data
));
307 dma_base
= AtapiVirtToPhysAddr(HwDeviceExtension
, Srb
, data
, &dma_count
, &dma_baseu
);
309 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: 1st block of buffer above 4Gb: %8.8x%8.8x\n", dma_baseu
, dma_base
));
310 if(!deviceExtension
->Host64
) {
313 dma_base
= chan
->DB_IO_PhAddr
;
314 data
= (PUCHAR
)(chan
->DB_IO
);
316 AtaReq
->ahci
.ahci_base64
= (ULONGLONG
)dma_base
| ((ULONGLONG
)dma_baseu
<< 32);
319 if(!dma_count
|| ((LONG
)(dma_base
) == -1)) {
320 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: No 1st block\n" ));
321 //AtaReq->dma_base = NULL;
322 AtaReq
->ahci
.ahci_base64
= NULL
;
326 dma_count
= min(count
, (PAGE_SIZE
- ((ULONG
)data
& PAGE_MASK
)));
333 AtaReq
->ahci
.ahci_cmd_ptr
->prd_tab
[i
].base
= dma_base
;
334 AtaReq
->ahci
.ahci_cmd_ptr
->prd_tab
[i
].baseu
= dma_baseu
;
335 AtaReq
->ahci
.ahci_cmd_ptr
->prd_tab
[i
].DBC
= ((dma_count
-1) & 0x3fffff);
337 AtaReq
->dma_tab
[i
].base
= dma_base
;
338 AtaReq
->dma_tab
[i
].count
= (dma_count
& 0xffff);
341 if (i
>= max_entries
) {
342 KdPrint2((PRINT_PREFIX
"too many segments in DMA table\n" ));
343 //AtaReq->dma_base = NULL;
344 AtaReq
->ahci
.ahci_base64
= NULL
;
347 KdPrint2((PRINT_PREFIX
" get Phys(data[n]=%x)\n", data
));
348 dma_base
= AtapiVirtToPhysAddr(HwDeviceExtension
, Srb
, data
, &dma_count
, &dma_baseu
);
350 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: block of buffer above 4Gb: %8.8x%8.8x\n", dma_baseu
, dma_base
));
351 if(!deviceExtension
->Host64
) {
353 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: *ERROR* special buffer above 4Gb: %8.8x%8.8x\n", dma_baseu
, dma_base
));
360 if(!dma_count
|| !dma_base
|| ((LONG
)(dma_base
) == -1)) {
361 //AtaReq->dma_base = NULL;
362 AtaReq
->ahci
.ahci_base64
= 0;
363 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: No NEXT block\n" ));
367 dma_count
= min(count
, PAGE_SIZE
);
368 data
+= min(count
, PAGE_SIZE
);
369 count
-= min(count
, PAGE_SIZE
);
371 KdPrint2((PRINT_PREFIX
" set TERM\n" ));
373 AtaReq
->ahci
.ahci_cmd_ptr
->prd_tab
[i
].base
= dma_base
;
374 AtaReq
->ahci
.ahci_cmd_ptr
->prd_tab
[i
].baseu
= dma_baseu
;
375 AtaReq
->ahci
.ahci_cmd_ptr
->prd_tab
[i
].DBC
= ((dma_count
-1) & 0x3fffff);
377 AtaReq
->dma_tab
[i
].base
= dma_base
;
378 AtaReq
->dma_tab
[i
].count
= (dma_count
& 0xffff) | ATA_DMA_EOT
;
380 AtaReq
->dma_entries
= i
;
383 AtaReq
->Flags
|= REQ_FLAG_DMA_DBUF
;
385 AtaReq
->Flags
|= REQ_FLAG_DMA_OPERATION
;
387 KdPrint2((PRINT_PREFIX
"AtapiDmaSetup: OK\n" ));
390 } // end AtapiDmaSetup()
395 PVOID HwDeviceExtension
,
396 PSCSI_REQUEST_BLOCK Srb
,
402 PHW_DEVICE_EXTENSION deviceExtension
= (PHW_DEVICE_EXTENSION
)HwDeviceExtension
;
409 // This must never be called after DMA operation !!!
410 KdPrint2((PRINT_PREFIX
"AtapiDmaPioSync: data %#x, len %#x\n", data
, count
));
413 KdPrint2((PRINT_PREFIX
"AtapiDmaPioSync: !Srb\n" ));
417 AtaReq
= (PATA_REQ
)(Srb
->SrbExtension
);
419 // do nothing on PCI (This can be changed. We cannot guarantee,
420 // that CommonBuffer will always point to User's buffer,
421 // however, this usually happens on PCI-32)
422 if(deviceExtension
->OrigAdapterInterfaceType
== PCIBus
) {
425 // do nothing for DMA
426 if(AtaReq
->Flags
& REQ_FLAG_DMA_OPERATION
) {
431 KdPrint2((PRINT_PREFIX
"AtapiDmaPioSync: !data\n" ));
436 dma_base
= AtapiVirtToPhysAddr(HwDeviceExtension
, Srb
, data
, &dma_count
);
438 KdPrint2((PRINT_PREFIX
"AtapiDmaPioSync: !dma_base for data %#x\n", data
));
441 DmaBuffer
= (PUCHAR
)ScsiPortGetVirtualAddress(HwDeviceExtension
,
442 ScsiPortConvertUlongToPhysicalAddress(dma_base
));
444 KdPrint2((PRINT_PREFIX
"AtapiDmaPioSync: !DmaBuffer for dma_base %#x\n", dma_base
));
447 len
= min(dma_count
, count
);
448 memcpy(DmaBuffer
, data
, len
);
455 } // end AtapiDmaPioSync()
461 PSCSI_REQUEST_BLOCK Srb
466 AtaReq
= (PATA_REQ
)(Srb
->SrbExtension
);
467 if((Srb
->SrbFlags
& SRB_FLAGS_DATA_IN
) &&
468 (AtaReq
->Flags
& REQ_FLAG_DMA_DBUF
)) {
469 KdPrint2((PRINT_PREFIX
" AtapiDmaDBSync is issued.\n"));
471 KdPrint2((PRINT_PREFIX
" DBUF (Read)\n"));
472 RtlCopyMemory(AtaReq
->DataBuffer
, chan
->DB_IO
,
473 Srb
->DataTransferLength
);
476 } // end AtapiDmaDBSync()
481 IN PVOID HwDeviceExtension
,
482 IN ULONG DeviceNumber
,
483 IN ULONG lChannel
, // logical channel,
484 IN PSCSI_REQUEST_BLOCK Srb
487 PHW_DEVICE_EXTENSION deviceExtension
= (PHW_DEVICE_EXTENSION
)HwDeviceExtension
;
488 //PIDE_BUSMASTER_REGISTERS BaseIoAddressBM = deviceExtension->BaseIoAddressBM[lChannel];
489 PATA_REQ AtaReq
= (PATA_REQ
)(Srb
->SrbExtension
);
490 PHW_CHANNEL chan
= &deviceExtension
->chan
[lChannel
];
492 ULONG VendorID
= deviceExtension
->DevID
& 0xffff;
493 ULONG ChipType
= deviceExtension
->HwFlags
& CHIPTYPE_MASK
;
495 KdPrint2((PRINT_PREFIX
"AtapiDmaStart: %s on %#x:%#x\n",
496 (Srb
->SrbFlags
& SRB_FLAGS_DATA_IN
) ? "read" : "write",
497 lChannel
, DeviceNumber
));
499 if(!AtaReq
->ata
.dma_base
) {
500 KdPrint2((PRINT_PREFIX
"AtapiDmaStart: *** !AtaReq->ata.dma_base\n"));
503 if(AtaReq
->Flags
& REQ_FLAG_DMA_DBUF_PRD
) {
504 KdPrint2((PRINT_PREFIX
" DBUF_PRD\n"));
506 if(deviceExtension
->HwFlags
& UNIATA_AHCI
) {
507 RtlCopyMemory(chan
->DB_PRD
, AtaReq
->ahci
.ahci_cmd_ptr
, sizeof(AtaReq
->ahci_cmd0
));
509 RtlCopyMemory(chan
->DB_PRD
, &(AtaReq
->dma_tab
), sizeof(AtaReq
->dma_tab
));
512 if(!(Srb
->SrbFlags
& SRB_FLAGS_DATA_IN
) &&
513 (AtaReq
->Flags
& REQ_FLAG_DMA_DBUF
)) {
514 KdPrint2((PRINT_PREFIX
" DBUF (Write)\n"));
516 RtlCopyMemory(chan
->DB_IO
, AtaReq
->DataBuffer
,
517 Srb
->DataTransferLength
);
521 chan
->ChannelCtrlFlags
|= CTRFLAGS_DMA_ACTIVE
;
525 if(ChipType
== PRNEW
) {
526 ULONG Channel
= deviceExtension
->Channel
+ lChannel
;
527 if(chan
->ChannelCtrlFlags
& CTRFLAGS_LBA48
) {
528 AtapiWritePortEx1(chan
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
),0x11,
529 AtapiReadPortEx1(chan
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
),0x11) |
530 (Channel
? 0x08 : 0x02));
531 AtapiWritePortEx4(chan
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
),(Channel
? 0x24 : 0x20),
532 ((Srb
->SrbFlags
& SRB_FLAGS_DATA_IN
) ? 0x05000000 : 0x06000000) | (Srb
->DataTransferLength
>> 1)
537 if(deviceExtension->MemIo) {
539 AtapiWritePort4(chan,
541 (AtapiReadPort4(chan,
542 IDX_BM_Command) & ~0x000000c0) |
543 ((Srb->SrbFlags & SRB_FLAGS_DATA_IN) ? 0x00000080 : 0x000000c0) );
550 // set pointer to Pointer Table
551 AtapiWritePort4(chan
, IDX_BM_PRD_Table
,
554 // set transfer direction
555 AtapiWritePort1(chan
, IDX_BM_Command
,
556 (Srb
->SrbFlags
& SRB_FLAGS_DATA_IN
) ? BM_COMMAND_READ
: BM_COMMAND_WRITE
);
557 // clear Error & Intr bits (writeing 1 clears bits)
558 // set DMA capability bit
559 AtapiWritePort1(chan
, IDX_BM_Status
,
560 AtapiReadPort1(chan
, IDX_BM_Status
) |
561 (BM_STATUS_INTR
| BM_STATUS_ERR
) /*|
562 (DeviceNumber ? BM_STATUS_DRIVE_1_DMA : BM_STATUS_DRIVE_0_DMA)*/);
564 AtapiWritePort1(chan
, IDX_BM_Command
,
565 AtapiReadPort1(chan
, IDX_BM_Command
) |
566 BM_COMMAND_START_STOP
);
569 } // end AtapiDmaStart()
574 IN PVOID HwDeviceExtension
,
575 IN ULONG DeviceNumber
,
576 IN ULONG lChannel
, // logical channel,
577 IN PSCSI_REQUEST_BLOCK Srb
580 PHW_DEVICE_EXTENSION deviceExtension
= (PHW_DEVICE_EXTENSION
)HwDeviceExtension
;
581 //PIDE_BUSMASTER_REGISTERS BaseIoAddressBM = deviceExtension->BaseIoAddressBM[lChannel];
582 PHW_CHANNEL chan
= &deviceExtension
->chan
[lChannel
];
585 ULONG VendorID
= deviceExtension
->DevID
& 0xffff;
586 ULONG ChipType
= deviceExtension
->HwFlags
& CHIPTYPE_MASK
;
588 KdPrint2((PRINT_PREFIX
"AtapiDmaDone: dev %d\n", DeviceNumber
));
590 if(deviceExtension
->HwFlags
& UNIATA_AHCI
) {
591 KdPrint2((PRINT_PREFIX
" ACHTUNG! should not be called for AHCI!\n"));
597 if(ChipType
== PRNEW
) {
598 ULONG Channel
= deviceExtension
->Channel
+ lChannel
;
599 if(chan
->ChannelCtrlFlags
& CTRFLAGS_LBA48
) {
600 AtapiWritePortEx1(chan
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
),0x11,
601 AtapiReadPortEx1(chan
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
),0x11) &
602 ~(Channel
? 0x08 : 0x02));
603 AtapiWritePortEx4(chan
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
),(Channel
? 0x24 : 0x20),
609 if(deviceExtension->MemIo) {
611 AtapiWritePort4(chan,
613 (AtapiReadPort4(chan,
614 IDX_BM_Command) & ~0x00000080) );
616 chan->ChannelCtrlFlags &= ~CTRFLAGS_DMA_ACTIVE;
624 dma_status
= AtapiReadPort1(chan
, IDX_BM_Status
) & BM_STATUS_MASK
;
626 AtapiWritePort1(chan
, IDX_BM_Command
,
627 AtapiReadPort1(chan
, IDX_BM_Command
) &
628 ~BM_COMMAND_START_STOP
);
629 // clear interrupt and error status
630 AtapiWritePort1(chan
, IDX_BM_Status
, BM_STATUS_ERR
| BM_STATUS_INTR
);
632 chan
->ChannelCtrlFlags
&= ~CTRFLAGS_DMA_ACTIVE
;
636 } // end AtapiDmaDone()
641 IN PHW_DEVICE_EXTENSION deviceExtension
,
642 IN PHW_LU_EXTENSION LunExt
,
648 apiomode
= (CHAR
)AtaPioMode(&(LunExt
->IdentifyData
));
650 if(!(AtaReq
->Flags
& REQ_FLAG_DMA_OPERATION
)) {
651 KdPrint2((PRINT_PREFIX
652 "AtapiDmaReinit: !(AtaReq->Flags & REQ_FLAG_DMA_OPERATION), fall to PIO on Device %d\n", LunExt
->Lun
));
655 if(deviceExtension
->HwFlags
& UNIATA_AHCI
) {
656 if(!AtaReq
->ahci
.ahci_base64
) {
657 KdPrint2((PRINT_PREFIX
658 "AtapiDmaReinit: no AHCI PRD, fall to PIO on Device %d\n", LunExt
->Lun
));
662 if(!AtaReq
->ata
.dma_base
) {
663 KdPrint2((PRINT_PREFIX
664 "AtapiDmaReinit: no PRD, fall to PIO on Device %d\n", LunExt
->Lun
));
668 if((deviceExtension
->HbaCtrlFlags
& HBAFLAGS_DMA_DISABLED_LBA48
) &&
669 (AtaReq
->lba
>= (LONGLONG
)ATA_MAX_LBA28
) &&
670 (LunExt
->TransferMode
> ATA_PIO5
) ) {
671 KdPrint2((PRINT_PREFIX
672 "AtapiDmaReinit: FORCE_DOWNRATE on Device %d for LBA48\n", LunExt
->Lun
));
677 if(AtaReq
->Flags
& REQ_FLAG_FORCE_DOWNRATE
) {
678 KdPrint2((PRINT_PREFIX
679 "AtapiDmaReinit: FORCE_DOWNRATE on Device %d\n", LunExt
->Lun
));
680 if(AtaReq
->lba
>= (LONGLONG
)ATA_MAX_LBA28
) {
682 LunExt
->DeviceFlags
|= REQ_FLAG_FORCE_DOWNRATE_LBA48
;
684 // do not make extra work if we already use PIO
685 if(/*LunExt->TransferMode >= ATA_DMA*/
686 (LunExt
->TransferMode
> ATA_PIO5
) && (LunExt
->TransferMode
!= ATA_PIO0
+apiomode
)
688 KdPrint2((PRINT_PREFIX
689 "AtapiDmaReinit: set PIO mode on Device %d (%x -> %x)\n", LunExt
->Lun
, LunExt
->TransferMode
, ATA_PIO0
+apiomode
));
690 AtapiDmaInit(deviceExtension
, LunExt
->Lun
, LunExt
->chan
->lChannel
,
695 if(LunExt
->LimitedTransferMode
< LunExt
->TransferMode
) {
696 KdPrint2((PRINT_PREFIX
697 "AtapiDmaReinit: set PIO mode on Device %d (%x -> %x) (2)\n", LunExt
->Lun
, LunExt
->TransferMode
, LunExt
->LimitedTransferMode
));
698 AtapiDmaInit(deviceExtension
, LunExt
->Lun
, LunExt
->chan
->lChannel
,
699 LunExt
->LimitedTransferMode
-ATA_PIO0
,
705 KdPrint2((PRINT_PREFIX
706 "AtapiDmaReinit: set MAX mode on Device %d\n", LunExt
->Lun
));
707 AtapiDmaInit(deviceExtension
, LunExt
->Lun
, LunExt
->chan
->lChannel
,
709 min( retry_Wdma
[AtaReq
->retry
],
710 (CHAR
)AtaWmode(&(LunExt
->IdentifyData
)) ),
711 min( retry_Udma
[AtaReq
->retry
],
712 (CHAR
)AtaUmode(&(LunExt
->IdentifyData
)) ) );
714 // LunExt->DeviceFlags &= ~DFLAGS_FORCE_DOWNRATE;
716 if(/*!(LunExt->DeviceFlags & DFLAGS_FORCE_DOWNRATE) &&*/
717 (LunExt
->LimitedTransferMode
>
718 LunExt
->TransferMode
) ||
719 (LunExt
->DeviceFlags
& DFLAGS_REINIT_DMA
)) {
721 KdPrint2((PRINT_PREFIX
722 "AtapiDmaReinit: restore IO mode on Device %d\n", LunExt
->Lun
));
723 AtapiDmaInit__(deviceExtension
, LunExt
);
725 } // end AtapiDmaReinit()
730 IN PHW_DEVICE_EXTENSION deviceExtension
,
731 IN PHW_LU_EXTENSION LunExt
734 if(LunExt
->IdentifyData
.SupportDma
) {
735 KdPrint2((PRINT_PREFIX
736 "AtapiDmaInit__: Set (U)DMA on Device %d\n", LunExt
->Lun
));
737 /* for(i=AtaUmode(&(LunExt->IdentifyData)); i>=0; i--) {
738 AtapiDmaInit(deviceExtension, ldev & 1, ldev >> 1,
739 (CHAR)AtaPioMode(&(LunExt->IdentifyData)),
740 (CHAR)AtaWmode(&(LunExt->IdentifyData)),
741 UDMA_MODE0+(CHAR)i );
743 for(i=AtaWmode(&(LunExt->IdentifyData)); i>=0; i--) {
744 AtapiDmaInit(deviceExtension, ldev & 1, ldev >> 1,
745 (CHAR)AtaPioMode(&(LunExt->IdentifyData)),
746 (CHAR)AtaWmode(&(LunExt->IdentifyData)),
747 UDMA_MODE0+(CHAR)i );
749 AtapiDmaInit(deviceExtension
, LunExt
->Lun
, LunExt
->chan
->lChannel
,
750 (CHAR
)AtaPioMode(&(LunExt
->IdentifyData
)),
751 (CHAR
)AtaWmode(&(LunExt
->IdentifyData
)),
752 (CHAR
)AtaUmode(&(LunExt
->IdentifyData
)) );
754 KdPrint2((PRINT_PREFIX
755 "AtapiDmaInit__: Set PIO on Device %d\n", LunExt
->Lun
));
756 AtapiDmaInit(deviceExtension
, LunExt
->Lun
, LunExt
->chan
->lChannel
,
757 (CHAR
)AtaPioMode(&(LunExt
->IdentifyData
)), -1, -1);
759 } // end AtapiDmaInit__()
764 IN PHW_DEVICE_EXTENSION deviceExtension
,
765 IN ULONG DeviceNumber
,
766 IN ULONG lChannel
, // logical channel,
767 IN PHW_LU_EXTENSION LunExt
,
771 KdPrint3((PRINT_PREFIX
772 "AtaSetTransferMode: Set %#x on Device %d/%d\n", mode
, lChannel
, DeviceNumber
));
776 statusByte
= AtaCommand(deviceExtension
, DeviceNumber
, lChannel
,
777 IDE_COMMAND_SET_FEATURES
, 0, 0, 0,
778 (UCHAR
)((mode
> ATA_UDMA6
) ? ATA_UDMA6
: mode
), ATA_C_F_SETXFER
, ATA_WAIT_BASE_READY
);
779 if(statusByte
& IDE_STATUS_ERROR
) {
780 KdPrint3((PRINT_PREFIX
" wait ready after error\n"));
781 if(LunExt
->DeviceFlags
& DFLAGS_ATAPI_DEVICE
) {
782 AtapiStallExecution(10);
784 AtapiStallExecution(100);
786 apiomode
= (CHAR
)AtaPioMode(&(LunExt
->IdentifyData
));
787 if( (apiomode
> 0) &&
788 ((CHAR
)AtaWmode(&(LunExt
->IdentifyData
)) > 0) &&
789 ((CHAR
)AtaUmode(&(LunExt
->IdentifyData
)) > 0)
793 if(mode
> ATA_PIO2
) {
796 KdPrint3((PRINT_PREFIX
" assume that drive doesn't support mode swithing using PIO%d\n", apiomode
));
797 mode
= ATA_PIO0
+ apiomode
;
799 //if(mode <= ATA_UDMA6) {
800 LunExt
->TransferMode
= (UCHAR
)mode
;
803 } // end AtaSetTransferMode()
808 IN PVOID HwDeviceExtension
,
809 IN ULONG DeviceNumber
,
810 IN ULONG lChannel
, // logical channel,
811 // is always 0 except simplex-only controllers
817 PHW_DEVICE_EXTENSION deviceExtension
= (PHW_DEVICE_EXTENSION
)HwDeviceExtension
;
818 ULONG Channel
= deviceExtension
->Channel
+ lChannel
;
819 PHW_CHANNEL chan
= &deviceExtension
->chan
[lChannel
];
820 //LONG statusByte = 0;
821 ULONG dev
= Channel
*2 + DeviceNumber
; // for non-SATA/AHCI only!
822 ULONG ldev
= lChannel
*2 + DeviceNumber
; // for non-SATA/AHCI only!
823 ULONG slotNumber
= deviceExtension
->slotNumber
;
824 ULONG SystemIoBusNumber
= deviceExtension
->SystemIoBusNumber
;
826 PHW_LU_EXTENSION LunExt
= chan
->lun
[DeviceNumber
];
828 ULONG VendorID
= deviceExtension
->DevID
& 0xffff;
829 //ULONG DeviceID = (deviceExtension->DevID >> 16) & 0xffff;
830 //ULONG RevID = deviceExtension->RevID;
831 ULONG ChipType
= deviceExtension
->HwFlags
& CHIPTYPE_MASK
;
832 ULONG ChipFlags
= deviceExtension
->HwFlags
& CHIPFLAG_MASK
;
836 //UCHAR *reg_val = NULL;
838 LunExt
->DeviceFlags
&= ~DFLAGS_REINIT_DMA
;
839 /* set our most pessimistic default mode */
840 LunExt
->TransferMode
= ATA_PIO
;
841 // if(!deviceExtension->BaseIoAddressBM[lChannel]) {
842 if(!deviceExtension
->BusMaster
) {
843 KdPrint2((PRINT_PREFIX
" !deviceExtension->BusMaster: NO DMA\n"));
844 wdmamode
= udmamode
= -1;
847 // Limit transfer mode (controller limitation)
848 if((LONG
)deviceExtension
->MaxTransferMode
>= ATA_UDMA
) {
849 KdPrint2((PRINT_PREFIX
"AtapiDmaInit: deviceExtension->MaxTransferMode >= ATA_UDMA\n"));
850 udmamode
= min( udmamode
, (CHAR
)(deviceExtension
->MaxTransferMode
- ATA_UDMA
));
852 if((LONG
)deviceExtension
->MaxTransferMode
>= ATA_WDMA
) {
853 KdPrint2((PRINT_PREFIX
"AtapiDmaInit: deviceExtension->MaxTransferMode >= ATA_WDMA\n"));
855 wdmamode
= min( wdmamode
, (CHAR
)(deviceExtension
->MaxTransferMode
- ATA_WDMA
));
857 if((LONG
)deviceExtension
->MaxTransferMode
>= ATA_PIO0
) {
858 KdPrint2((PRINT_PREFIX
"AtapiDmaInit: NO DMA\n"));
859 wdmamode
= udmamode
= -1;
860 apiomode
= min( apiomode
, (CHAR
)(deviceExtension
->MaxTransferMode
- ATA_PIO0
));
862 KdPrint2((PRINT_PREFIX
"AtapiDmaInit: PIO0\n"));
863 wdmamode
= udmamode
= -1;
866 // Limit transfer mode (device limitation)
867 KdPrint2((PRINT_PREFIX
"AtapiDmaInit: LunExt->LimitedTransferMode %#x\n", LunExt
->LimitedTransferMode
));
868 if((LONG
)LunExt
->LimitedTransferMode
>= ATA_UDMA
) {
869 KdPrint2((PRINT_PREFIX
"AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => %#x\n",
870 min( udmamode
, (CHAR
)(LunExt
->LimitedTransferMode
- ATA_UDMA
))
872 udmamode
= min( udmamode
, (CHAR
)(LunExt
->LimitedTransferMode
- ATA_UDMA
));
874 if((LONG
)LunExt
->LimitedTransferMode
>= ATA_WDMA
) {
875 KdPrint2((PRINT_PREFIX
"AtapiDmaInit: LunExt->MaxTransferMode >= ATA_WDMA => %#x\n",
876 min( wdmamode
, (CHAR
)(LunExt
->LimitedTransferMode
- ATA_WDMA
))
879 wdmamode
= min( wdmamode
, (CHAR
)(LunExt
->LimitedTransferMode
- ATA_WDMA
));
881 if((LONG
)LunExt
->LimitedTransferMode
>= ATA_PIO0
) {
882 KdPrint2((PRINT_PREFIX
"AtapiDmaInit: lun NO DMA\n"));
883 wdmamode
= udmamode
= -1;
884 apiomode
= min( apiomode
, (CHAR
)(LunExt
->LimitedTransferMode
- ATA_PIO0
));
886 KdPrint2((PRINT_PREFIX
"AtapiDmaInit: lun PIO0\n"));
887 wdmamode
= udmamode
= -1;
891 SelectDrive(chan
, DeviceNumber
);
892 GetStatus(chan
, statusByte
);
893 // we can see here IDE_STATUS_ERROR status after previous operation
894 if(statusByte
& IDE_STATUS_ERROR
) {
895 KdPrint2((PRINT_PREFIX
"IDE_STATUS_ERROR detected on entry, statusByte = %#x\n", statusByte
));
896 //GetBaseStatus(chan, statusByte);
898 if(statusByte
&& UniataIsIdle(deviceExtension
, statusByte
& ~IDE_STATUS_ERROR
) != IDE_STATUS_IDLE
) {
899 KdPrint2((PRINT_PREFIX
"Can't setup transfer mode: statusByte = %#x\n", statusByte
));
903 if(deviceExtension
->UnknownDev
) {
904 KdPrint2((PRINT_PREFIX
"Unknown chip, omit Vendor/Dev checks\n"));
905 goto try_generic_dma
;
908 if(UniataIsSATARangeAvailable(deviceExtension
, lChannel
)) {
909 //if(ChipFlags & UNIATA_SATA) {
915 KdPrint2((PRINT_PREFIX
"SATA Generic\n"));
917 if(LunExt
->IdentifyData
.SataCapabilities
!= 0x0000 &&
918 LunExt
->IdentifyData
.SataCapabilities
!= 0xffff) {
919 //udmamode = min(udmamode, 6);
920 KdPrint2((PRINT_PREFIX
"LunExt->LimitedTransferMode %x, LunExt->OrigTransferMode %x\n",
921 LunExt
->LimitedTransferMode
, LunExt
->OrigTransferMode
));
922 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, min(LunExt
->LimitedTransferMode
, LunExt
->OrigTransferMode
))) {
925 udmamode
= min(udmamode
, 5);
928 KdPrint2((PRINT_PREFIX
"SATA -> PATA adapter ?\n"));
929 if (udmamode
> 2 && !LunExt
->IdentifyData
.HwResCableId
) {
930 KdPrint2((PRINT_PREFIX
"AtapiDmaInit: DMA limited to UDMA33, non-ATA66 compliant cable\n"));
932 apiomode
= min( apiomode
, (CHAR
)(LunExt
->LimitedTransferMode
- ATA_PIO0
));
934 udmamode
= min(udmamode
, 5);
939 ModeByte
= ATA_UDMA0
+ udmamode
;
942 ModeByte
= ATA_WDMA0
+ wdmamode
;
945 ModeByte
= ATA_PIO0
+ apiomode
;
950 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ModeByte
);
953 if(udmamode
> 2 && !LunExt
->IdentifyData
.HwResCableId
) {
954 KdPrint2((PRINT_PREFIX
"AtapiDmaInit: DMA limited to UDMA33, non-ATA66 compliant cable\n"));
956 apiomode
= min( apiomode
, (CHAR
)(LunExt
->LimitedTransferMode
- ATA_PIO
));
959 KdPrint2((PRINT_PREFIX
"Setup chip a:w:u=%d:%d:%d\n",
969 static const USHORT reg4a
= 0xa6;
970 UCHAR reg
= 0x40 + (UCHAR
)dev
;
972 if(ChipType
== ATPOLD
) {
974 static const USHORT reg4x
= 0x0301;
976 for(i
=udmamode
; i
>=0; i
--) {
977 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA
+ i
)) {
979 ChangePciConfig1(0x54, a
| (0x01 << dev
) | ((i
+1) << (dev
*2)));
980 SetPciConfig1(0x4a, reg4a
);
981 SetPciConfig2(reg
, reg4x
);
986 if (wdmamode
>= 2 && apiomode
>= 4) {
987 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA2
)) {
993 static const UCHAR reg4x
= 0x31;
995 for(i
=udmamode
; i
>=0; i
--) {
996 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA
+ i
)) {
998 ChangePciConfig2(0x44, (a
& ~(0x000f << (dev
* 4))) | ((i
+1) << (dev
*4)));
999 SetPciConfig1(0x4a, reg4a
);
1000 SetPciConfig1(reg
, reg4x
);
1005 if (wdmamode
>= 2 && apiomode
>= 4) {
1006 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA2
)) {
1011 /* Use GENERIC PIO */
1013 case ATA_ACER_LABS_ID
: {
1014 /************************/
1015 /* Acer Labs Inc. (ALI) */
1016 /************************/
1017 static const UCHAR ali_udma
[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f};
1018 static const ULONG ali_pio
[] =
1019 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
1020 0x00310001, 0x00440001};
1021 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */
1022 if ((ChipFlags
& ALIOLD
) &&
1023 (udmamode
>= 0 || wdmamode
>= 0)) {
1024 if(ATAPI_DEVICE(deviceExtension
, lChannel
*2) &&
1025 ATAPI_DEVICE(deviceExtension
, lChannel
*2 + 1)) {
1026 // 2 devices on this channel - NO DMA
1027 chan
->MaxTransferMode
=
1028 min(chan
->MaxTransferMode
, ATA_PIO4
);
1029 udmamode
= wdmamode
= -1;
1033 for(i
=udmamode
; i
>=0; i
--) {
1034 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1037 GetPciConfig4(0x54, word54
);
1038 word54
&= ~(0x000f000f << (dev
* 4));
1039 word54
|= (((ali_udma
[i
]<<16) | 5) << (dev
* 4));
1040 SetPciConfig4(0x54, word54
);
1041 ChangePciConfig1(0x53, a
| 0x03);
1042 SetPciConfig4(0x58 + (Channel
<<2), 0x00310001);
1046 /* make sure eventual UDMA mode from the BIOS is disabled */
1047 ChangePciConfig2(0x56, a
& ~(0x0008 << (dev
* 4)) );
1048 if (wdmamode
>= 2 && apiomode
>= 4) {
1049 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA2
)) {
1050 ChangePciConfig1(0x53, a
| 0x03);
1051 chan
->ChannelCtrlFlags
|= CTRFLAGS_DMA_RO
;
1055 ChangePciConfig1(0x53, (a
& ~0x01) | 0x02);
1057 for(i
=apiomode
; i
>=0; i
--) {
1058 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ i
)) {
1059 ChangePciConfig4(0x54, a
& ~(0x0008000f << (dev
* 4)));
1060 SetPciConfig4(0x58 + (Channel
<<2), ali_pio
[i
]);
1069 /********************/
1070 /* AMD, nVidia, VIA */
1071 /********************/
1072 if((VendorID
== ATA_VIA_ID
) &&
1073 (ChipFlags
& VIASATA
) &&
1075 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_SA150
);
1079 static const UCHAR via_modes
[5][7] = {
1080 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* ATA33 and New Chips */
1081 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* ATA66 */
1082 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* ATA100 */
1083 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
1084 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */
1085 static const UCHAR via_pio
[] =
1086 { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
1087 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1088 const UCHAR
*reg_val
= NULL
;
1089 UCHAR reg
= 0x53-(UCHAR
)dev
;
1091 reg_val
= &via_modes
[ChipType
][0];
1093 if(VendorID
== ATA_NVIDIA_ID
)
1096 for(i
= udmamode
; i
>=0; i
--) {
1097 SetPciConfig1(reg
-0x08, via_pio
[8+i
]);
1098 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1099 SetPciConfig1(reg
, (UCHAR
)reg_val
[i
]);
1103 if(!(ChipFlags
& VIABAR
)) {
1104 /* This chip can't do WDMA. */
1105 for(i
= wdmamode
; i
>=0; i
--) {
1106 SetPciConfig1(reg
-0x08, via_pio
[5+i
]);
1107 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1108 SetPciConfig1(reg
, 0x8b);
1113 /* set PIO mode timings */
1114 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1115 if((apiomode
>= 0) && (ChipType
!= VIA133
)) {
1116 SetPciConfig1(reg
-0x08, via_pio
[apiomode
]);
1118 via82c_timing(deviceExtension
, dev
, ATA_PIO0
+ apiomode
);
1119 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1123 case ATA_CYRIX_ID
: {
1127 ULONG cyr_piotiming
[] =
1128 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
1129 ULONG cyr_wdmatiming
[] = { 0x00077771, 0x00012121, 0x00002020 };
1130 ULONG cyr_udmatiming
[] = { 0x00921250, 0x00911140, 0x00911030 };
1131 ULONG mode_reg
= 0x24+(dev
<< 3);
1135 for(i
=udmamode
; i
>=0; i
--) {
1136 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1137 AtapiWritePortEx4(chan
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
), mode_reg
, cyr_udmatiming
[udmamode
]);
1141 for(i
=wdmamode
; i
>=0; i
--) {
1142 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1143 AtapiWritePortEx4(chan
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
), mode_reg
, cyr_wdmatiming
[wdmamode
]);
1147 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
)) {
1148 AtapiWritePortEx4(chan
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
), mode_reg
, cyr_piotiming
[apiomode
]);
1154 case ATA_NATIONAL_ID
: {
1158 ULONG nat_piotiming
[] =
1159 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
1160 0x00803020, 0x20102010, 0x00100010,
1161 0x00100010, 0x00100010, 0x00100010 };
1162 ULONG nat_dmatiming
[] = { 0x80077771, 0x80012121, 0x80002020 };
1163 ULONG nat_udmatiming
[] = { 0x80921250, 0x80911140, 0x80911030 };
1167 for(i
=udmamode
; i
>=0; i
--) {
1168 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1169 SetPciConfig4(0x44 + (dev
* 8), nat_udmatiming
[i
]);
1170 SetPciConfig4(0x40 + (dev
* 8), nat_piotiming
[i
+8]);
1174 for(i
=wdmamode
; i
>=0; i
--) {
1175 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1176 SetPciConfig4(0x44 + (dev
* 8), nat_dmatiming
[i
]);
1177 SetPciConfig4(0x40 + (dev
* 8), nat_piotiming
[i
+5]);
1181 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
)) {
1182 ChangePciConfig4(0x44 + (dev
* 8), a
| 0x80000000);
1183 SetPciConfig4(0x40 + (dev
* 8), nat_piotiming
[apiomode
]);
1186 /* Use GENERIC PIO */
1188 case ATA_CYPRESS_ID
:
1192 if (wdmamode
>= 2 && apiomode
>= 4) {
1193 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA2
)) {
1194 SetPciConfig2(Channel
? 0x4e:0x4c, 0x2020);
1198 /* Use GENERIC PIO */
1200 case ATA_MARVELL_ID
:
1204 for(i
=udmamode
; i
>=0; i
--) {
1205 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1209 for(i
=wdmamode
; i
>=0; i
--) {
1210 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1214 /* try generic DMA, use hpt_timing() */
1215 if (wdmamode
>= 0 && apiomode
>= 4) {
1216 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_DMA
)) {
1220 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1223 case ATA_NETCELL_ID
:
1227 if (wdmamode
>= 2 && apiomode
>= 4) {
1228 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA2
)) {
1232 /* Use GENERIC PIO */
1234 case ATA_HIGHPOINT_ID
: {
1235 /********************/
1236 /* High Point (HPT) */
1237 /********************/
1238 for(i
=udmamode
; i
>=0; i
--) {
1239 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1240 hpt_timing(deviceExtension
, dev
, (UCHAR
)(ATA_UDMA
+ i
)); // ???
1245 for(i
=wdmamode
; i
>=0; i
--) {
1246 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1247 hpt_timing(deviceExtension
, dev
, (UCHAR
)(ATA_WDMA0
+i
));
1251 /* try generic DMA, use hpt_timing() */
1252 if (wdmamode
>= 0 && apiomode
>= 4) {
1253 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_DMA
)) {
1257 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1258 hpt_timing(deviceExtension
, dev
, ATA_PIO0
+ apiomode
);
1261 case ATA_INTEL_ID
: {
1266 BOOLEAN udma_ok
= FALSE
;
1277 UCHAR intel_timings
[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
1278 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
1280 if(deviceExtension
->DevID
== ATA_I82371FB
) {
1281 if (wdmamode
>= 2 && apiomode
>= 4) {
1284 GetPciConfig4(0x40, word40
);
1285 word40
>>= Channel
* 16;
1287 /* Check for timing config usable for DMA on controller */
1288 if (!((word40
& 0x3300) == 0x2300 &&
1289 ((word40
>> ((!(DeviceNumber
& 1)) ? 0 : 4)) & 1) == 1)) {
1290 udmamode
= wdmamode
= -1;
1294 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA2
)) {
1301 if(deviceExtension
->DevID
== ATA_ISCH
) {
1303 GetPciConfig4(0x80 + dev
*4, tim
);
1305 for(i
=udmamode
; i
>=0; i
--) {
1306 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1308 tim
&= ~(0x7 << 16);
1313 apiomode
= ATA_PIO4
;
1318 for(i
=wdmamode
; i
>=0; i
--) {
1319 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1320 tim
&= ~(0x1 << 31);
1326 apiomode
= (i
== 0) ? ATA_PIO0
:
1327 (i
== 1) ? ATA_PIO3
: ATA_PIO4
;
1333 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1337 tim
|= (apiomode
& 0x7);
1338 SetPciConfig4(0x80 + dev
*4, tim
);
1343 GetPciConfig2(0x48, reg48
);
1344 if(!(ChipFlags
& ICH4_FIX
)) {
1345 GetPciConfig2(0x4a, reg4a
);
1347 GetPciConfig2(0x54, reg54
);
1348 // if(udmamode >= 0) {
1349 // enable the write buffer to be used in a split (ping/pong) manner.
1355 // reg40 &= ~0x00ff00ff;
1356 // reg40 |= 0x40774077;
1358 for(i
=udmamode
; i
>=0; i
--) {
1359 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1361 /* Set UDMA reference clock (33/66/133MHz). */
1362 SetPciConfig1(0x48, reg48
| (0x0001 << dev
));
1363 if(!(ChipFlags
& ICH4_FIX
)) {
1364 SetPciConfig2(0x4a, (reg4a
& ~(0x3 << (dev
<<2))) |
1365 (0x01 + !(i
& 0x01)) );
1368 reg54
|= (0x1 << dev
);
1370 reg54
&= ~(0x1 << dev
);
1373 reg54
|= (0x1000 << dev
);
1375 reg54
&= ~(0x1000 << dev
);
1377 SetPciConfig2(0x54, reg54
);
1381 if(ChipFlags
& ICH4_FIX
) {
1389 SetPciConfig1(0x48, reg48
& ~(0x0001 << dev
));
1390 if(!(ChipFlags
& ICH4_FIX
)) {
1391 SetPciConfig2(0x4a, (reg4a
& ~(0x3 << (dev
<< 2))) );
1393 SetPciConfig2(0x54, reg54
& ~(0x1001 << dev
));
1394 for(i
=wdmamode
; i
>=0; i
--) {
1395 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1398 if(ChipFlags
& ICH4_FIX
) {
1407 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1411 GetPciConfig4(0x40, reg40
);
1412 GetPciConfig1(0x44, reg44
);
1414 /* Allow PIO/WDMA timing controls. */
1415 reg40
&= ~0x00ff00ff;
1416 reg40
|= ~0x40774077;
1417 /* Set PIO/WDMA timings. */
1418 if(!(DeviceNumber
& 1)) {
1419 mask40
|= 0x00003300;
1420 new40
= ((USHORT
)(intel_timings
[idx
]) << 8);
1423 new44
= ((intel_timings
[idx
] & 0x30) >> 2) |
1424 (intel_timings
[idx
] & 0x03);
1434 SetPciConfig4(0x40, (reg40
& ~mask40
) | new40
);
1435 SetPciConfig1(0x44, (reg44
& ~mask44
) | new44
);
1439 case ATA_PROMISE_ID
:
1443 if(ChipType
< PRTX
) {
1444 if (ATAPI_DEVICE(deviceExtension
, ldev
)) {
1449 for(i
=udmamode
; i
>=0; i
--) {
1450 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1451 promise_timing(deviceExtension
, dev
, (UCHAR
)(ATA_UDMA
+ i
)); // ???
1456 for(i
=wdmamode
; i
>=0; i
--) {
1457 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1458 promise_timing(deviceExtension
, dev
, (UCHAR
)(ATA_WDMA0
+i
));
1462 /* try generic DMA, use hpt_timing() */
1463 if (wdmamode
>= 0 && apiomode
>= 4) {
1464 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_DMA
)) {
1468 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1469 promise_timing(deviceExtension
, dev
, ATA_PIO0
+ apiomode
);
1474 KdPrint2((PRINT_PREFIX
"ATI\n"));
1475 if(ChipType
== SIIMIO
) {
1476 goto l_ATA_SILICON_IMAGE_ID
;
1478 //goto ATA_SERVERWORKS_ID;
1483 case ATA_SERVERWORKS_ID
: {
1487 // static const ULONG udma_modes[] = { 0x70, 0x21, 0x20 };
1488 static const ULONG sw_dma_modes
[] = { 0x70, 0x21, 0x20 };
1489 static const ULONG sw_pio_modes
[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
1490 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1494 ULONG offset
= dev
^ 0x01;
1495 ULONG bit_offset
= offset
* 8;
1497 for(i
=udmamode
; i
>=0; i
--) {
1498 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1499 GetPciConfig2(0x56, reg56
);
1500 reg56
&= ~(0xf << (dev
* 4));
1501 reg56
|= ((USHORT
)i
<< (dev
* 4));
1502 SetPciConfig2(0x56, reg56
);
1503 ChangePciConfig1(0x54, a
| (0x01 << dev
));
1505 GetPciConfig4(0x44, reg44
);
1506 reg44
= (reg44
& ~(0xff << bit_offset
)) |
1507 (sw_dma_modes
[2] << bit_offset
);
1508 SetPciConfig4(0x44, reg44
);
1510 GetPciConfig4(0x40, reg40
);
1511 reg40
= (reg40
& ~(0xff << bit_offset
)) |
1512 (sw_pio_modes
[8+i
] << bit_offset
);
1513 SetPciConfig4(0x40, reg40
);
1518 for(i
=wdmamode
; i
>=0; i
--) {
1519 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1521 ChangePciConfig1(0x54, a
& ~(0x01 << dev
));
1523 GetPciConfig4(0x44, reg44
);
1524 reg44
= (reg44
& ~(0xff << bit_offset
)) |
1525 (sw_dma_modes
[wdmamode
] << bit_offset
);
1526 SetPciConfig4(0x44, reg44
);
1528 GetPciConfig4(0x40, reg40
);
1529 reg40
= (reg40
& ~(0xff << bit_offset
)) |
1530 (sw_pio_modes
[5+i
] << bit_offset
);
1531 SetPciConfig4(0x40, reg40
);
1535 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1536 // SetPciConfig4(0x44, sw_pio_modes[apiomode]);
1537 if(VendorID
== ATA_ATI_ID
) {
1538 // special case for ATI
1539 // Seems, that PATA ATI are just re-brended ServerWorks
1542 GetPciConfig2(0x4a, reg4a
);
1543 reg4a
= (reg4a
& ~(0xf << (dev
*4))) |
1544 (apiomode
<< (dev
*4));
1545 SetPciConfig2(0x4a, reg4a
);
1549 GetPciConfig4(0x40, reg40
);
1550 reg40
= (reg40
& ~(0xff << bit_offset
)) |
1551 (sw_pio_modes
[apiomode
] << bit_offset
);
1552 SetPciConfig4(0x40, reg40
);
1555 case ATA_SILICON_IMAGE_ID
: {
1556 l_ATA_SILICON_IMAGE_ID
:
1557 /********************/
1558 /* SiliconImage/CMD */
1559 /********************/
1560 if(ChipType
== SIIMIO
) {
1562 static const UCHAR sil_modes
[7] =
1563 { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
1564 static const USHORT sil_wdma_modes
[3] =
1565 { 0x2208, 0x10c2, 0x10c1 };
1566 static const USHORT sil_pio_modes
[6] =
1567 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1, 0x10c1 };
1569 UCHAR ureg
= 0xac + ((UCHAR
)DeviceNumber
* 0x02) + ((UCHAR
)Channel
* 0x10);
1571 UCHAR mreg
= Channel
? 0x84 : 0x80;
1572 UCHAR mask
= DeviceNumber
? 0x30 : 0x03;
1575 GetPciConfig1(ureg
, uval
);
1576 GetPciConfig1(mreg
, mode
);
1578 /* enable UDMA mode */
1579 for(i
= udmamode
; i
>=0; i
--) {
1581 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1582 SetPciConfig1(mreg
, mode
| mask
);
1583 SetPciConfig1(ureg
, (uval
& 0x3f) | sil_modes
[i
]);
1587 /* enable WDMA mode */
1588 for(i
= wdmamode
; i
>=0; i
--) {
1590 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1591 SetPciConfig1(mreg
, mode
| (mask
& 0x22));
1592 SetPciConfig2(ureg
- 0x4, sil_wdma_modes
[i
]);
1596 /* restore PIO mode */
1597 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1599 SetPciConfig1(mreg
, mode
| (mask
& 0x11));
1600 SetPciConfig2(ureg
- 0x8, sil_pio_modes
[apiomode
]);
1605 static const UCHAR cmd_modes
[2][6] = {
1606 { 0x31, 0x21, 0x011, 0x25, 0x15, 0x05 },
1607 { 0xc2, 0x82, 0x042, 0x8a, 0x4a, 0x0a } };
1608 static const UCHAR cmd_wdma_modes
[] = { 0x87, 0x32, 0x3f };
1609 static const UCHAR cmd_pio_modes
[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
1610 ULONG treg
= 0x54 + (dev
< 3) ? (dev
<< 1) : 7;
1612 udmamode
= min(udmamode
, 5);
1613 /* enable UDMA mode */
1614 for(i
= udmamode
; i
>=0; i
--) {
1617 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1618 GetPciConfig1(Channel
? 0x7b : 0x73, umode
);
1619 umode
&= ~(!(DeviceNumber
& 1) ? 0x35 : 0xca);
1620 umode
|= ( cmd_modes
[DeviceNumber
& 1][i
]);
1621 SetPciConfig1(Channel
? 0x7b : 0x73, umode
);
1625 /* make sure eventual UDMA mode from the BIOS is disabled */
1626 ChangePciConfig1(Channel
? 0x7b : 0x73, a
& ~(!(DeviceNumber
& 1) ? 0x35 : 0xca));
1628 for(i
= wdmamode
; i
>=0; i
--) {
1630 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1631 SetPciConfig1(treg
, cmd_wdma_modes
[i
]);
1632 ChangePciConfig1(Channel
? 0x7b : 0x73, a
& ~(!(DeviceNumber
& 1) ? 0x35 : 0xca));
1636 /* set PIO mode timings */
1637 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1639 SetPciConfig1(treg
, cmd_pio_modes
[apiomode
]);
1640 ChangePciConfig1(Channel
? 0x7b : 0x73, a
& ~(!(DeviceNumber
& 1) ? 0x35 : 0xca));
1650 PULONG sis_modes
= NULL
;
1651 static const ULONG sis_modes_new133
[] =
1652 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
1653 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
1654 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
1655 static const ULONG sis_modes_old133
[] =
1656 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
1657 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
1658 static const ULONG sis_modes_old
[] =
1659 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303, 0x0301,
1660 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
1661 static const ULONG sis_modes_new100
[] =
1662 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
1663 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
1672 sis_modes
= (PULONG
)(&sis_modes_new133
[0]);
1674 GetPciConfig1(0x57, reg57
);
1675 reg
= (reg57
& 0x40 ? 0x70 : 0x40) + (dev
* 4);
1678 sis_modes
= (PULONG
)(&sis_modes_old133
[0]);
1680 reg
= 0x40 + (dev
* 2);
1683 sis_modes
= (PULONG
)(&sis_modes_new100
[0]);
1685 reg
= 0x40 + (dev
* 2);
1690 sis_modes
= (PULONG
)(&sis_modes_old
[0]);
1692 reg
= 0x40 + (dev
* 2);
1697 for(i
=udmamode
; i
>=0; i
--) {
1698 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1700 SetPciConfig4(reg
, sis_modes
[offs
+i
]);
1702 SetPciConfig2(reg
, (USHORT
)sis_modes
[offs
+i
]);
1709 for(i
=wdmamode
; i
>=0; i
--) {
1710 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1712 SetPciConfig4(reg
, sis_modes
[offs
+i
]);
1714 SetPciConfig2(reg
, (USHORT
)sis_modes
[offs
+i
]);
1719 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1721 SetPciConfig4(reg
, sis_modes
[apiomode
]);
1723 SetPciConfig2(reg
, (USHORT
)sis_modes
[apiomode
]);
1728 /* Cenatek Rocket Drive controller */
1729 if (wdmamode
>= 0 &&
1730 (AtapiReadPort1(chan
, IDX_BM_Status
) &
1731 (DeviceNumber
? BM_STATUS_DRIVE_1_DMA
: BM_STATUS_DRIVE_0_DMA
))) {
1732 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ wdmamode
);
1734 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1737 case ATA_ITE_ID
: { /* ITE IDE controller */
1739 if(ChipType
== ITE_33
) {
1740 int a_speed
= 3 << (dev
* 4);
1741 int u_flag
= 1 << dev
;
1745 USHORT drive_enables
;
1748 GetPciConfig1(0x48, reg48
);
1749 GetPciConfig1(0x4a, reg4a
);
1752 * Setting the DMA cycle time to 2 or 3 PCI clocks (60 and 91 nsec
1753 * at 33 MHz PCI clock) seems to cause BadCRC errors during DMA
1754 * transfers on some drives, even though both numbers meet the minimum
1755 * ATAPI-4 spec of 73 and 54 nsec for UDMA 1 and 2 respectively.
1756 * So the faster times are just commented out here. The good news is
1757 * that the slower cycle time has very little affect on transfer
1761 for(i
=udmamode
; i
>=0; i
--) {
1762 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1763 SetPciConfig1(0x48, reg48
| u_flag
);
1765 SetPciConfig1(0x4a, reg4a
| u_speed
);
1767 goto setup_drive_ite
;
1771 for(i
=wdmamode
; i
>=0; i
--) {
1772 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1773 SetPciConfig1(0x48, reg48
& ~u_flag
);
1774 SetPciConfig1(0x4a, reg4a
& ~a_speed
);
1779 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1780 SetPciConfig1(0x48, reg48
& ~u_flag
);
1781 SetPciConfig1(0x4a, reg4a
& ~a_speed
);
1787 GetPciConfig2(0x40, drive_enables
);
1788 GetPciConfig4(0x44, drive_timing
);
1791 * FIX! The DIOR/DIOW pulse width and recovery times in port 0x44
1792 * are being left at the default values of 8 PCI clocks (242 nsec
1793 * for a 33 MHz clock). These can be safely shortened at higher
1794 * PIO modes. The DIOR/DIOW pulse width and recovery times only
1795 * apply to PIO modes, not to the DMA modes.
1799 * Enable port 0x44. The IT8172G spec is confused; it calls
1800 * this register the "Slave IDE Timing Register", but in fact,
1801 * it controls timing for both master and slave drives.
1803 drive_enables
|= 0x4000;
1805 drive_enables
&= (0xc000 | (0x06 << (DeviceNumber
*4)));
1807 /* enable prefetch and IORDY sample-point */
1808 drive_enables
|= (0x06 << (DeviceNumber
*4));
1811 SetPciConfig2(0x40, drive_enables
);
1813 if(ChipType
== ITE_133
) {
1814 static const UCHAR udmatiming
[] =
1815 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 };
1816 static const UCHAR chtiming
[] =
1817 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 };
1818 ULONG offset
= (Channel
<<2) + DeviceNumber
;
1821 for(i
=udmamode
; i
>=0; i
--) {
1822 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1823 ChangePciConfig1(0x50, a
& ~(1 << (dev
+ 3)) );
1824 SetPciConfig1(0x56 + offset
, udmatiming
[i
]);
1829 for(i
=wdmamode
; i
>=0; i
--) {
1830 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1832 ChangePciConfig1(0x50, a
| (1 << (dev
+ 3)) );
1833 GetPciConfig1(0x54 + offset
, reg54
);
1834 if(reg54
< chtiming
[i
+5]) {
1835 SetPciConfig1(0x54 + offset
, chtiming
[i
+5]);
1840 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1841 ChangePciConfig1(0x50, a
| (1 << (dev
+ 3)) );
1842 GetPciConfig1(0x54 + offset
, reg54
);
1843 if(reg54
< chtiming
[apiomode
]) {
1844 SetPciConfig1(0x54 + offset
, chtiming
[apiomode
]);
1848 if(ChipType
== ITE_133_NEW
) {
1849 //static const USHORT reg54_timings[] = { 0x0000, 0x0000, 0x0001, 0x0001, 0x0001, 0x1001, 0x1001 };
1850 static const UCHAR udmatiming
[] =
1851 { 0x00, 0x01, 0x10, 0x01, 0x10, 0x01, 0x10 };
1852 static const UCHAR timings
[] =
1853 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
1854 0x23, 0x23, 0x23, 0x23, 0x23, 0x02, 0x02 };
1855 BOOLEAN udma_ok
= FALSE
;
1863 USHORT mask40
=0, new40
=0;
1864 UCHAR mask44
=0, new44
=0;
1866 GetPciConfig2(0x40, reg40
);
1867 GetPciConfig1(0x44, reg44
);
1868 GetPciConfig2(0x4a, reg4a
);
1869 GetPciConfig2(0x54, reg54
);
1871 if(!(reg54
& (0x10 << dev
))) {
1873 udmamode
= min(udmamode
, 2);
1876 for(i
=udmamode
; i
>=0; i
--) {
1877 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1878 ChangePciConfig1(0x48, a
| (1 << dev
) );
1879 ChangePciConfig2(0x4a,
1880 (a
& ~(0x3 << (dev
*4))) |
1881 (udmatiming
[i
] << (dev
*4)) );
1884 timing
= timings
[i
+8];
1889 for(i
=wdmamode
; !ok
&& i
>=0; i
--) {
1890 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1893 timing
= timings
[i
+5];
1899 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1900 timing
= timings
[apiomode
];
1904 ChangePciConfig1(0x48, a
& ~(1 << dev
) );
1905 ChangePciConfig2(0x4a, a
& ~(0x3 << (dev
<< 2)) );
1907 if (udma_ok
&& udmamode
>= ATA_UDMA2
) {
1908 reg54
|= (0x1 << dev
);
1910 reg54
&= ~(0x1 << dev
);
1912 if (udma_ok
&& udmamode
>= ATA_UDMA5
) {
1913 reg54
|= (0x1000 << dev
);
1915 reg54
&= ~(0x1000 << dev
);
1917 SetPciConfig2(0x54, reg54
);
1923 reg40
|= (ATAPI_DEVICE(deviceExtension
, ldev
) ? 0x04 : 0x00);
1925 new40
= timing
<< 8;
1927 reg40
|= (ATAPI_DEVICE(deviceExtension
, ldev
) ? 0x40 : 0x00);
1929 new44
= ((timing
& 0x30) >> 2) |
1932 SetPciConfig2(0x40, (reg40
& ~mask40
) | new40
);
1933 SetPciConfig1(0x44, (reg44
& ~mask44
) | new44
);
1940 /* HiNT Corp. VXPro II EIDE */
1941 if (wdmamode
>= 0 &&
1942 (AtapiReadPort1(chan
, IDX_BM_Status
) &
1943 (DeviceNumber
? BM_STATUS_DRIVE_1_DMA
: BM_STATUS_DRIVE_0_DMA
))) {
1944 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_DMA
);
1946 AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
);
1949 case ATA_JMICRON_ID
: {
1952 GetPciConfig1(0x40, reg40
);
1956 udmamode
= min(udmamode
, 2);
1958 /* Nothing to do to setup mode, the controller snoop SET_FEATURE cmd. */
1961 for(i
=udmamode
; i
>=0; i
--) {
1962 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_UDMA0
+ i
)) {
1966 for(i
=wdmamode
; i
>=0; i
--) {
1967 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_WDMA0
+ i
)) {
1971 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
)) {
1980 /* unknown controller chip */
1982 /* better not try generic DMA on ATAPI devices it almost never works */
1983 if (ATAPI_DEVICE(deviceExtension
, ldev
)) {
1984 KdPrint2((PRINT_PREFIX
"ATAPI on unknown controller -> PIO\n"));
1989 /* if controller says its setup for DMA take the easy way out */
1990 /* the downside is we dont know what DMA mode we are in */
1991 if ((udmamode
>= 0 || /*wdmamode > 1*/ wdmamode
>= 0) &&
1992 /*deviceExtension->BaseIoAddressBM[lChannel]*/ deviceExtension
->BusMaster
&&
1993 (GetDmaStatus(deviceExtension
, lChannel
) &
1995 BM_STATUS_DRIVE_0_DMA
: BM_STATUS_DRIVE_1_DMA
))) {
1996 // LunExt->TransferMode = ATA_DMA;
1998 KdPrint2((PRINT_PREFIX
"try DMA on unknown controller\n"));
1999 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_DMA
)) {
2005 /* well, we have no support for this, but try anyways */
2006 if ((wdmamode
>= 0 && apiomode
>= 4) && deviceExtension
->BaseIoAddressBM
[lChannel
]) {
2007 if(AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_DMA
/* + wdmamode*/)) {
2013 KdPrint2((PRINT_PREFIX
"try PIO%d on unknown controller\n", apiomode
));
2014 if(!AtaSetTransferMode(deviceExtension
, DeviceNumber
, lChannel
, LunExt
, ATA_PIO0
+ apiomode
)) {
2015 KdPrint2((PRINT_PREFIX
"fall to PIO on unknown controller\n"));
2016 LunExt
->TransferMode
= ATA_PIO
;
2019 } // end AtapiDmaInit()
2025 IN PHW_DEVICE_EXTENSION deviceExtension
,
2026 IN ULONG dev
, // physical device number (0-3)
2030 // ASSERT(dev/2 >= deviceExtension->Channel);
2031 // PHW_CHANNEL chan = &(deviceExtension->chan[dev/2-deviceExtension->Channel]);
2032 ULONG reg20
= 0x0000e132;
2033 ULONG reg24
= 0x00017771;
2035 if(mode
== ATA_PIO5
)
2039 case ATA_PIO0
: reg20
= 0x0000e132; break;
2040 case ATA_PIO1
: reg20
= 0x00018121; break;
2041 case ATA_PIO2
: reg20
= 0x00024020; break;
2042 case ATA_PIO3
: reg20
= 0x00032010; break;
2044 case ATA_PIO5
: reg20
= 0x00040010; break;
2045 case ATA_WDMA2
: reg24
= 0x00002020; break;
2046 case ATA_UDMA2
: reg24
= 0x00911030; break;
2048 AtapiWritePortEx4(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
),(dev
*8) + 0x20, reg20
);
2049 AtapiWritePortEx4(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
),(dev
*8) + 0x24, reg24
);
2055 IN PHW_DEVICE_EXTENSION deviceExtension
,
2056 IN ULONG dev
, // physical device number (0-3)
2060 PVOID HwDeviceExtension
= (PVOID
)deviceExtension
;
2061 ULONG slotNumber
= deviceExtension
->slotNumber
;
2062 ULONG SystemIoBusNumber
= deviceExtension
->SystemIoBusNumber
;
2064 ULONG ChipType
= deviceExtension
->HwFlags
& CHIPTYPE_MASK
;
2065 //ULONG ChipFlags = deviceExtension->HwFlags & CHIPFLAG_MASK;
2069 if(mode
== ATA_PIO5
)
2076 case ATA_PIO0
: timing
= 0x004ff329; break;
2077 case ATA_PIO1
: timing
= 0x004fec25; break;
2078 case ATA_PIO2
: timing
= 0x004fe823; break;
2079 case ATA_PIO3
: timing
= 0x004fe622; break;
2080 case ATA_PIO4
: timing
= 0x004fe421; break;
2081 case ATA_WDMA0
: timing
= 0x004567f3; break;
2082 case ATA_WDMA1
: timing
= 0x004467f3; break;
2083 case ATA_WDMA2
: timing
= 0x004367f3; break;
2084 case ATA_UDMA0
: timing
= 0x004367f3; break;
2085 case ATA_UDMA1
: timing
= 0x004247f3; break;
2086 case ATA_UDMA2
: timing
= 0x004127f3; break;
2093 case ATA_PIO0
: timing
= 0x004fff2f; break;
2094 case ATA_PIO1
: timing
= 0x004ff82a; break;
2095 case ATA_PIO2
: timing
= 0x004ff026; break;
2096 case ATA_PIO3
: timing
= 0x004fec24; break;
2097 case ATA_PIO4
: timing
= 0x004fe822; break;
2098 case ATA_WDMA0
: timing
= 0x004acef6; break;
2099 case ATA_WDMA1
: timing
= 0x0048cef6; break;
2100 case ATA_WDMA2
: timing
= 0x0046cef6; break;
2101 case ATA_UDMA0
: timing
= 0x0046cef6; break;
2102 case ATA_UDMA1
: timing
= 0x00448ef6; break;
2103 case ATA_UDMA2
: timing
= 0x00436ef6; break;
2104 case ATA_UDMA3
: timing
= 0x00424ef6; break;
2105 case ATA_UDMA4
: timing
= 0x004127f3; break;
2106 case ATA_UDMA5
: timing
= 0x004127f3; break;
2112 SetPciConfig4(0x60 + (dev
<<2), timing
);
2113 } // end promise_timing()
2119 IN PHW_DEVICE_EXTENSION deviceExtension
,
2120 IN ULONG dev
, // physical device number (0-3)
2124 PVOID HwDeviceExtension
= (PVOID
)deviceExtension
;
2125 ULONG slotNumber
= deviceExtension
->slotNumber
;
2126 ULONG SystemIoBusNumber
= deviceExtension
->SystemIoBusNumber
;
2128 ULONG ChipType
= deviceExtension
->HwFlags
& CHIPTYPE_MASK
;
2129 //ULONG ChipFlags = deviceExtension->HwFlags & CHIPFLAG_MASK;
2133 if(mode
== ATA_PIO5
)
2139 switch (mode
) { /* HPT374 */
2140 case ATA_PIO0
: timing
= 0x0ac1f48a; break;
2141 case ATA_PIO1
: timing
= 0x0ac1f465; break;
2142 case ATA_PIO2
: timing
= 0x0a81f454; break;
2143 case ATA_PIO3
: timing
= 0x0a81f443; break;
2144 case ATA_PIO4
: timing
= 0x0a81f442; break;
2145 case ATA_WDMA0
: timing
= 0x228082ea; break;
2146 case ATA_WDMA1
: timing
= 0x22808254; break;
2147 case ATA_WDMA2
: timing
= 0x22808242; break;
2148 case ATA_UDMA0
: timing
= 0x121882ea; break;
2149 case ATA_UDMA1
: timing
= 0x12148254; break;
2150 case ATA_UDMA2
: timing
= 0x120c8242; break;
2151 case ATA_UDMA3
: timing
= 0x128c8242; break;
2152 case ATA_UDMA4
: timing
= 0x12ac8242; break;
2153 case ATA_UDMA5
: timing
= 0x12848242; break;
2154 case ATA_UDMA6
: timing
= 0x12808242; break;
2155 default: timing
= 0x0d029d5e;
2161 switch (mode
) { /* HPT372 */
2162 case ATA_PIO0
: timing
= 0x0d029d5e; break;
2163 case ATA_PIO1
: timing
= 0x0d029d26; break;
2164 case ATA_PIO2
: timing
= 0x0c829ca6; break;
2165 case ATA_PIO3
: timing
= 0x0c829c84; break;
2166 case ATA_PIO4
: timing
= 0x0c829c62; break;
2167 case ATA_WDMA0
: timing
= 0x2c82922e; break;
2168 case ATA_WDMA1
: timing
= 0x2c829266; break;
2169 case ATA_WDMA2
: timing
= 0x2c829262; break;
2170 case ATA_UDMA0
: timing
= 0x1c829c62; break;
2171 case ATA_UDMA1
: timing
= 0x1c9a9c62; break;
2172 case ATA_UDMA2
: timing
= 0x1c929c62; break;
2173 case ATA_UDMA3
: timing
= 0x1c8e9c62; break;
2174 case ATA_UDMA4
: timing
= 0x1c8a9c62; break;
2175 case ATA_UDMA5
: timing
= 0x1c8a9c62; break;
2176 case ATA_UDMA6
: timing
= 0x1c869c62; break;
2177 default: timing
= 0x0d029d5e;
2183 switch (mode
) { /* HPT370 */
2184 case ATA_PIO0
: timing
= 0x06914e57; break;
2185 case ATA_PIO1
: timing
= 0x06914e43; break;
2186 case ATA_PIO2
: timing
= 0x06514e33; break;
2187 case ATA_PIO3
: timing
= 0x06514e22; break;
2188 case ATA_PIO4
: timing
= 0x06514e21; break;
2189 case ATA_WDMA0
: timing
= 0x26514e97; break;
2190 case ATA_WDMA1
: timing
= 0x26514e33; break;
2191 case ATA_WDMA2
: timing
= 0x26514e21; break;
2192 case ATA_UDMA0
: timing
= 0x16514e31; break;
2193 case ATA_UDMA1
: timing
= 0x164d4e31; break;
2194 case ATA_UDMA2
: timing
= 0x16494e31; break;
2195 case ATA_UDMA3
: timing
= 0x166d4e31; break;
2196 case ATA_UDMA4
: timing
= 0x16454e31; break;
2197 case ATA_UDMA5
: timing
= 0x16454e31; break;
2198 default: timing
= 0x06514e57;
2204 GetPciConfig1(0x41 + (dev
<< 2), reg41
);
2207 case 0x85: /* 25Mhz */
2209 case ATA_PIO0
: timing
= 0x40d08585; break;
2210 case ATA_PIO1
: timing
= 0x40d08572; break;
2211 case ATA_PIO2
: timing
= 0x40ca8542; break;
2212 case ATA_PIO3
: timing
= 0x40ca8532; break;
2213 case ATA_PIO4
: timing
= 0x40ca8521; break;
2214 case ATA_WDMA2
: timing
= 0x20ca8521; break;
2215 case ATA_UDMA2
: timing
= 0x10cf8521; break;
2216 case ATA_UDMA4
: timing
= 0x10c98521; break;
2217 default: timing
= 0x01208585;
2221 case 0xa7: /* 33MHz */
2223 case ATA_PIO0
: timing
= 0x40d0a7aa; break;
2224 case ATA_PIO1
: timing
= 0x40d0a7a3; break;
2225 case ATA_PIO2
: timing
= 0x40d0a753; break;
2226 case ATA_PIO3
: timing
= 0x40c8a742; break;
2227 case ATA_PIO4
: timing
= 0x40c8a731; break;
2228 case ATA_WDMA0
: timing
= 0x20c8a797; break;
2229 case ATA_WDMA1
: timing
= 0x20c8a732; break;
2230 case ATA_WDMA2
: timing
= 0x20c8a731; break;
2231 case ATA_UDMA0
: timing
= 0x10c8a731; break;
2232 case ATA_UDMA1
: timing
= 0x10cba731; break;
2233 case ATA_UDMA2
: timing
= 0x10caa731; break;
2234 case ATA_UDMA3
: timing
= 0x10cfa731; break;
2235 case ATA_UDMA4
: timing
= 0x10c9a731; break;
2236 default: timing
= 0x0120a7a7;
2239 case 0xd9: /* 40Mhz */
2241 case ATA_PIO0
: timing
= 0x4018d9d9; break;
2242 case ATA_PIO1
: timing
= 0x4010d9c7; break;
2243 case ATA_PIO2
: timing
= 0x4010d997; break;
2244 case ATA_PIO3
: timing
= 0x4010d974; break;
2245 case ATA_PIO4
: timing
= 0x4008d963; break;
2246 case ATA_WDMA2
: timing
= 0x2008d943; break;
2247 case ATA_UDMA2
: timing
= 0x100bd943; break;
2248 case ATA_UDMA4
: timing
= 0x100fd943; break;
2249 default: timing
= 0x0120d9d9;
2255 SetPciConfig4(0x40 + (dev
<<2), timing
);
2256 } // end hpt_timing()
2259 #define FIT(v,min,max) (((v)>(max)?(max):(v))<(min)?(min):(v))
2264 IN PHW_DEVICE_EXTENSION deviceExtension
,
2265 IN ULONG dev
, // physical device number (0-3)
2269 PVOID HwDeviceExtension
= (PVOID
)deviceExtension
;
2270 ULONG slotNumber
= deviceExtension
->slotNumber
;
2271 ULONG SystemIoBusNumber
= deviceExtension
->SystemIoBusNumber
;
2273 USHORT T
= 1000 / /* PciBusClockMHz()*/ 33;
2284 case ATA_PIO0
: setup
= 70; active
= 165; recover
= 150; cycle
= 600; break;
2285 case ATA_PIO1
: setup
= 50; active
= 125; recover
= 100; cycle
= 383; break;
2286 case ATA_PIO2
: setup
= 30; active
= 100; recover
= 90; cycle
= 240; break;
2287 case ATA_PIO3
: setup
= 30; active
= 80; recover
= 70; cycle
= 180; break;
2288 case ATA_PIO4
: setup
= 25; active
= 70; recover
= 25; cycle
= 120; break;
2289 case ATA_PIO5
: setup
= 20; active
= 50; recover
= 30; cycle
= 100; break;
2292 setup
= (setup
-1)/(T
+1);
2293 active
= (active
-1)/(T
+1);
2294 recover
= (recover
-1)/(T
+1);
2295 cycle
= (cycle
-1)/(T
+1);
2297 if (active
+ recover
< cycle
) {
2298 active
+= (cycle
- (active
+ recover
)) / 2;
2299 recover
= cycle
- active
;
2302 // Newer chips dislike this:
2303 if(/*!(deviceExtension->HwFlags & VIAAST)*/
2304 deviceExtension
->MaxTransferMode
< ATA_UDMA6
) {
2305 /* PIO address setup */
2306 GetPciConfig1(0x4c, t
);
2307 t
= (t
& ~(3 << ((3 - dev
) << 1))) | (FIT(setup
- 1, 0, 3) << ((3 - dev
) << 1));
2308 SetPciConfig1(0x4c, t
);
2311 /* PIO active & recover */
2312 SetPciConfig1(0x4b-dev
, (FIT(active
- 1, 0, 0xf) << 4) | FIT(recover
- 1, 0, 0xf) );
2313 } // end via82c_timing()