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[UNIATA]
[reactos.git] / reactos / drivers / storage / ide / uniata / id_dma.cpp
1 /*++
2
3 Copyright (c) 2002-2012 Alexander A. Telyatnikov (Alter)
4
5 Module Name:
6 id_dma.cpp
7
8 Abstract:
9 This is the miniport driver for ATAPI IDE controllers
10 With Busmaster DMA support
11
12 Author:
13 Alexander A. Telyatnikov (Alter)
14
15 Environment:
16 kernel mode only
17
18 Notes:
19
20 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30
31 Revision History:
32
33 This module is a port from FreeBSD 4.3-6.1 ATA driver (ata-dma.c, ata-chipset.c) by
34 Søren Schmidt, Copyright (c) 1998-2008
35
36 Changed defaulting-to-generic-PIO/DMA policy
37 Added PIO settings for VIA
38 Optimized VIA/AMD/nVidia init part
39 Optimized Promise TX2 init part
40 Optimized Intel init part
41 by Alex A. Telyatnikov (Alter) (c) 2002-2007
42
43
44 --*/
45
46 #include "stdafx.h"
47
48 static const ULONG valid_udma[7] = {0,0,2,0,4,5,6};
49
50 static const CHAR retry_Wdma[MAX_RETRIES+1] = {2, 2, 2,-1,-1,-1};
51 static const CHAR retry_Udma[MAX_RETRIES+1] = {6, 2,-1,-1,-1,-1};
52
53 PHYSICAL_ADDRESS ph4gb = {{0xFFFFFFFF, 0}};
54
55 VOID
56 NTAPI
57 cyrix_timing (
58 IN PHW_DEVICE_EXTENSION deviceExtension,
59 IN ULONG dev, // physical device number (0-3)
60 IN CHAR mode
61 );
62
63 VOID
64 NTAPI
65 promise_timing (
66 IN PHW_DEVICE_EXTENSION deviceExtension,
67 IN ULONG dev, // physical device number (0-3)
68 IN CHAR mode
69 );
70
71 VOID
72 NTAPI
73 hpt_timing (
74 IN PHW_DEVICE_EXTENSION deviceExtension,
75 IN ULONG dev, // physical device number (0-3)
76 IN CHAR mode
77 );
78
79 VOID
80 NTAPI
81 via82c_timing (
82 IN PHW_DEVICE_EXTENSION deviceExtension,
83 IN ULONG dev, // physical device number (0-3)
84 IN CHAR mode
85 );
86
87 ULONG
88 NTAPI
89 hpt_cable80(
90 IN PHW_DEVICE_EXTENSION deviceExtension,
91 IN ULONG channel // physical channel number (0-1)
92 );
93
94 ULONG
95 NTAPI
96 AtapiVirtToPhysAddr_(
97 IN PVOID HwDeviceExtension,
98 IN PSCSI_REQUEST_BLOCK Srb,
99 IN PUCHAR data,
100 OUT PULONG count, /* bytes */
101 OUT PULONG ph_addru
102 )
103 {
104 PHYSICAL_ADDRESS ph_addr;
105 ULONG addr;
106
107 ph_addr = MmGetPhysicalAddress(data);
108 if(!ph_addru && ph_addr.HighPart) {
109 // do so until we add 64bit address support
110 // or some workaround
111 *count = 0;
112 return -1;
113 }
114
115 (*ph_addru) = ph_addr.HighPart;
116 //addr = ScsiPortConvertPhysicalAddressToUlong(ph_addr);
117 addr = ph_addr.LowPart;
118 if(!addr && !ph_addr.HighPart) {
119 *count = 0;
120 return 0;
121 }
122 if(!Srb) {
123 *count = sizeof(BM_DMA_ENTRY)*ATA_DMA_ENTRIES;
124 } else {
125 *count = PAGE_SIZE - (addr & (PAGE_SIZE-1));
126 }
127 return addr;
128 } // end AtapiVirtToPhysAddr_()
129
130 VOID
131 NTAPI
132 AtapiDmaAlloc(
133 IN PVOID HwDeviceExtension,
134 IN PPORT_CONFIGURATION_INFORMATION ConfigInfo,
135 IN ULONG lChannel // logical channel,
136 )
137 {
138 #ifdef USE_OWN_DMA
139 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
140 PHW_CHANNEL chan = &(deviceExtension->chan[lChannel]);
141 ULONG c = lChannel;
142 ULONG i;
143 ULONG ph_addru;
144
145 deviceExtension->chan[c].CopyDmaBuffer = FALSE;
146
147 if(!deviceExtension->Host64 && (WinVer_Id() > WinVer_NT)) {
148 KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: allocate tmp buffers below 4Gb\n"));
149 chan->DB_PRD = MmAllocateContiguousMemory(sizeof(((PATA_REQ)NULL)->dma_tab), ph4gb);
150 if(chan->DB_PRD) {
151 chan->DB_PRD_PhAddr = AtapiVirtToPhysAddr(HwDeviceExtension, NULL, (PUCHAR)(chan->DB_PRD), &i, &ph_addru);
152 if(!chan->DB_PRD_PhAddr || !i || ((LONG)(chan->DB_PRD_PhAddr) == -1)) {
153 KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: No DB PRD BASE\n" ));
154 chan->DB_PRD = NULL;
155 chan->DB_PRD_PhAddr = 0;
156 return;
157 }
158 if(ph_addru) {
159 KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: No DB PRD below 4Gb\n" ));
160 goto err_1;
161 }
162 }
163 chan->DB_IO = MmAllocateContiguousMemory(deviceExtension->MaximumDmaTransferLength, ph4gb);
164 if(chan->DB_IO) {
165 chan->DB_IO_PhAddr = AtapiVirtToPhysAddr(HwDeviceExtension, NULL, (PUCHAR)(chan->DB_IO), &i, &ph_addru);
166 if(!chan->DB_IO_PhAddr || !i || ((LONG)(chan->DB_IO_PhAddr) == -1)) {
167 KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: No DB IO BASE\n" ));
168 err_1:
169 MmFreeContiguousMemory(chan->DB_PRD);
170 chan->DB_PRD = NULL;
171 chan->DB_PRD_PhAddr = 0;
172 chan->DB_IO = NULL;
173 chan->DB_IO_PhAddr = 0;
174 return;
175 }
176 if(ph_addru) {
177 KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: No DB IO below 4Gb\n" ));
178 MmFreeContiguousMemory(chan->DB_IO);
179 goto err_1;
180 }
181 }
182 }
183
184
185 if(deviceExtension->HwFlags & UNIATA_AHCI) {
186 KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: AHCI\n" ));
187 if(chan->AhciCtlBlock) {
188 KdPrint2((PRINT_PREFIX " already initialized %x\n", chan->AhciCtlBlock));
189 return;
190 }
191 // Need 1K-byte alignment
192 chan->AhciCtlBlock0 = (PIDE_AHCI_CHANNEL_CTL_BLOCK)MmAllocateContiguousMemory(
193 sizeof(IDE_AHCI_CHANNEL_CTL_BLOCK)+AHCI_CLB_ALIGNEMENT_MASK,
194 ph4gb);
195 if(chan->AhciCtlBlock0) {
196 union {
197 PUCHAR AhciCtlBlock;
198 ULONGLONG AhciCtlBlock64;
199 };
200 AhciCtlBlock64 = 0;
201 AhciCtlBlock = (PUCHAR)chan->AhciCtlBlock0;
202
203 KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: CLP BASE %I64x\n", AhciCtlBlock64));
204
205 AhciCtlBlock64 += AHCI_CLB_ALIGNEMENT_MASK;
206 AhciCtlBlock64 &= ~AHCI_CLB_ALIGNEMENT_MASK;
207
208 KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: CLP BASE 1k-aligned %I64x\n", AhciCtlBlock64));
209
210 chan->AhciCtlBlock = (PIDE_AHCI_CHANNEL_CTL_BLOCK)AhciCtlBlock;
211
212 chan->AHCI_CTL_PhAddr = AtapiVirtToPhysAddr(HwDeviceExtension, NULL, (PUCHAR)(chan->AhciCtlBlock), &i, &ph_addru);
213 KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: CLP Phys BASE %I64x\n", chan->AHCI_CTL_PhAddr));
214 if(!chan->AHCI_CTL_PhAddr || !i || ((LONG)(chan->AHCI_CTL_PhAddr) == -1)) {
215 KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: No AHCI CLP BASE\n" ));
216 chan->AhciCtlBlock = NULL;
217 chan->AHCI_CTL_PhAddr = 0;
218 return;
219 }
220 if(ph_addru) {
221 KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: No AHCI CLP below 4Gb\n" ));
222 MmFreeContiguousMemory(chan->AhciCtlBlock0);
223 chan->AhciCtlBlock = NULL;
224 chan->AHCI_CTL_PhAddr = 0;
225 return;
226 }
227 } else {
228 KdPrint2((PRINT_PREFIX "AtapiDmaAlloc: Can't alloc AHCI CLP\n"));
229 }
230 }
231 #endif //USE_OWN_DMA
232 return;
233 } // end AtapiDmaAlloc()
234
235 BOOLEAN
236 NTAPI
237 AtapiDmaSetup(
238 IN PVOID HwDeviceExtension,
239 IN ULONG DeviceNumber,
240 IN ULONG lChannel, // logical channel,
241 IN PSCSI_REQUEST_BLOCK Srb,
242 IN PUCHAR data,
243 IN ULONG count /* bytes */
244 )
245 {
246 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
247 ULONG dma_count, dma_base, dma_baseu;
248 ULONG dma_count0, dma_base0;
249 ULONG i;
250 PHW_CHANNEL chan = &(deviceExtension->chan[lChannel]);
251 PATA_REQ AtaReq = (PATA_REQ)(Srb->SrbExtension);
252 BOOLEAN use_DB_IO = FALSE;
253 BOOLEAN use_AHCI = (deviceExtension->HwFlags & UNIATA_AHCI) ? TRUE : FALSE;
254 ULONG orig_count = count;
255 ULONG max_entries = use_AHCI ? ATA_AHCI_DMA_ENTRIES : ATA_DMA_ENTRIES;
256 //ULONG max_frag = use_AHCI ? (0x3fffff+1) : (4096); // DEBUG, replace 4096 for procer chipset-specific value
257 ULONG max_frag = deviceExtension->DmaSegmentLength;
258 ULONG seg_align = deviceExtension->DmaSegmentAlignmentMask;
259
260 if(AtaReq->dma_entries) {
261 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: already setup, %d entries\n", AtaReq->dma_entries));
262 return TRUE;
263 }
264 AtaReq->ata.dma_base = 0;
265 AtaReq->Flags &= ~REQ_FLAG_DMA_OPERATION;
266
267 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: mode %#x, data %x, count %x, lCh %x, dev %x\n",
268 chan->lun[DeviceNumber]->TransferMode,
269 data, count, lChannel, DeviceNumber ));
270 if(chan->lun[DeviceNumber]->TransferMode < ATA_DMA) {
271 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: Not DMA mode, assume this is just preparation\n" ));
272 //return FALSE;
273 }
274 //KdPrint2((PRINT_PREFIX " checkpoint 1\n" ));
275 if(!count) {
276 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: count=0\n" ));
277 return FALSE;
278 }
279 //KdPrint2((PRINT_PREFIX " checkpoint 2\n" ));
280 if(count > deviceExtension->MaximumDmaTransferLength) {
281 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: deviceExtension->MaximumDmaTransferLength > count\n" ));
282 return FALSE;
283 }
284 //KdPrint2((PRINT_PREFIX " checkpoint 3\n" ));
285 if((ULONG)data & deviceExtension->AlignmentMask) {
286 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: unaligned data: %#x (%#x)\n", data, deviceExtension->AlignmentMask));
287 return FALSE;
288 }
289
290 //KdPrint2((PRINT_PREFIX " checkpoint 4\n" ));
291 if(use_AHCI) {
292 KdPrint2((PRINT_PREFIX " get Phys(AHCI_CMD=%x)\n", AtaReq->ahci.ahci_cmd_ptr ));
293 dma_base = AtapiVirtToPhysAddr(HwDeviceExtension, NULL, (PUCHAR)(AtaReq->ahci.ahci_cmd_ptr), &i, &dma_baseu);
294 AtaReq->ahci.ahci_base64 = 0; // clear before setup
295 } else {
296 KdPrint2((PRINT_PREFIX " get Phys(PRD=%x)\n", &(AtaReq->dma_tab) ));
297 dma_base = AtapiVirtToPhysAddr(HwDeviceExtension, NULL, (PUCHAR)&(AtaReq->dma_tab) /*chan->dma_tab*/, &i, &dma_baseu);
298 }
299 if(dma_baseu) {
300 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: SRB built-in PRD above 4Gb: %8.8x%8.8x\n", dma_baseu, dma_base));
301 if(!deviceExtension->Host64) {
302 dma_base = chan->DB_PRD_PhAddr;
303 AtaReq->Flags |= REQ_FLAG_DMA_DBUF_PRD;
304 i = 1;
305 }
306 } else
307 if(!dma_base || !i || ((LONG)(dma_base) == -1)) {
308 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: No BASE\n" ));
309 return FALSE;
310 }
311 AtaReq->ata.dma_base = dma_base; // aliased to AtaReq->ahci.ahci_base64
312
313 KdPrint2((PRINT_PREFIX " get Phys(data[0]=%x)\n", data ));
314 dma_base = AtapiVirtToPhysAddr(HwDeviceExtension, Srb, data, &dma_count, &dma_baseu);
315 if(dma_baseu) {
316 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: 1st block of buffer above 4Gb: %8.8x%8.8x\n", dma_baseu, dma_base));
317 if(!deviceExtension->Host64) {
318 retry_DB_IO:
319 use_DB_IO = TRUE;
320 dma_base = chan->DB_IO_PhAddr;
321 data = (PUCHAR)(chan->DB_IO);
322 } else {
323 AtaReq->ahci.ahci_base64 = (ULONGLONG)dma_base | ((ULONGLONG)dma_baseu << 32);
324 }
325 } else
326 if(!dma_count || ((LONG)(dma_base) == -1)) {
327 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: No 1st block\n" ));
328 //AtaReq->dma_base = NULL;
329 AtaReq->ahci.ahci_base64 = NULL;
330 return FALSE;
331 }
332
333 dma_count = min(count, (PAGE_SIZE - ((ULONG)data & PAGE_MASK)));
334 data += dma_count;
335 count -= dma_count;
336 i = 0;
337
338 dma_count0 = dma_count;
339 dma_base0 = dma_base;
340
341 while (count) {
342 /* KdPrint2((PRINT_PREFIX " segments %#x+%#x == %#x && %#x+%#x <= %#x\n",
343 dma_base0, dma_count0, dma_base,
344 dma_count0, dma_count, max_frag));*/
345 if(dma_base0+dma_count0 == dma_base &&
346 dma_count0+dma_count <= max_frag) {
347 // 'i' should be always > 0 here
348 // for BM we cannot cross 64k boundary
349 if(dma_base & seg_align) {
350 //KdPrint2((PRINT_PREFIX " merge segments\n" ));
351 ASSERT(i);
352 //BrutePoint();
353 i--;
354 dma_base = dma_base0;
355 dma_count += dma_count0;
356 }
357 }
358 if(use_AHCI) {
359 AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].base = dma_base;
360 AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].baseu = dma_baseu;
361 AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].Reserved1 = 0;
362 *((PULONG)&(AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].DBC_ULONG)) = ((dma_count-1) & 0x3fffff);
363 /* AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].Reserved2 = 0;
364 AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].I = 0;*/
365 KdPrint2((PRINT_PREFIX " ph data[%d]=%x:%x (%x)\n", i, dma_baseu, dma_base, AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].DBC));
366 } else {
367 AtaReq->dma_tab[i].base = dma_base;
368 AtaReq->dma_tab[i].count = (dma_count & 0xffff);
369 }
370 dma_count0 = dma_count;
371 dma_base0 = dma_base;
372 i++;
373 if (i >= max_entries) {
374 KdPrint2((PRINT_PREFIX "too many segments in DMA table\n" ));
375 //AtaReq->dma_base = NULL;
376 AtaReq->ahci.ahci_base64 = NULL;
377 return FALSE;
378 }
379 KdPrint2((PRINT_PREFIX " get Phys(data[n=%d]=%x)\n", i, data ));
380 dma_base = AtapiVirtToPhysAddr(HwDeviceExtension, Srb, data, &dma_count, &dma_baseu);
381 if(dma_baseu) {
382 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: block of buffer above 4Gb: %8.8x%8.8x\n", dma_baseu, dma_base));
383 if(!deviceExtension->Host64) {
384 if(use_DB_IO) {
385 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: *ERROR* special buffer above 4Gb: %8.8x%8.8x\n", dma_baseu, dma_base));
386 return FALSE;
387 }
388 count = orig_count;
389 goto retry_DB_IO;
390 }
391 } else
392 if(!dma_count || !dma_base || ((LONG)(dma_base) == -1)) {
393 //AtaReq->dma_base = NULL;
394 AtaReq->ahci.ahci_base64 = 0;
395 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: No NEXT block\n" ));
396 return FALSE;
397 }
398
399 dma_count = min(count, PAGE_SIZE);
400 data += min(count, PAGE_SIZE);
401 count -= min(count, PAGE_SIZE);
402 }
403 KdPrint2((PRINT_PREFIX " set TERM\n" ));
404 /* KdPrint2((PRINT_PREFIX " segments %#x+%#x == %#x && #x+%#x <= %#x\n",
405 dma_base0, dma_count0, dma_base,
406 dma_count0, dma_count, max_frag));*/
407 if(dma_base0+dma_count0 == dma_base &&
408 dma_count0+dma_count <= max_frag) {
409 // 'i' should be always > 0 here
410 if(dma_base & seg_align) {
411 //KdPrint2((PRINT_PREFIX " merge segments\n" ));
412 //BrutePoint();
413 ASSERT(i);
414 i--;
415 dma_base = dma_base0;
416 dma_count += dma_count0;
417 }
418 }
419 if(use_AHCI) {
420 AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].base = dma_base;
421 AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].baseu = dma_baseu;
422 AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].Reserved1 = 0;
423 //AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].DBC = ((dma_count-1) & 0x3fffff);
424 //AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].Reserved2 = 0;
425 *((PULONG)&(AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].DBC_ULONG)) = ((dma_count-1) & 0x3fffff);
426 //AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].I = 1; // interrupt when ready
427 KdPrint2((PRINT_PREFIX " ph data[%d]=%x:%x (%x)\n", i, dma_baseu, dma_base, AtaReq->ahci.ahci_cmd_ptr->prd_tab[i].DBC));
428 if(((ULONG)&(AtaReq->ahci.ahci_cmd_ptr->prd_tab) & ~PAGE_MASK) != ((ULONG)&(AtaReq->ahci.ahci_cmd_ptr->prd_tab[i]) & ~PAGE_MASK)) {
429 KdPrint2((PRINT_PREFIX "PRD table crosses page boundary! %x vs %x\n",
430 &AtaReq->ahci.ahci_cmd_ptr->prd_tab, &(AtaReq->ahci.ahci_cmd_ptr->prd_tab[i]) ));
431 //AtaReq->Flags |= REQ_FLAG_DMA_DBUF_PRD;
432 }
433 } else {
434 AtaReq->dma_tab[i].base = dma_base;
435 AtaReq->dma_tab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
436 if(((ULONG)&(AtaReq->dma_tab) & ~PAGE_MASK) != ((ULONG)&(AtaReq->dma_tab[i]) & ~PAGE_MASK)) {
437 KdPrint2((PRINT_PREFIX "DMA table crosses page boundary! %x vs %x\n",
438 &AtaReq->dma_tab, &(AtaReq->dma_tab[i]) ));
439 //AtaReq->Flags |= REQ_FLAG_DMA_DBUF_PRD;
440 }
441 }
442 AtaReq->dma_entries = i+1;
443
444 if(use_DB_IO) {
445 AtaReq->Flags |= REQ_FLAG_DMA_DBUF;
446 }
447 AtaReq->Flags |= REQ_FLAG_DMA_OPERATION;
448
449 KdPrint2((PRINT_PREFIX "AtapiDmaSetup: OK\n" ));
450 return TRUE;
451
452 } // end AtapiDmaSetup()
453
454 BOOLEAN
455 NTAPI
456 AtapiDmaPioSync(
457 PVOID HwDeviceExtension,
458 PSCSI_REQUEST_BLOCK Srb,
459 PUCHAR data,
460 ULONG count
461 )
462 {
463 #ifndef USE_OWN_DMA
464 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
465 ULONG dma_base;
466 PUCHAR DmaBuffer;
467 ULONG dma_count;
468 ULONG len;
469 PATA_REQ AtaReq;
470
471 // This must never be called after DMA operation !!!
472 KdPrint2((PRINT_PREFIX "AtapiDmaPioSync: data %#x, len %#x\n", data, count));
473
474 if(!Srb) {
475 KdPrint2((PRINT_PREFIX "AtapiDmaPioSync: !Srb\n" ));
476 return FALSE;
477 }
478
479 AtaReq = (PATA_REQ)(Srb->SrbExtension);
480
481 // do nothing on PCI (This can be changed. We cannot guarantee,
482 // that CommonBuffer will always point to User's buffer,
483 // however, this usually happens on PCI-32)
484 if(deviceExtension->OrigAdapterInterfaceType == PCIBus) {
485 return TRUE;
486 }
487 // do nothing for DMA
488 if(AtaReq->Flags & REQ_FLAG_DMA_OPERATION) {
489 return TRUE;
490 }
491
492 if(!data) {
493 KdPrint2((PRINT_PREFIX "AtapiDmaPioSync: !data\n" ));
494 return FALSE;
495 }
496
497 while(count) {
498 dma_base = AtapiVirtToPhysAddr(HwDeviceExtension, Srb, data, &dma_count);
499 if(!dma_base) {
500 KdPrint2((PRINT_PREFIX "AtapiDmaPioSync: !dma_base for data %#x\n", data));
501 return FALSE;
502 }
503 DmaBuffer = (PUCHAR)ScsiPortGetVirtualAddress(HwDeviceExtension,
504 ScsiPortConvertUlongToPhysicalAddress(dma_base));
505 if(!DmaBuffer) {
506 KdPrint2((PRINT_PREFIX "AtapiDmaPioSync: !DmaBuffer for dma_base %#x\n", dma_base));
507 return FALSE;
508 }
509 len = min(dma_count, count);
510 memcpy(DmaBuffer, data, len);
511 count -= len;
512 data += len;
513 }
514 #endif //USE_OWN_DMA
515
516 return TRUE;
517 } // end AtapiDmaPioSync()
518
519 BOOLEAN
520 NTAPI
521 AtapiDmaDBSync(
522 PHW_CHANNEL chan,
523 PSCSI_REQUEST_BLOCK Srb
524 )
525 {
526 PATA_REQ AtaReq;
527
528 AtaReq = (PATA_REQ)(Srb->SrbExtension);
529 if((Srb->SrbFlags & SRB_FLAGS_DATA_IN) &&
530 (AtaReq->Flags & REQ_FLAG_DMA_DBUF)) {
531 KdPrint2((PRINT_PREFIX " AtapiDmaDBSync is issued.\n"));
532 ASSERT(FALSE);
533 KdPrint2((PRINT_PREFIX " DBUF (Read)\n"));
534 RtlCopyMemory(AtaReq->DataBuffer, chan->DB_IO,
535 Srb->DataTransferLength);
536 }
537 return TRUE;
538 } // end AtapiDmaDBSync()
539
540 VOID
541 NTAPI
542 AtapiDmaStart(
543 IN PVOID HwDeviceExtension,
544 IN ULONG DeviceNumber,
545 IN ULONG lChannel, // logical channel,
546 IN PSCSI_REQUEST_BLOCK Srb
547 )
548 {
549 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
550 //PIDE_BUSMASTER_REGISTERS BaseIoAddressBM = deviceExtension->BaseIoAddressBM[lChannel];
551 PATA_REQ AtaReq = (PATA_REQ)(Srb->SrbExtension);
552 PHW_CHANNEL chan = &deviceExtension->chan[lChannel];
553
554 ULONG VendorID = deviceExtension->DevID & 0xffff;
555 ULONG ChipType = deviceExtension->HwFlags & CHIPTYPE_MASK;
556
557 KdPrint2((PRINT_PREFIX "AtapiDmaStart: %s on %#x:%#x\n",
558 (Srb->SrbFlags & SRB_FLAGS_DATA_IN) ? "read" : "write",
559 lChannel, DeviceNumber ));
560
561 if(!AtaReq->ata.dma_base) {
562 KdPrint2((PRINT_PREFIX "AtapiDmaStart: *** !AtaReq->ata.dma_base\n"));
563 return;
564 }
565 if(AtaReq->Flags & REQ_FLAG_DMA_DBUF_PRD) {
566 KdPrint2((PRINT_PREFIX " DBUF_PRD\n"));
567 ASSERT(FALSE);
568 if(deviceExtension->HwFlags & UNIATA_AHCI) {
569 RtlCopyMemory(chan->DB_PRD, AtaReq->ahci.ahci_cmd_ptr, sizeof(AtaReq->ahci_cmd0));
570 } else {
571 RtlCopyMemory(chan->DB_PRD, &(AtaReq->dma_tab), sizeof(AtaReq->dma_tab));
572 }
573 }
574 if(!(Srb->SrbFlags & SRB_FLAGS_DATA_IN) &&
575 (AtaReq->Flags & REQ_FLAG_DMA_DBUF)) {
576 KdPrint2((PRINT_PREFIX " DBUF (Write)\n"));
577 ASSERT(FALSE);
578 RtlCopyMemory(chan->DB_IO, AtaReq->DataBuffer,
579 Srb->DataTransferLength);
580 }
581
582 // set flag
583 chan->ChannelCtrlFlags |= CTRFLAGS_DMA_ACTIVE;
584
585 switch(VendorID) {
586 case ATA_PROMISE_ID:
587 if(ChipType == PRNEW) {
588 ULONG Channel = deviceExtension->Channel + lChannel;
589 if(chan->ChannelCtrlFlags & CTRFLAGS_LBA48) {
590 AtapiWritePortEx1(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11,
591 AtapiReadPortEx1(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11) |
592 (Channel ? 0x08 : 0x02));
593 AtapiWritePortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),(Channel ? 0x24 : 0x20),
594 ((Srb->SrbFlags & SRB_FLAGS_DATA_IN) ? 0x05000000 : 0x06000000) | (Srb->DataTransferLength >> 1)
595 );
596 }
597 /*
598 } else
599 if(deviceExtension->MemIo) {
600 // begin transaction
601 AtapiWritePort4(chan,
602 IDX_BM_Command,
603 (AtapiReadPort4(chan,
604 IDX_BM_Command) & ~0x000000c0) |
605 ((Srb->SrbFlags & SRB_FLAGS_DATA_IN) ? 0x00000080 : 0x000000c0) );
606 return;
607 */
608 }
609 break;
610 }
611
612 // set pointer to Pointer Table
613 AtapiWritePort4(chan, IDX_BM_PRD_Table,
614 AtaReq->ata.dma_base
615 );
616 // set transfer direction
617 AtapiWritePort1(chan, IDX_BM_Command,
618 (Srb->SrbFlags & SRB_FLAGS_DATA_IN) ? BM_COMMAND_READ : BM_COMMAND_WRITE);
619 // clear Error & Intr bits (writeing 1 clears bits)
620 // set DMA capability bit
621 AtapiWritePort1(chan, IDX_BM_Status,
622 AtapiReadPort1(chan, IDX_BM_Status) |
623 (BM_STATUS_INTR | BM_STATUS_ERR) /*|
624 (DeviceNumber ? BM_STATUS_DRIVE_1_DMA : BM_STATUS_DRIVE_0_DMA)*/);
625 // begin transaction
626 AtapiWritePort1(chan, IDX_BM_Command,
627 AtapiReadPort1(chan, IDX_BM_Command) |
628 BM_COMMAND_START_STOP);
629 return;
630
631 } // end AtapiDmaStart()
632
633 UCHAR
634 NTAPI
635 AtapiDmaDone(
636 IN PVOID HwDeviceExtension,
637 IN ULONG DeviceNumber,
638 IN ULONG lChannel, // logical channel,
639 IN PSCSI_REQUEST_BLOCK Srb
640 )
641 {
642 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
643 //PIDE_BUSMASTER_REGISTERS BaseIoAddressBM = deviceExtension->BaseIoAddressBM[lChannel];
644 PHW_CHANNEL chan = &deviceExtension->chan[lChannel];
645 UCHAR dma_status;
646
647 ULONG VendorID = deviceExtension->DevID & 0xffff;
648 ULONG ChipType = deviceExtension->HwFlags & CHIPTYPE_MASK;
649
650 KdPrint2((PRINT_PREFIX "AtapiDmaDone: dev %d\n", DeviceNumber));
651
652 if(deviceExtension->HwFlags & UNIATA_AHCI) {
653 KdPrint2((PRINT_PREFIX " ACHTUNG! should not be called for AHCI!\n"));
654 return IDE_STATUS_WRONG;
655 }
656
657 switch(VendorID) {
658 case ATA_PROMISE_ID:
659 if(ChipType == PRNEW) {
660 ULONG Channel = deviceExtension->Channel + lChannel;
661 if(chan->ChannelCtrlFlags & CTRFLAGS_LBA48) {
662 AtapiWritePortEx1(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11,
663 AtapiReadPortEx1(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),0x11) &
664 ~(Channel ? 0x08 : 0x02));
665 AtapiWritePortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),(Channel ? 0x24 : 0x20),
666 0
667 );
668 }
669 /*
670 } else
671 if(deviceExtension->MemIo) {
672 // end transaction
673 AtapiWritePort4(chan,
674 IDX_BM_Command,
675 (AtapiReadPort4(chan,
676 IDX_BM_Command) & ~0x00000080) );
677 // clear flag
678 chan->ChannelCtrlFlags &= ~CTRFLAGS_DMA_ACTIVE;
679 return 0;
680 */
681 }
682 break;
683 }
684
685 // get status
686 dma_status = AtapiReadPort1(chan, IDX_BM_Status) & BM_STATUS_MASK;
687 // end transaction
688 AtapiWritePort1(chan, IDX_BM_Command,
689 AtapiReadPort1(chan, IDX_BM_Command) &
690 ~BM_COMMAND_START_STOP);
691 // clear interrupt and error status
692 AtapiWritePort1(chan, IDX_BM_Status, BM_STATUS_ERR | BM_STATUS_INTR);
693 // clear flag
694 chan->ChannelCtrlFlags &= ~CTRFLAGS_DMA_ACTIVE;
695
696 return dma_status;
697
698 } // end AtapiDmaDone()
699
700 VOID
701 NTAPI
702 AtapiDmaReinit(
703 IN PHW_DEVICE_EXTENSION deviceExtension,
704 IN PHW_LU_EXTENSION LunExt,
705 IN PATA_REQ AtaReq
706 )
707 {
708 SCHAR apiomode;
709
710 if((deviceExtension->HwFlags & UNIATA_AHCI) &&
711 !(LunExt->DeviceFlags & DFLAGS_ATAPI_DEVICE)) {
712 // skip unnecessary checks
713 KdPrint2((PRINT_PREFIX "AtapiDmaReinit: ahci, nothing to do for HDD\n"));
714 return;
715 }
716
717 apiomode = (CHAR)AtaPioMode(&(LunExt->IdentifyData));
718
719 if(!(AtaReq->Flags & REQ_FLAG_DMA_OPERATION)) {
720 KdPrint2((PRINT_PREFIX
721 "AtapiDmaReinit: !(AtaReq->Flags & REQ_FLAG_DMA_OPERATION), fall to PIO on Device %d\n", LunExt->Lun));
722 goto limit_pio;
723 }
724 if(deviceExtension->HwFlags & UNIATA_AHCI) {
725 if(!AtaReq->ahci.ahci_base64) {
726 KdPrint2((PRINT_PREFIX
727 "AtapiDmaReinit: no AHCI PRD, fatal on Device %d\n", LunExt->Lun));
728 goto exit;
729 }
730 } else
731 if(!AtaReq->ata.dma_base) {
732 KdPrint2((PRINT_PREFIX
733 "AtapiDmaReinit: no PRD, fall to PIO on Device %d\n", LunExt->Lun));
734 goto limit_pio;
735 }
736
737 if((deviceExtension->HbaCtrlFlags & HBAFLAGS_DMA_DISABLED_LBA48) &&
738 (AtaReq->lba >= (LONGLONG)ATA_MAX_LBA28) &&
739 (LunExt->TransferMode > ATA_PIO5) ) {
740 KdPrint2((PRINT_PREFIX
741 "AtapiDmaReinit: FORCE_DOWNRATE on Device %d for LBA48\n", LunExt->Lun));
742 goto limit_lba48;
743 }
744
745
746 if(AtaReq->Flags & REQ_FLAG_FORCE_DOWNRATE) {
747 KdPrint2((PRINT_PREFIX
748 "AtapiDmaReinit: FORCE_DOWNRATE on Device %d\n", LunExt->Lun));
749 if(AtaReq->lba >= (LONGLONG)ATA_MAX_LBA28) {
750 limit_lba48:
751 LunExt->DeviceFlags |= REQ_FLAG_FORCE_DOWNRATE_LBA48;
752 limit_pio:
753 // do not make extra work if we already use PIO
754 if(/*LunExt->TransferMode >= ATA_DMA*/
755 (LunExt->TransferMode > ATA_PIO5) && (LunExt->TransferMode != ATA_PIO0+apiomode)
756 ) {
757 KdPrint2((PRINT_PREFIX
758 "AtapiDmaReinit: set PIO mode on Device %d (%x -> %x)\n", LunExt->Lun, LunExt->TransferMode, ATA_PIO0+apiomode));
759 AtapiDmaInit(deviceExtension, LunExt->Lun, LunExt->chan->lChannel,
760 apiomode,
761 -1,
762 -1 );
763 } else
764 if(LunExt->LimitedTransferMode < LunExt->TransferMode) {
765 KdPrint2((PRINT_PREFIX
766 "AtapiDmaReinit: set PIO mode on Device %d (%x -> %x) (2)\n", LunExt->Lun, LunExt->TransferMode, LunExt->LimitedTransferMode));
767 AtapiDmaInit(deviceExtension, LunExt->Lun, LunExt->chan->lChannel,
768 LunExt->LimitedTransferMode-ATA_PIO0,
769 -1,
770 -1 );
771 }
772
773 } else {
774 KdPrint2((PRINT_PREFIX
775 "AtapiDmaReinit: set MAX mode on Device %d\n", LunExt->Lun));
776 AtapiDmaInit(deviceExtension, LunExt->Lun, LunExt->chan->lChannel,
777 apiomode,
778 min( retry_Wdma[AtaReq->retry],
779 (CHAR)AtaWmode(&(LunExt->IdentifyData)) ),
780 min( retry_Udma[AtaReq->retry],
781 (CHAR)AtaUmode(&(LunExt->IdentifyData)) ) );
782 }
783 // LunExt->DeviceFlags &= ~DFLAGS_FORCE_DOWNRATE;
784 } else
785 if(/*!(LunExt->DeviceFlags & DFLAGS_FORCE_DOWNRATE) &&*/
786 (LunExt->LimitedTransferMode >
787 LunExt->TransferMode) ||
788 (LunExt->DeviceFlags & DFLAGS_REINIT_DMA)) {
789 // restore IO mode
790 KdPrint2((PRINT_PREFIX
791 "AtapiDmaReinit: restore IO mode on Device %d\n", LunExt->Lun));
792 AtapiDmaInit__(deviceExtension, LunExt);
793 }
794
795 exit:
796 return;
797 } // end AtapiDmaReinit()
798
799 VOID
800 NTAPI
801 AtapiDmaInit__(
802 IN PHW_DEVICE_EXTENSION deviceExtension,
803 IN PHW_LU_EXTENSION LunExt
804 )
805 {
806 if(LunExt->IdentifyData.SupportDma ||
807 (LunExt->IdentifyData.AtapiDMA.DMASupport && (LunExt->DeviceFlags & DFLAGS_ATAPI_DEVICE))) {
808 KdPrint2((PRINT_PREFIX
809 "AtapiDmaInit__: Set (U)DMA on Device %d\n", LunExt->Lun));
810 /* for(i=AtaUmode(&(LunExt->IdentifyData)); i>=0; i--) {
811 AtapiDmaInit(deviceExtension, ldev & 1, ldev >> 1,
812 (CHAR)AtaPioMode(&(LunExt->IdentifyData)),
813 (CHAR)AtaWmode(&(LunExt->IdentifyData)),
814 UDMA_MODE0+(CHAR)i );
815 }
816 for(i=AtaWmode(&(LunExt->IdentifyData)); i>=0; i--) {
817 AtapiDmaInit(deviceExtension, ldev & 1, ldev >> 1,
818 (CHAR)AtaPioMode(&(LunExt->IdentifyData)),
819 (CHAR)AtaWmode(&(LunExt->IdentifyData)),
820 UDMA_MODE0+(CHAR)i );
821 }*/
822 AtapiDmaInit(deviceExtension, LunExt->Lun, LunExt->chan->lChannel,
823 (CHAR)AtaPioMode(&(LunExt->IdentifyData)),
824 (CHAR)AtaWmode(&(LunExt->IdentifyData)),
825 (CHAR)AtaUmode(&(LunExt->IdentifyData)) );
826 } else {
827 KdPrint2((PRINT_PREFIX
828 "AtapiDmaInit__: Set PIO on Device %d\n", LunExt->Lun));
829 AtapiDmaInit(deviceExtension, LunExt->Lun, LunExt->chan->lChannel,
830 (CHAR)AtaPioMode(&(LunExt->IdentifyData)), -1, -1);
831 }
832 } // end AtapiDmaInit__()
833
834 BOOLEAN
835 NTAPI
836 AtaSetTransferMode(
837 IN PHW_DEVICE_EXTENSION deviceExtension,
838 IN ULONG DeviceNumber,
839 IN ULONG lChannel, // logical channel,
840 IN PHW_LU_EXTENSION LunExt,
841 IN ULONG mode
842 )
843 {
844 KdPrint3((PRINT_PREFIX
845 "AtaSetTransferMode: Set %#x on Device %d/%d\n", mode, lChannel, DeviceNumber));
846 LONG statusByte = 0;
847 CHAR apiomode;
848
849 if(LunExt->DeviceFlags & DFLAGS_MANUAL_CHS) {
850 statusByte = mode <= ATA_PIO2 ? IDE_STATUS_IDLE : IDE_STATUS_ERROR;
851 } else {
852 if(deviceExtension->HwFlags & UNIATA_AHCI) {
853 AtapiDisableInterrupts(deviceExtension, lChannel);
854 }
855 statusByte = AtaCommand(deviceExtension, DeviceNumber, lChannel,
856 IDE_COMMAND_SET_FEATURES, 0, 0, 0,
857 (UCHAR)((mode > ATA_UDMA6) ? ATA_UDMA6 : mode), ATA_C_F_SETXFER, ATA_WAIT_BASE_READY);
858 if(deviceExtension->HwFlags & UNIATA_AHCI) {
859 AtapiEnableInterrupts(deviceExtension, lChannel);
860 }
861 }
862 if(statusByte & IDE_STATUS_ERROR) {
863 KdPrint3((PRINT_PREFIX " wait ready after error\n"));
864 if(LunExt->DeviceFlags & DFLAGS_ATAPI_DEVICE) {
865 AtapiStallExecution(10);
866 } else {
867 AtapiStallExecution(100);
868 }
869 apiomode = (CHAR)AtaPioMode(&(LunExt->IdentifyData));
870 if( (apiomode > 0) &&
871 ((CHAR)AtaWmode(&(LunExt->IdentifyData)) > 0) &&
872 ((CHAR)AtaUmode(&(LunExt->IdentifyData)) > 0)
873 ) {
874 return FALSE;
875 }
876 if(mode > ATA_PIO2) {
877 return FALSE;
878 }
879 KdPrint3((PRINT_PREFIX " assume that drive doesn't support mode swithing using PIO%d\n", apiomode));
880 mode = ATA_PIO0 + apiomode;
881 }
882 //if(mode <= ATA_UDMA6) {
883 LunExt->TransferMode = (UCHAR)mode;
884 //}
885 return TRUE;
886 } // end AtaSetTransferMode()
887
888 VOID
889 NTAPI
890 AtapiDmaInit(
891 IN PVOID HwDeviceExtension,
892 IN ULONG DeviceNumber,
893 IN ULONG lChannel, // logical channel,
894 // is always 0 except simplex-only controllers
895 IN SCHAR apiomode,
896 IN SCHAR wdmamode,
897 IN SCHAR udmamode
898 )
899 {
900 PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
901 ULONG Channel = deviceExtension->Channel + lChannel;
902 PHW_CHANNEL chan = &deviceExtension->chan[lChannel];
903 //LONG statusByte = 0;
904 ULONG dev = Channel*2 + DeviceNumber; // for non-SATA/AHCI only!
905 //ULONG ldev = lChannel*2 + DeviceNumber; // for non-SATA/AHCI only!
906 BOOLEAN isAtapi = ATAPI_DEVICE(chan, DeviceNumber);
907 ULONG slotNumber = deviceExtension->slotNumber;
908 ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
909 LONG i;
910 PHW_LU_EXTENSION LunExt = chan->lun[DeviceNumber];
911 UCHAR ModeByte;
912
913 ULONG VendorID = deviceExtension->DevID & 0xffff;
914 //ULONG DeviceID = (deviceExtension->DevID >> 16) & 0xffff;
915 //ULONG RevID = deviceExtension->RevID;
916 ULONG ChipType = deviceExtension->HwFlags & CHIPTYPE_MASK;
917 ULONG ChipFlags = deviceExtension->HwFlags & CHIPFLAG_MASK;
918
919 LONG statusByte = 0;
920
921 //UCHAR *reg_val = NULL;
922
923 LunExt->DeviceFlags &= ~DFLAGS_REINIT_DMA;
924 /* set our most pessimistic default mode */
925 LunExt->TransferMode = ATA_PIO;
926 // if(!deviceExtension->BaseIoAddressBM[lChannel]) {
927 if(!deviceExtension->BusMaster) {
928 KdPrint2((PRINT_PREFIX " !deviceExtension->BusMaster: NO DMA\n"));
929 wdmamode = udmamode = -1;
930 }
931
932 // Limit transfer mode (controller limitation)
933 if((LONG)deviceExtension->MaxTransferMode >= ATA_UDMA) {
934 KdPrint2((PRINT_PREFIX "AtapiDmaInit: deviceExtension->MaxTransferMode >= ATA_UDMA\n"));
935 udmamode = min( udmamode, (CHAR)(deviceExtension->MaxTransferMode - ATA_UDMA));
936 } else
937 if((LONG)deviceExtension->MaxTransferMode >= ATA_WDMA) {
938 KdPrint2((PRINT_PREFIX "AtapiDmaInit: deviceExtension->MaxTransferMode >= ATA_WDMA\n"));
939 udmamode = -1;
940 wdmamode = min( wdmamode, (CHAR)(deviceExtension->MaxTransferMode - ATA_WDMA));
941 } else
942 if((LONG)deviceExtension->MaxTransferMode >= ATA_PIO0) {
943 KdPrint2((PRINT_PREFIX "AtapiDmaInit: NO DMA\n"));
944 wdmamode = udmamode = -1;
945 apiomode = min( apiomode, (CHAR)(deviceExtension->MaxTransferMode - ATA_PIO0));
946 } else {
947 KdPrint2((PRINT_PREFIX "AtapiDmaInit: PIO0\n"));
948 wdmamode = udmamode = -1;
949 apiomode = 0;
950 }
951 // Limit transfer mode (device limitation)
952 KdPrint2((PRINT_PREFIX "AtapiDmaInit: LunExt->LimitedTransferMode %#x\n", LunExt->LimitedTransferMode));
953 if((LONG)LunExt->LimitedTransferMode >= ATA_UDMA) {
954 KdPrint2((PRINT_PREFIX "AtapiDmaInit: LunExt->MaxTransferMode >= ATA_UDMA => %#x\n",
955 min( udmamode, (CHAR)(LunExt->LimitedTransferMode - ATA_UDMA))
956 ));
957 udmamode = min( udmamode, (CHAR)(LunExt->LimitedTransferMode - ATA_UDMA));
958 } else
959 if((LONG)LunExt->LimitedTransferMode >= ATA_WDMA) {
960 KdPrint2((PRINT_PREFIX "AtapiDmaInit: LunExt->MaxTransferMode >= ATA_WDMA => %#x\n",
961 min( wdmamode, (CHAR)(LunExt->LimitedTransferMode - ATA_WDMA))
962 ));
963 udmamode = -1;
964 wdmamode = min( wdmamode, (CHAR)(LunExt->LimitedTransferMode - ATA_WDMA));
965 } else
966 if((LONG)LunExt->LimitedTransferMode >= ATA_PIO0) {
967 KdPrint2((PRINT_PREFIX "AtapiDmaInit: lun NO DMA\n"));
968 wdmamode = udmamode = -1;
969 apiomode = min( apiomode, (CHAR)(LunExt->LimitedTransferMode - ATA_PIO0));
970 } else {
971 KdPrint2((PRINT_PREFIX "AtapiDmaInit: lun PIO0\n"));
972 wdmamode = udmamode = -1;
973 apiomode = 0;
974 }
975
976 //if(!(ChipFlags & UNIATA_AHCI)) {
977
978 // this is necessary for future PM support
979 SelectDrive(chan, DeviceNumber);
980 GetStatus(chan, statusByte);
981 // we can see here IDE_STATUS_ERROR status after previous operation
982 if(statusByte & IDE_STATUS_ERROR) {
983 KdPrint2((PRINT_PREFIX "IDE_STATUS_ERROR detected on entry, statusByte = %#x\n", statusByte));
984 //GetBaseStatus(chan, statusByte);
985 }
986 if(statusByte && UniataIsIdle(deviceExtension, statusByte & ~IDE_STATUS_ERROR) != IDE_STATUS_IDLE) {
987 KdPrint2((PRINT_PREFIX "Can't setup transfer mode: statusByte = %#x\n", statusByte));
988 return;
989 }
990 //}
991
992 if(UniataIsSATARangeAvailable(deviceExtension, lChannel)) {
993 //if(ChipFlags & (UNIATA_SATA | UNIATA_AHCI)) {
994 /****************/
995 /* SATA Generic */
996 /****************/
997
998 KdPrint2((PRINT_PREFIX "SATA Generic\n"));
999 if(udmamode > 5) {
1000 if(LunExt->IdentifyData.SataCapabilities != 0x0000 &&
1001 LunExt->IdentifyData.SataCapabilities != 0xffff) {
1002 //udmamode = min(udmamode, 6);
1003 KdPrint2((PRINT_PREFIX "LunExt->LimitedTransferMode %x, LunExt->OrigTransferMode %x\n",
1004 LunExt->LimitedTransferMode, LunExt->OrigTransferMode));
1005 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, min(LunExt->LimitedTransferMode, LunExt->OrigTransferMode))) {
1006 return;
1007 }
1008 udmamode = min(udmamode, 6);
1009
1010 } else {
1011 KdPrint2((PRINT_PREFIX "SATA -> PATA adapter ?\n"));
1012 if (udmamode > 2 && !LunExt->IdentifyData.HwResCableId) {
1013 KdPrint2((PRINT_PREFIX "AtapiDmaInit: DMA limited to UDMA33, non-ATA66 compliant cable\n"));
1014 udmamode = 2;
1015 apiomode = min( apiomode, (CHAR)(LunExt->LimitedTransferMode - ATA_PIO0));
1016 } else {
1017 udmamode = min(udmamode, 6);
1018 }
1019 }
1020 }
1021 if(udmamode >= 0) {
1022 ModeByte = ATA_UDMA0 + udmamode;
1023 } else
1024 if(wdmamode >= 0) {
1025 ModeByte = ATA_WDMA0 + wdmamode;
1026 } else
1027 if(apiomode >= 0) {
1028 ModeByte = ATA_PIO0 + apiomode;
1029 } else {
1030 ModeByte = ATA_PIO;
1031 }
1032
1033 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ModeByte);
1034 return;
1035 }
1036
1037 if(deviceExtension->UnknownDev) {
1038 KdPrint2((PRINT_PREFIX "Unknown chip, omit Vendor/Dev checks\n"));
1039 goto try_generic_dma;
1040 }
1041
1042 if(udmamode > 2 && !LunExt->IdentifyData.HwResCableId) {
1043 if(LunExt->IdentifyData.SataCapabilities != 0x0000 &&
1044 LunExt->IdentifyData.SataCapabilities != 0xffff) {
1045 KdPrint2((PRINT_PREFIX "AtapiDmaInit: SATA beyond adapter or Controller compat mode\n"));
1046 } else {
1047 KdPrint2((PRINT_PREFIX "AtapiDmaInit: DMA limited to UDMA33, non-ATA66 compliant cable\n"));
1048 udmamode = 2;
1049 apiomode = min( apiomode, (CHAR)(LunExt->LimitedTransferMode - ATA_PIO));
1050 }
1051 }
1052
1053 KdPrint2((PRINT_PREFIX "Setup chip a:w:u=%d:%d:%d\n",
1054 apiomode,
1055 wdmamode,
1056 udmamode));
1057
1058 switch(VendorID) {
1059 case ATA_ACARD_ID: {
1060 /*********/
1061 /* Acard */
1062 /*********/
1063 static const USHORT reg4a = 0xa6;
1064 UCHAR reg = 0x40 + (UCHAR)dev;
1065
1066 if(ChipType == ATPOLD) {
1067 /* Old Acard 850 */
1068 static const USHORT reg4x = 0x0301;
1069
1070 for(i=udmamode; i>=0; i--) {
1071 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA + i)) {
1072 set_old_acard:
1073 ChangePciConfig1(0x54, a | (0x01 << dev) | ((i+1) << (dev*2)));
1074 SetPciConfig1(0x4a, reg4a);
1075 SetPciConfig2(reg, reg4x);
1076 return;
1077 }
1078
1079 }
1080 if (wdmamode >= 2 && apiomode >= 4) {
1081 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA2)) {
1082 goto set_old_acard;
1083 }
1084 }
1085 } else {
1086 /* New Acard 86X */
1087 static const UCHAR reg4x = 0x31;
1088
1089 for(i=udmamode; i>=0; i--) {
1090 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA + i)) {
1091 set_new_acard:
1092 ChangePciConfig2(0x44, (a & ~(0x000f << (dev * 4))) | ((i+1) << (dev*4)));
1093 SetPciConfig1(0x4a, reg4a);
1094 SetPciConfig1(reg, reg4x);
1095 return;
1096 }
1097
1098 }
1099 if (wdmamode >= 2 && apiomode >= 4) {
1100 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA2)) {
1101 goto set_new_acard;
1102 }
1103 }
1104 }
1105 /* Use GENERIC PIO */
1106 break; }
1107 case ATA_ACER_LABS_ID: {
1108 /************************/
1109 /* Acer Labs Inc. (ALI) */
1110 /************************/
1111 static const UCHAR ali_udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f};
1112 static const ULONG ali_pio[] =
1113 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
1114 0x00310001, 0x00440001};
1115 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */
1116 if ((ChipFlags & ALIOLD) &&
1117 (udmamode >= 0 || wdmamode >= 0)) {
1118 if(ATAPI_DEVICE(chan, 0) &&
1119 ATAPI_DEVICE(chan, 1)) {
1120 // 2 devices on this channel - NO DMA
1121 chan->MaxTransferMode =
1122 min(chan->MaxTransferMode, ATA_PIO4);
1123 udmamode = wdmamode = -1;
1124 break;
1125 }
1126 }
1127 for(i=udmamode; i>=0; i--) {
1128 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1129 ULONG word54;
1130
1131 GetPciConfig4(0x54, word54);
1132 word54 &= ~(0x000f000f << (dev * 4));
1133 word54 |= (((ali_udma[i]<<16) | 5) << (dev * 4));
1134 SetPciConfig4(0x54, word54);
1135 ChangePciConfig1(0x53, a | 0x03);
1136 SetPciConfig4(0x58 + (Channel<<2), 0x00310001);
1137 return;
1138 }
1139 }
1140 /* make sure eventual UDMA mode from the BIOS is disabled */
1141 ChangePciConfig2(0x56, a & ~(0x0008 << (dev * 4)) );
1142 if (wdmamode >= 2 && apiomode >= 4) {
1143 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA2)) {
1144 ChangePciConfig1(0x53, a | 0x03);
1145 chan->ChannelCtrlFlags |= CTRFLAGS_DMA_RO;
1146 return;
1147 }
1148 }
1149 ChangePciConfig1(0x53, (a & ~0x01) | 0x02);
1150
1151 for(i=apiomode; i>=0; i--) {
1152 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + i)) {
1153 ChangePciConfig4(0x54, a & ~(0x0008000f << (dev * 4)));
1154 SetPciConfig4(0x58 + (Channel<<2), ali_pio[i]);
1155 return;
1156 }
1157 }
1158 return;
1159 break; }
1160 case ATA_AMD_ID:
1161 case ATA_NVIDIA_ID:
1162 case ATA_VIA_ID: {
1163 /********************/
1164 /* AMD, nVidia, VIA */
1165 /********************/
1166 if((VendorID == ATA_VIA_ID) &&
1167 (ChipFlags & VIASATA) &&
1168 (Channel == 0)) {
1169 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_SA150);
1170 return;
1171 }
1172
1173 static const UCHAR via_modes[5][7] = {
1174 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* ATA33 and New Chips */
1175 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* ATA66 */
1176 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* ATA100 */
1177 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
1178 { 0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6, 0xc7 }}; /* AMD/nVIDIA */
1179 static const UCHAR via_pio[] =
1180 { 0xa8, 0x65, 0x42, 0x22, 0x20, 0x42, 0x22, 0x20,
1181 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1182 const UCHAR *reg_val = NULL;
1183 UCHAR reg = 0x53-(UCHAR)dev;
1184
1185 reg_val = &via_modes[ChipType][0];
1186
1187 if(VendorID == ATA_NVIDIA_ID)
1188 reg += 0x10;
1189
1190 for(i = udmamode; i>=0; i--) {
1191 SetPciConfig1(reg-0x08, via_pio[8+i]);
1192 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1193 SetPciConfig1(reg, (UCHAR)reg_val[i]);
1194 return;
1195 }
1196 }
1197 if(!(ChipFlags & VIABAR)) {
1198 /* This chip can't do WDMA. */
1199 for(i = wdmamode; i>=0; i--) {
1200 SetPciConfig1(reg-0x08, via_pio[5+i]);
1201 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1202 SetPciConfig1(reg, 0x8b);
1203 return;
1204 }
1205 }
1206 }
1207 /* set PIO mode timings */
1208 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
1209 if((apiomode >= 0) && (ChipType != VIA133)) {
1210 SetPciConfig1(reg-0x08, via_pio[apiomode]);
1211 }
1212 via82c_timing(deviceExtension, dev, ATA_PIO0 + apiomode);
1213 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
1214 return;
1215
1216 break; }
1217 case ATA_CYRIX_ID: {
1218 /*********/
1219 /* Cyrix */
1220 /*********/
1221 ULONG cyr_piotiming[] =
1222 { 0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010 };
1223 ULONG cyr_wdmatiming[] = { 0x00077771, 0x00012121, 0x00002020 };
1224 ULONG cyr_udmatiming[] = { 0x00921250, 0x00911140, 0x00911030 };
1225 ULONG mode_reg = 0x24+(dev << 3);
1226
1227 if(apiomode >= 4)
1228 apiomode = 4;
1229 for(i=udmamode; i>=0; i--) {
1230 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1231 AtapiWritePortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0), mode_reg, cyr_udmatiming[udmamode]);
1232 return;
1233 }
1234 }
1235 for(i=wdmamode; i>=0; i--) {
1236 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1237 AtapiWritePortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0), mode_reg, cyr_wdmatiming[wdmamode]);
1238 return;
1239 }
1240 }
1241 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode)) {
1242 AtapiWritePortEx4(chan, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0), mode_reg, cyr_piotiming[apiomode]);
1243 return;
1244 }
1245 return;
1246
1247 break; }
1248 case ATA_NATIONAL_ID: {
1249 /************/
1250 /* National */
1251 /************/
1252 ULONG nat_piotiming[] =
1253 { 0x9172d132, 0x21717121, 0x00803020, 0x20102010, 0x00100010,
1254 0x00803020, 0x20102010, 0x00100010,
1255 0x00100010, 0x00100010, 0x00100010 };
1256 ULONG nat_dmatiming[] = { 0x80077771, 0x80012121, 0x80002020 };
1257 ULONG nat_udmatiming[] = { 0x80921250, 0x80911140, 0x80911030 };
1258
1259 if(apiomode >= 4)
1260 apiomode = 4;
1261 for(i=udmamode; i>=0; i--) {
1262 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1263 SetPciConfig4(0x44 + (dev * 8), nat_udmatiming[i]);
1264 SetPciConfig4(0x40 + (dev * 8), nat_piotiming[i+8]);
1265 return;
1266 }
1267 }
1268 for(i=wdmamode; i>=0; i--) {
1269 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1270 SetPciConfig4(0x44 + (dev * 8), nat_dmatiming[i]);
1271 SetPciConfig4(0x40 + (dev * 8), nat_piotiming[i+5]);
1272 return;
1273 }
1274 }
1275 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode)) {
1276 ChangePciConfig4(0x44 + (dev * 8), a | 0x80000000);
1277 SetPciConfig4(0x40 + (dev * 8), nat_piotiming[apiomode]);
1278 return;
1279 }
1280 /* Use GENERIC PIO */
1281 break; }
1282 case ATA_CYPRESS_ID:
1283 /***********/
1284 /* Cypress */
1285 /***********/
1286 if (wdmamode >= 2 && apiomode >= 4) {
1287 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA2)) {
1288 SetPciConfig2(Channel ? 0x4e:0x4c, 0x2020);
1289 return;
1290 }
1291 }
1292 /* Use GENERIC PIO */
1293 break;
1294 case ATA_MARVELL_ID:
1295 /***********/
1296 /* Marvell */
1297 /***********/
1298 for(i=udmamode; i>=0; i--) {
1299 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1300 return;
1301 }
1302 }
1303 for(i=wdmamode; i>=0; i--) {
1304 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1305 return;
1306 }
1307 }
1308 /* try generic DMA, use hpt_timing() */
1309 if (wdmamode >= 0 && apiomode >= 4) {
1310 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_DMA)) {
1311 return;
1312 }
1313 }
1314 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
1315 return;
1316 break;
1317 case ATA_NETCELL_ID:
1318 /***********/
1319 /* NetCell */
1320 /***********/
1321 if (wdmamode >= 2 && apiomode >= 4) {
1322 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA2)) {
1323 return;
1324 }
1325 }
1326 /* Use GENERIC PIO */
1327 break;
1328 case ATA_HIGHPOINT_ID: {
1329 /********************/
1330 /* High Point (HPT) */
1331 /********************/
1332 for(i=udmamode; i>=0; i--) {
1333 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1334 hpt_timing(deviceExtension, dev, (UCHAR)(ATA_UDMA + i)); // ???
1335 return;
1336 }
1337 }
1338
1339 for(i=wdmamode; i>=0; i--) {
1340 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1341 hpt_timing(deviceExtension, dev, (UCHAR)(ATA_WDMA0+i));
1342 return;
1343 }
1344 }
1345 /* try generic DMA, use hpt_timing() */
1346 if (wdmamode >= 0 && apiomode >= 4) {
1347 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_DMA)) {
1348 return;
1349 }
1350 }
1351 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
1352 hpt_timing(deviceExtension, dev, ATA_PIO0 + apiomode);
1353 return;
1354 break; }
1355 case ATA_INTEL_ID: {
1356 /*********/
1357 /* Intel */
1358 /*********/
1359
1360 BOOLEAN udma_ok = FALSE;
1361 ULONG idx = 0;
1362 ULONG reg40;
1363 UCHAR reg44;
1364 USHORT reg48;
1365 USHORT reg4a;
1366 USHORT reg54;
1367 ULONG mask40 = 0;
1368 ULONG new40 = 0;
1369 UCHAR mask44 = 0;
1370 UCHAR new44 = 0;
1371 UCHAR intel_timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
1372 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
1373
1374 if(deviceExtension->DevID == ATA_I82371FB) {
1375 if (wdmamode >= 2 && apiomode >= 4) {
1376 ULONG word40;
1377
1378 GetPciConfig4(0x40, word40);
1379 word40 >>= Channel * 16;
1380
1381 /* Check for timing config usable for DMA on controller */
1382 if (!((word40 & 0x3300) == 0x2300 &&
1383 ((word40 >> ((!(DeviceNumber & 1)) ? 0 : 4)) & 1) == 1)) {
1384 udmamode = wdmamode = -1;
1385 break;
1386 }
1387
1388 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA2)) {
1389 return;
1390 }
1391 }
1392 break;
1393 }
1394
1395 if(deviceExtension->DevID == ATA_ISCH) {
1396 ULONG tim;
1397 GetPciConfig4(0x80 + dev*4, tim);
1398
1399 for(i=udmamode; i>=0; i--) {
1400 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1401 tim |= (0x1 << 31);
1402 tim &= ~(0x7 << 16);
1403 tim |= (i << 16);
1404
1405 idx = i+8;
1406 udma_ok = TRUE;
1407 apiomode = ATA_PIO4;
1408 break;
1409 }
1410 }
1411 if(!udma_ok) {
1412 for(i=wdmamode; i>=0; i--) {
1413 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1414 tim &= ~(0x1 << 31);
1415 tim &= ~(0x3 << 8);
1416 tim |= (i << 8);
1417
1418 idx = i+5;
1419 udma_ok = TRUE;
1420 apiomode = (i == 0) ? ATA_PIO0 :
1421 (i == 1) ? ATA_PIO3 : ATA_PIO4;
1422 break;
1423 }
1424 }
1425 }
1426 if(!udma_ok) {
1427 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
1428 idx = apiomode;
1429 }
1430 tim &= ~(0x7);
1431 tim |= (apiomode & 0x7);
1432 SetPciConfig4(0x80 + dev*4, tim);
1433
1434 break;
1435 }
1436
1437 GetPciConfig2(0x48, reg48);
1438 if(!(ChipFlags & ICH4_FIX)) {
1439 GetPciConfig2(0x4a, reg4a);
1440 }
1441 GetPciConfig2(0x54, reg54);
1442 // if(udmamode >= 0) {
1443 // enable the write buffer to be used in a split (ping/pong) manner.
1444 reg54 |= 0x400;
1445 // } else {
1446 // reg54 &= ~0x400;
1447 // }
1448
1449 // reg40 &= ~0x00ff00ff;
1450 // reg40 |= 0x40774077;
1451
1452 for(i=udmamode; i>=0; i--) {
1453 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1454
1455 /* Set UDMA reference clock (33/66/133MHz). */
1456 SetPciConfig1(0x48, reg48 | (0x0001 << dev));
1457 if(!(ChipFlags & ICH4_FIX)) {
1458 SetPciConfig2(0x4a, (reg4a & ~(0x3 << (dev<<2))) |
1459 (0x01 + !(i & 0x01)) );
1460 }
1461 if(i >= 2) {
1462 reg54 |= (0x1 << dev);
1463 } else {
1464 reg54 &= ~(0x1 << dev);
1465 }
1466 if(i >= 5) {
1467 reg54 |= (0x1000 << dev);
1468 } else {
1469 reg54 &= ~(0x1000 << dev);
1470 }
1471 SetPciConfig2(0x54, reg54);
1472
1473 udma_ok = TRUE;
1474 idx = i+8;
1475 if(ChipFlags & ICH4_FIX) {
1476 return;
1477 }
1478 break;
1479 }
1480 }
1481
1482 if(!udma_ok) {
1483 SetPciConfig1(0x48, reg48 & ~(0x0001 << dev));
1484 if(!(ChipFlags & ICH4_FIX)) {
1485 SetPciConfig2(0x4a, (reg4a & ~(0x3 << (dev << 2))) );
1486 }
1487 SetPciConfig2(0x54, reg54 & ~(0x1001 << dev));
1488 for(i=wdmamode; i>=0; i--) {
1489 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1490 udma_ok = TRUE;
1491 idx = i+5;
1492 if(ChipFlags & ICH4_FIX) {
1493 return;
1494 }
1495 break;
1496 }
1497 }
1498 }
1499
1500 if(!udma_ok) {
1501 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
1502 idx = apiomode;
1503 }
1504
1505 GetPciConfig4(0x40, reg40);
1506 GetPciConfig1(0x44, reg44);
1507
1508 /* Allow PIO/WDMA timing controls. */
1509 mask40 = 0x000000ff;
1510 /* Set PIO/WDMA timings. */
1511 if(!(DeviceNumber & 1)) {
1512 mask40 |= 0x00003300;
1513 new40 = ((USHORT)(intel_timings[idx]) << 8);
1514 } else {
1515 mask44 = 0x0f;
1516 new44 = ((intel_timings[idx] & 0x30) >> 2) |
1517 (intel_timings[idx] & 0x03);
1518 }
1519 new40 |= 0x00004077;
1520
1521 if (Channel) {
1522 mask40 <<= 16;
1523 new40 <<= 16;
1524 mask44 <<= 4;
1525 new44 <<= 4;
1526 }
1527
1528 SetPciConfig4(0x40, (reg40 & ~mask40) | new40);
1529 SetPciConfig1(0x44, (reg44 & ~mask44) | new44);
1530
1531 return;
1532 break; }
1533 case ATA_PROMISE_ID:
1534 /***********/
1535 /* Promise */
1536 /***********/
1537 if(ChipType < PRTX) {
1538 if (isAtapi) {
1539 udmamode =
1540 wdmamode = -1;
1541 }
1542 }
1543 for(i=udmamode; i>=0; i--) {
1544 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1545 promise_timing(deviceExtension, dev, (UCHAR)(ATA_UDMA + i)); // ???
1546 return;
1547 }
1548 }
1549
1550 for(i=wdmamode; i>=0; i--) {
1551 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1552 promise_timing(deviceExtension, dev, (UCHAR)(ATA_WDMA0+i));
1553 return;
1554 }
1555 }
1556 /* try generic DMA, use hpt_timing() */
1557 if (wdmamode >= 0 && apiomode >= 4) {
1558 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_DMA)) {
1559 return;
1560 }
1561 }
1562 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
1563 promise_timing(deviceExtension, dev, ATA_PIO0 + apiomode);
1564 return;
1565 break;
1566 case ATA_ATI_ID:
1567
1568 KdPrint2((PRINT_PREFIX "ATI\n"));
1569 if(ChipType == SIIMIO) {
1570 goto l_ATA_SILICON_IMAGE_ID;
1571 }
1572 //goto ATA_SERVERWORKS_ID;
1573 // FALL THROUGH
1574
1575 //break; }
1576
1577 case ATA_SERVERWORKS_ID: {
1578 /***************/
1579 /* ServerWorks */
1580 /***************/
1581 // static const ULONG udma_modes[] = { 0x70, 0x21, 0x20 };
1582 static const ULONG sw_dma_modes[] = { 0x70, 0x21, 0x20 };
1583 static const ULONG sw_pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20, 0x34, 0x22, 0x20,
1584 0x20, 0x20, 0x20, 0x20, 0x20, 0x20 };
1585 USHORT reg56;
1586 ULONG reg44;
1587 ULONG reg40;
1588 ULONG offset = dev ^ 0x01;
1589 ULONG bit_offset = offset * 8;
1590
1591 for(i=udmamode; i>=0; i--) {
1592 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1593 GetPciConfig2(0x56, reg56);
1594 reg56 &= ~(0xf << (dev * 4));
1595 reg56 |= ((USHORT)i << (dev * 4));
1596 SetPciConfig2(0x56, reg56);
1597 ChangePciConfig1(0x54, a | (0x01 << dev));
1598 // 44
1599 GetPciConfig4(0x44, reg44);
1600 reg44 = (reg44 & ~(0xff << bit_offset)) |
1601 (sw_dma_modes[2] << bit_offset);
1602 SetPciConfig4(0x44, reg44);
1603 // 40
1604 GetPciConfig4(0x40, reg40);
1605 reg40 = (reg40 & ~(0xff << bit_offset)) |
1606 (sw_pio_modes[8+i] << bit_offset);
1607 SetPciConfig4(0x40, reg40);
1608 return;
1609 }
1610 }
1611
1612 for(i=wdmamode; i>=0; i--) {
1613 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1614
1615 ChangePciConfig1(0x54, a & ~(0x01 << dev));
1616 // 44
1617 GetPciConfig4(0x44, reg44);
1618 reg44 = (reg44 & ~(0xff << bit_offset)) |
1619 (sw_dma_modes[wdmamode] << bit_offset);
1620 SetPciConfig4(0x44, reg44);
1621 // 40
1622 GetPciConfig4(0x40, reg40);
1623 reg40 = (reg40 & ~(0xff << bit_offset)) |
1624 (sw_pio_modes[5+i] << bit_offset);
1625 SetPciConfig4(0x40, reg40);
1626 return;
1627 }
1628 }
1629 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
1630 // SetPciConfig4(0x44, sw_pio_modes[apiomode]);
1631 if(VendorID == ATA_ATI_ID) {
1632 // special case for ATI
1633 // Seems, that PATA ATI are just re-brended ServerWorks
1634 USHORT reg4a;
1635 // 4a
1636 GetPciConfig2(0x4a, reg4a);
1637 reg4a = (reg4a & ~(0xf << (dev*4))) |
1638 (apiomode << (dev*4));
1639 SetPciConfig2(0x4a, reg4a);
1640 }
1641
1642 // 40
1643 GetPciConfig4(0x40, reg40);
1644 reg40 = (reg40 & ~(0xff << bit_offset)) |
1645 (sw_pio_modes[apiomode] << bit_offset);
1646 SetPciConfig4(0x40, reg40);
1647 return;
1648 break; }
1649 case ATA_SILICON_IMAGE_ID: {
1650 l_ATA_SILICON_IMAGE_ID:
1651 /********************/
1652 /* SiliconImage/CMD */
1653 /********************/
1654 if(ChipType == SIIMIO) {
1655
1656 static const UCHAR sil_modes[7] =
1657 { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
1658 static const USHORT sil_wdma_modes[3] =
1659 { 0x2208, 0x10c2, 0x10c1 };
1660 static const USHORT sil_pio_modes[6] =
1661 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1, 0x10c1 };
1662
1663 UCHAR ureg = 0xac + ((UCHAR)DeviceNumber * 0x02) + ((UCHAR)Channel * 0x10);
1664 UCHAR uval;
1665 UCHAR mreg = Channel ? 0x84 : 0x80;
1666 UCHAR mask = DeviceNumber ? 0x30 : 0x03;
1667 UCHAR mode;
1668
1669 GetPciConfig1(ureg, uval);
1670 GetPciConfig1(mreg, mode);
1671
1672 /* enable UDMA mode */
1673 for(i = udmamode; i>=0; i--) {
1674
1675 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1676 SetPciConfig1(mreg, mode | mask);
1677 SetPciConfig1(ureg, (uval & 0x3f) | sil_modes[i]);
1678 return;
1679 }
1680 }
1681 /* enable WDMA mode */
1682 for(i = wdmamode; i>=0; i--) {
1683
1684 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1685 SetPciConfig1(mreg, mode | (mask & 0x22));
1686 SetPciConfig2(ureg - 0x4, sil_wdma_modes[i]);
1687 return;
1688 }
1689 }
1690 /* restore PIO mode */
1691 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
1692
1693 SetPciConfig1(mreg, mode | (mask & 0x11));
1694 SetPciConfig2(ureg - 0x8, sil_pio_modes[apiomode]);
1695 return;
1696
1697 } else {
1698
1699 static const UCHAR cmd_modes[2][6] = {
1700 { 0x31, 0x21, 0x011, 0x25, 0x15, 0x05 },
1701 { 0xc2, 0x82, 0x042, 0x8a, 0x4a, 0x0a } };
1702 static const UCHAR cmd_wdma_modes[] = { 0x87, 0x32, 0x3f };
1703 static const UCHAR cmd_pio_modes[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f };
1704 ULONG treg = 0x54 + ((dev < 3) ? (dev << 1) : 7);
1705
1706 udmamode = min(udmamode, 5);
1707 /* enable UDMA mode */
1708 for(i = udmamode; i>=0; i--) {
1709 UCHAR umode;
1710
1711 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1712 GetPciConfig1(Channel ? 0x7b : 0x73, umode);
1713 umode &= ~(!(DeviceNumber & 1) ? 0x35 : 0xca);
1714 umode |= ( cmd_modes[DeviceNumber & 1][i]);
1715 SetPciConfig1(Channel ? 0x7b : 0x73, umode);
1716 return;
1717 }
1718 }
1719 /* make sure eventual UDMA mode from the BIOS is disabled */
1720 ChangePciConfig1(Channel ? 0x7b : 0x73, a & ~(!(DeviceNumber & 1) ? 0x35 : 0xca));
1721
1722 for(i = wdmamode; i>=0; i--) {
1723
1724 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1725 SetPciConfig1(treg, cmd_wdma_modes[i]);
1726 ChangePciConfig1(Channel ? 0x7b : 0x73, a & ~(!(DeviceNumber & 1) ? 0x35 : 0xca));
1727 return;
1728 }
1729 }
1730 /* set PIO mode timings */
1731 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
1732
1733 SetPciConfig1(treg, cmd_pio_modes[apiomode]);
1734 ChangePciConfig1(Channel ? 0x7b : 0x73, a & ~(!(DeviceNumber & 1) ? 0x35 : 0xca));
1735 return;
1736
1737 }
1738 return;
1739 break; }
1740 case ATA_SIS_ID: {
1741 /*******/
1742 /* SiS */
1743 /*******/
1744 PULONG sis_modes = NULL;
1745 static const ULONG sis_modes_new133[] =
1746 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
1747 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
1748 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
1749 static const ULONG sis_modes_old133[] =
1750 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
1751 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
1752 static const ULONG sis_modes_old[] =
1753 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303, 0x0301,
1754 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
1755 static const ULONG sis_modes_new100[] =
1756 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
1757 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
1758
1759 ULONG reg = 0;
1760 UCHAR reg57;
1761 ULONG reg_size = 0;
1762 ULONG offs;
1763
1764 switch(ChipType) {
1765 case SIS133NEW:
1766 sis_modes = (PULONG)(&sis_modes_new133[0]);
1767 reg_size = 4;
1768 GetPciConfig1(0x57, reg57);
1769 reg = (reg57 & 0x40 ? 0x70 : 0x40) + (dev * 4);
1770 break;
1771 case SIS133OLD:
1772 sis_modes = (PULONG)(&sis_modes_old133[0]);
1773 reg_size = 2;
1774 reg = 0x40 + (dev * 2);
1775 break;
1776 case SIS100NEW:
1777 sis_modes = (PULONG)(&sis_modes_new100[0]);
1778 reg_size = 2;
1779 reg = 0x40 + (dev * 2);
1780 break;
1781 case SIS100OLD:
1782 case SIS66:
1783 case SIS33:
1784 sis_modes = (PULONG)(&sis_modes_old[0]);
1785 reg_size = 2;
1786 reg = 0x40 + (dev * 2);
1787 break;
1788 }
1789
1790 offs = 5+3;
1791 for(i=udmamode; i>=0; i--) {
1792 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1793 if(reg_size == 4) {
1794 SetPciConfig4(reg, sis_modes[offs+i]);
1795 } else {
1796 SetPciConfig2(reg, (USHORT)sis_modes[offs+i]);
1797 }
1798 return;
1799 }
1800 }
1801
1802 offs = 5;
1803 for(i=wdmamode; i>=0; i--) {
1804 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1805 if(reg_size == 4) {
1806 SetPciConfig4(reg, sis_modes[offs+i]);
1807 } else {
1808 SetPciConfig2(reg, (USHORT)sis_modes[offs+i]);
1809 }
1810 return;
1811 }
1812 }
1813 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
1814 if(reg_size == 4) {
1815 SetPciConfig4(reg, sis_modes[apiomode]);
1816 } else {
1817 SetPciConfig2(reg, (USHORT)sis_modes[apiomode]);
1818 }
1819 return;
1820 break; }
1821 case 0x16ca:
1822 /* Cenatek Rocket Drive controller */
1823 if (wdmamode >= 0 &&
1824 (AtapiReadPort1(chan, IDX_BM_Status) &
1825 (DeviceNumber ? BM_STATUS_DRIVE_1_DMA : BM_STATUS_DRIVE_0_DMA))) {
1826 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + wdmamode);
1827 } else {
1828 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
1829 }
1830 return;
1831 case ATA_ITE_ID: { /* ITE IDE controller */
1832
1833 if(ChipType == ITE_33) {
1834 int a_speed = 3 << (dev * 4);
1835 int u_flag = 1 << dev;
1836 int u_speed = 0;
1837 int pio = 1;
1838 UCHAR reg48, reg4a;
1839 USHORT drive_enables;
1840 ULONG drive_timing;
1841
1842 GetPciConfig1(0x48, reg48);
1843 GetPciConfig1(0x4a, reg4a);
1844
1845 /*
1846 * Setting the DMA cycle time to 2 or 3 PCI clocks (60 and 91 nsec
1847 * at 33 MHz PCI clock) seems to cause BadCRC errors during DMA
1848 * transfers on some drives, even though both numbers meet the minimum
1849 * ATAPI-4 spec of 73 and 54 nsec for UDMA 1 and 2 respectively.
1850 * So the faster times are just commented out here. The good news is
1851 * that the slower cycle time has very little affect on transfer
1852 * performance.
1853 */
1854
1855 for(i=udmamode; i>=0; i--) {
1856 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1857 SetPciConfig1(0x48, reg48 | u_flag);
1858 reg4a &= ~a_speed;
1859 SetPciConfig1(0x4a, reg4a | u_speed);
1860 pio = 4;
1861 goto setup_drive_ite;
1862 }
1863 }
1864
1865 for(i=wdmamode; i>=0; i--) {
1866 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1867 SetPciConfig1(0x48, reg48 & ~u_flag);
1868 SetPciConfig1(0x4a, reg4a & ~a_speed);
1869 pio = 3;
1870 return;
1871 }
1872 }
1873 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
1874 SetPciConfig1(0x48, reg48 & ~u_flag);
1875 SetPciConfig1(0x4a, reg4a & ~a_speed);
1876
1877 pio = apiomode;
1878
1879 setup_drive_ite:
1880
1881 GetPciConfig2(0x40, drive_enables);
1882 GetPciConfig4(0x44, drive_timing);
1883
1884 /*
1885 * FIX! The DIOR/DIOW pulse width and recovery times in port 0x44
1886 * are being left at the default values of 8 PCI clocks (242 nsec
1887 * for a 33 MHz clock). These can be safely shortened at higher
1888 * PIO modes. The DIOR/DIOW pulse width and recovery times only
1889 * apply to PIO modes, not to the DMA modes.
1890 */
1891
1892 /*
1893 * Enable port 0x44. The IT8172G spec is confused; it calls
1894 * this register the "Slave IDE Timing Register", but in fact,
1895 * it controls timing for both master and slave drives.
1896 */
1897 drive_enables |= 0x4000;
1898
1899 drive_enables &= (0xc000 | (0x06 << (DeviceNumber*4)));
1900 if (pio > 1) {
1901 /* enable prefetch and IORDY sample-point */
1902 drive_enables |= (0x06 << (DeviceNumber*4));
1903 }
1904
1905 SetPciConfig2(0x40, drive_enables);
1906 } else
1907 if(ChipType == ITE_133) {
1908 static const UCHAR udmatiming[] =
1909 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 };
1910 static const UCHAR chtiming[] =
1911 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 };
1912 ULONG offset = (Channel<<2) + DeviceNumber;
1913 UCHAR reg54;
1914
1915 for(i=udmamode; i>=0; i--) {
1916 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1917 ChangePciConfig1(0x50, a & ~(1 << (dev + 3)) );
1918 SetPciConfig1(0x56 + offset, udmatiming[i]);
1919 return;
1920 }
1921 }
1922
1923 for(i=wdmamode; i>=0; i--) {
1924 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1925
1926 ChangePciConfig1(0x50, a | (1 << (dev + 3)) );
1927 GetPciConfig1(0x54 + offset, reg54);
1928 if(reg54 < chtiming[i+5]) {
1929 SetPciConfig1(0x54 + offset, chtiming[i+5]);
1930 }
1931 return;
1932 }
1933 }
1934 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
1935 ChangePciConfig1(0x50, a | (1 << (dev + 3)) );
1936 GetPciConfig1(0x54 + offset, reg54);
1937 if(reg54 < chtiming[apiomode]) {
1938 SetPciConfig1(0x54 + offset, chtiming[apiomode]);
1939 }
1940 return;
1941 } else
1942 if(ChipType == ITE_133_NEW) {
1943 //static const USHORT reg54_timings[] = { 0x0000, 0x0000, 0x0001, 0x0001, 0x0001, 0x1001, 0x1001 };
1944 static const UCHAR udmatiming[] =
1945 { 0x00, 0x01, 0x10, 0x01, 0x10, 0x01, 0x10 };
1946 static const UCHAR timings[] =
1947 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
1948 0x23, 0x23, 0x23, 0x23, 0x23, 0x02, 0x02 };
1949 BOOLEAN udma_ok = FALSE;
1950 BOOLEAN ok = FALSE;
1951 UCHAR timing = 0;
1952
1953 WCHAR reg40;
1954 UCHAR reg44;
1955 USHORT reg4a;
1956 USHORT reg54;
1957 USHORT mask40=0, new40=0;
1958 UCHAR mask44=0, new44=0;
1959
1960 GetPciConfig2(0x40, reg40);
1961 GetPciConfig1(0x44, reg44);
1962 GetPciConfig2(0x4a, reg4a);
1963 GetPciConfig2(0x54, reg54);
1964
1965 if(!(reg54 & (0x10 << dev))) {
1966 // 80-pin check
1967 udmamode = min(udmamode, 2);
1968 }
1969
1970 for(i=udmamode; i>=0; i--) {
1971 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
1972 ChangePciConfig1(0x48, a | (1 << dev) );
1973 ChangePciConfig2(0x4a,
1974 (a & ~(0x3 << (dev*4))) |
1975 (udmatiming[i] << (dev*4)) );
1976 ok=TRUE;
1977 udma_ok=TRUE;
1978 timing = timings[i+8];
1979 break;
1980 }
1981 }
1982
1983 for(i=wdmamode; !ok && i>=0; i--) {
1984 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
1985
1986 ok=TRUE;
1987 timing = timings[i+5];
1988 break;
1989 }
1990 }
1991
1992 if(!ok) {
1993 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
1994 timing = timings[apiomode];
1995 }
1996
1997 if(!udma_ok) {
1998 ChangePciConfig1(0x48, a & ~(1 << dev) );
1999 ChangePciConfig2(0x4a, a & ~(0x3 << (dev << 2)) );
2000 }
2001 if (udma_ok && udmamode >= ATA_UDMA2) {
2002 reg54 |= (0x1 << dev);
2003 } else {
2004 reg54 &= ~(0x1 << dev);
2005 }
2006 if (udma_ok && udmamode >= ATA_UDMA5) {
2007 reg54 |= (0x1000 << dev);
2008 } else {
2009 reg54 &= ~(0x1000 << dev);
2010 }
2011 SetPciConfig2(0x54, reg54 );
2012
2013 reg40 &= 0xff00;
2014 reg40 |= 0x4033;
2015
2016 if(!(DeviceNumber & 1)) {
2017 reg40 |= (isAtapi ? 0x04 : 0x00);
2018 mask40 = 0x3300;
2019 new40 = timing << 8;
2020 } else {
2021 reg40 |= (isAtapi ? 0x40 : 0x00);
2022 mask44 = 0x0f;
2023 new44 = ((timing & 0x30) >> 2) |
2024 (timing & 0x03);
2025 }
2026 SetPciConfig2(0x40, (reg40 & ~mask40) | new40);
2027 SetPciConfig1(0x44, (reg44 & ~mask44) | new44);
2028 return;
2029 }
2030
2031 return;
2032 break; }
2033 case 0x3388:
2034 /* HiNT Corp. VXPro II EIDE */
2035 if (wdmamode >= 0 &&
2036 (AtapiReadPort1(chan, IDX_BM_Status) &
2037 (DeviceNumber ? BM_STATUS_DRIVE_1_DMA : BM_STATUS_DRIVE_0_DMA))) {
2038 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_DMA);
2039 } else {
2040 AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode);
2041 }
2042 return;
2043 case ATA_JMICRON_ID: {
2044
2045 UCHAR reg40;
2046 GetPciConfig1(0x40, reg40);
2047
2048 if(reg40 & 0x08) {
2049 // 80-pin check
2050 udmamode = min(udmamode, 2);
2051 }
2052 /* Nothing to do to setup mode, the controller snoop SET_FEATURE cmd. */
2053 if(apiomode >= 4)
2054 apiomode = 4;
2055 for(i=udmamode; i>=0; i--) {
2056 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_UDMA0 + i)) {
2057 return;
2058 }
2059 }
2060 for(i=wdmamode; i>=0; i--) {
2061 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_WDMA0 + i)) {
2062 return;
2063 }
2064 }
2065 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode)) {
2066 return;
2067 }
2068 return;
2069 break; }
2070 }
2071
2072 try_generic_dma:
2073
2074 /* unknown controller chip */
2075
2076 /* better not try generic DMA on ATAPI devices it almost never works */
2077 if (isAtapi) {
2078 KdPrint2((PRINT_PREFIX "ATAPI on unknown controller -> PIO\n"));
2079 udmamode =
2080 wdmamode = -1;
2081 }
2082
2083 /* if controller says its setup for DMA take the easy way out */
2084 /* the downside is we dont know what DMA mode we are in */
2085 if ((udmamode >= 0 || /*wdmamode > 1*/ wdmamode >= 0) &&
2086 /*deviceExtension->BaseIoAddressBM[lChannel]*/ (deviceExtension->BusMaster==DMA_MODE_BM) &&
2087 (GetDmaStatus(deviceExtension, lChannel) &
2088 (!(DeviceNumber & 1) ?
2089 BM_STATUS_DRIVE_0_DMA : BM_STATUS_DRIVE_1_DMA))) {
2090 // LunExt->TransferMode = ATA_DMA;
2091 // return;
2092 KdPrint2((PRINT_PREFIX "try DMA on unknown controller\n"));
2093 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_DMA)) {
2094 return;
2095 }
2096 }
2097
2098 #if 0
2099 /* well, we have no support for this, but try anyways */
2100 if ((wdmamode >= 0 && apiomode >= 4) && deviceExtension->BaseIoAddressBM[lChannel]) {
2101 if(AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_DMA/* + wdmamode*/)) {
2102 return;
2103 }
2104 }
2105 #endif
2106
2107 KdPrint2((PRINT_PREFIX "try PIO%d on unknown controller\n", apiomode));
2108 if(!AtaSetTransferMode(deviceExtension, DeviceNumber, lChannel, LunExt, ATA_PIO0 + apiomode)) {
2109 KdPrint2((PRINT_PREFIX "fall to PIO on unknown controller\n"));
2110 LunExt->TransferMode = ATA_PIO;
2111 }
2112 return;
2113 } // end AtapiDmaInit()
2114
2115
2116 VOID
2117 NTAPI
2118 cyrix_timing(
2119 IN PHW_DEVICE_EXTENSION deviceExtension,
2120 IN ULONG dev, // physical device number (0-3)
2121 IN CHAR mode
2122 )
2123 {
2124 // ASSERT(dev/2 >= deviceExtension->Channel);
2125 // PHW_CHANNEL chan = &(deviceExtension->chan[dev/2-deviceExtension->Channel]);
2126 ULONG reg20 = 0x0000e132;
2127 ULONG reg24 = 0x00017771;
2128
2129 if(mode == ATA_PIO5)
2130 mode = ATA_PIO4;
2131
2132 switch (mode) {
2133 case ATA_PIO0: reg20 = 0x0000e132; break;
2134 case ATA_PIO1: reg20 = 0x00018121; break;
2135 case ATA_PIO2: reg20 = 0x00024020; break;
2136 case ATA_PIO3: reg20 = 0x00032010; break;
2137 case ATA_PIO4:
2138 case ATA_PIO5: reg20 = 0x00040010; break;
2139 case ATA_WDMA2: reg24 = 0x00002020; break;
2140 case ATA_UDMA2: reg24 = 0x00911030; break;
2141 }
2142 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),(dev*8) + 0x20, reg20);
2143 AtapiWritePortEx4(NULL, (ULONGIO_PTR)(&deviceExtension->BaseIoAddressBM_0),(dev*8) + 0x24, reg24);
2144 } // cyrix_timing()
2145
2146 VOID
2147 NTAPI
2148 promise_timing(
2149 IN PHW_DEVICE_EXTENSION deviceExtension,
2150 IN ULONG dev, // physical device number (0-3)
2151 IN CHAR mode
2152 )
2153 {
2154 PVOID HwDeviceExtension = (PVOID)deviceExtension;
2155 ULONG slotNumber = deviceExtension->slotNumber;
2156 ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
2157
2158 ULONG ChipType = deviceExtension->HwFlags & CHIPTYPE_MASK;
2159 //ULONG ChipFlags = deviceExtension->HwFlags & CHIPFLAG_MASK;
2160
2161 ULONG timing = 0;
2162
2163 if(mode == ATA_PIO5)
2164 mode = ATA_PIO4;
2165
2166 switch(ChipType) {
2167 case PROLD:
2168 switch (mode) {
2169 default:
2170 case ATA_PIO0: timing = 0x004ff329; break;
2171 case ATA_PIO1: timing = 0x004fec25; break;
2172 case ATA_PIO2: timing = 0x004fe823; break;
2173 case ATA_PIO3: timing = 0x004fe622; break;
2174 case ATA_PIO4: timing = 0x004fe421; break;
2175 case ATA_WDMA0: timing = 0x004567f3; break;
2176 case ATA_WDMA1: timing = 0x004467f3; break;
2177 case ATA_WDMA2: timing = 0x004367f3; break;
2178 case ATA_UDMA0: timing = 0x004367f3; break;
2179 case ATA_UDMA1: timing = 0x004247f3; break;
2180 case ATA_UDMA2: timing = 0x004127f3; break;
2181 }
2182 break;
2183
2184 case PRNEW:
2185 switch (mode) {
2186 default:
2187 case ATA_PIO0: timing = 0x004fff2f; break;
2188 case ATA_PIO1: timing = 0x004ff82a; break;
2189 case ATA_PIO2: timing = 0x004ff026; break;
2190 case ATA_PIO3: timing = 0x004fec24; break;
2191 case ATA_PIO4: timing = 0x004fe822; break;
2192 case ATA_WDMA0: timing = 0x004acef6; break;
2193 case ATA_WDMA1: timing = 0x0048cef6; break;
2194 case ATA_WDMA2: timing = 0x0046cef6; break;
2195 case ATA_UDMA0: timing = 0x0046cef6; break;
2196 case ATA_UDMA1: timing = 0x00448ef6; break;
2197 case ATA_UDMA2: timing = 0x00436ef6; break;
2198 case ATA_UDMA3: timing = 0x00424ef6; break;
2199 case ATA_UDMA4: timing = 0x004127f3; break;
2200 case ATA_UDMA5: timing = 0x004127f3; break;
2201 }
2202 break;
2203 default:
2204 return;
2205 }
2206 SetPciConfig4(0x60 + (dev<<2), timing);
2207 } // end promise_timing()
2208
2209
2210 VOID
2211 NTAPI
2212 hpt_timing(
2213 IN PHW_DEVICE_EXTENSION deviceExtension,
2214 IN ULONG dev, // physical device number (0-3)
2215 IN CHAR mode
2216 )
2217 {
2218 PVOID HwDeviceExtension = (PVOID)deviceExtension;
2219 ULONG slotNumber = deviceExtension->slotNumber;
2220 ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
2221
2222 ULONG ChipType = deviceExtension->HwFlags & CHIPTYPE_MASK;
2223 //ULONG ChipFlags = deviceExtension->HwFlags & CHIPFLAG_MASK;
2224
2225 ULONG timing = 0;
2226
2227 if(mode == ATA_PIO5)
2228 mode = ATA_PIO4;
2229
2230 switch(ChipType) {
2231 case HPT374:
2232
2233 switch (mode) { /* HPT374 */
2234 case ATA_PIO0: timing = 0x0ac1f48a; break;
2235 case ATA_PIO1: timing = 0x0ac1f465; break;
2236 case ATA_PIO2: timing = 0x0a81f454; break;
2237 case ATA_PIO3: timing = 0x0a81f443; break;
2238 case ATA_PIO4: timing = 0x0a81f442; break;
2239 case ATA_WDMA0: timing = 0x228082ea; break;
2240 case ATA_WDMA1: timing = 0x22808254; break;
2241 case ATA_WDMA2: timing = 0x22808242; break;
2242 case ATA_UDMA0: timing = 0x121882ea; break;
2243 case ATA_UDMA1: timing = 0x12148254; break;
2244 case ATA_UDMA2: timing = 0x120c8242; break;
2245 case ATA_UDMA3: timing = 0x128c8242; break;
2246 case ATA_UDMA4: timing = 0x12ac8242; break;
2247 case ATA_UDMA5: timing = 0x12848242; break;
2248 case ATA_UDMA6: timing = 0x12808242; break;
2249 default: timing = 0x0d029d5e;
2250 }
2251 break;
2252
2253 case HPT372:
2254
2255 switch (mode) { /* HPT372 */
2256 case ATA_PIO0: timing = 0x0d029d5e; break;
2257 case ATA_PIO1: timing = 0x0d029d26; break;
2258 case ATA_PIO2: timing = 0x0c829ca6; break;
2259 case ATA_PIO3: timing = 0x0c829c84; break;
2260 case ATA_PIO4: timing = 0x0c829c62; break;
2261 case ATA_WDMA0: timing = 0x2c82922e; break;
2262 case ATA_WDMA1: timing = 0x2c829266; break;
2263 case ATA_WDMA2: timing = 0x2c829262; break;
2264 case ATA_UDMA0: timing = 0x1c829c62; break;
2265 case ATA_UDMA1: timing = 0x1c9a9c62; break;
2266 case ATA_UDMA2: timing = 0x1c929c62; break;
2267 case ATA_UDMA3: timing = 0x1c8e9c62; break;
2268 case ATA_UDMA4: timing = 0x1c8a9c62; break;
2269 case ATA_UDMA5: timing = 0x1c8a9c62; break;
2270 case ATA_UDMA6: timing = 0x1c869c62; break;
2271 default: timing = 0x0d029d5e;
2272 }
2273 break;
2274
2275 case HPT370:
2276
2277 switch (mode) { /* HPT370 */
2278 case ATA_PIO0: timing = 0x06914e57; break;
2279 case ATA_PIO1: timing = 0x06914e43; break;
2280 case ATA_PIO2: timing = 0x06514e33; break;
2281 case ATA_PIO3: timing = 0x06514e22; break;
2282 case ATA_PIO4: timing = 0x06514e21; break;
2283 case ATA_WDMA0: timing = 0x26514e97; break;
2284 case ATA_WDMA1: timing = 0x26514e33; break;
2285 case ATA_WDMA2: timing = 0x26514e21; break;
2286 case ATA_UDMA0: timing = 0x16514e31; break;
2287 case ATA_UDMA1: timing = 0x164d4e31; break;
2288 case ATA_UDMA2: timing = 0x16494e31; break;
2289 case ATA_UDMA3: timing = 0x166d4e31; break;
2290 case ATA_UDMA4: timing = 0x16454e31; break;
2291 case ATA_UDMA5: timing = 0x16454e31; break;
2292 default: timing = 0x06514e57;
2293 }
2294
2295 case HPT366: {
2296 UCHAR reg41;
2297
2298 GetPciConfig1(0x41 + (dev << 2), reg41);
2299
2300 switch (reg41) {
2301 case 0x85: /* 25Mhz */
2302 switch (mode) {
2303 case ATA_PIO0: timing = 0x40d08585; break;
2304 case ATA_PIO1: timing = 0x40d08572; break;
2305 case ATA_PIO2: timing = 0x40ca8542; break;
2306 case ATA_PIO3: timing = 0x40ca8532; break;
2307 case ATA_PIO4: timing = 0x40ca8521; break;
2308 case ATA_WDMA2: timing = 0x20ca8521; break;
2309 case ATA_UDMA2: timing = 0x10cf8521; break;
2310 case ATA_UDMA4: timing = 0x10c98521; break;
2311 default: timing = 0x01208585;
2312 }
2313 break;
2314 default:
2315 case 0xa7: /* 33MHz */
2316 switch (mode) {
2317 case ATA_PIO0: timing = 0x40d0a7aa; break;
2318 case ATA_PIO1: timing = 0x40d0a7a3; break;
2319 case ATA_PIO2: timing = 0x40d0a753; break;
2320 case ATA_PIO3: timing = 0x40c8a742; break;
2321 case ATA_PIO4: timing = 0x40c8a731; break;
2322 case ATA_WDMA0: timing = 0x20c8a797; break;
2323 case ATA_WDMA1: timing = 0x20c8a732; break;
2324 case ATA_WDMA2: timing = 0x20c8a731; break;
2325 case ATA_UDMA0: timing = 0x10c8a731; break;
2326 case ATA_UDMA1: timing = 0x10cba731; break;
2327 case ATA_UDMA2: timing = 0x10caa731; break;
2328 case ATA_UDMA3: timing = 0x10cfa731; break;
2329 case ATA_UDMA4: timing = 0x10c9a731; break;
2330 default: timing = 0x0120a7a7;
2331 }
2332 break;
2333 case 0xd9: /* 40Mhz */
2334 switch (mode) {
2335 case ATA_PIO0: timing = 0x4018d9d9; break;
2336 case ATA_PIO1: timing = 0x4010d9c7; break;
2337 case ATA_PIO2: timing = 0x4010d997; break;
2338 case ATA_PIO3: timing = 0x4010d974; break;
2339 case ATA_PIO4: timing = 0x4008d963; break;
2340 case ATA_WDMA2: timing = 0x2008d943; break;
2341 case ATA_UDMA2: timing = 0x100bd943; break;
2342 case ATA_UDMA4: timing = 0x100fd943; break;
2343 default: timing = 0x0120d9d9;
2344 }
2345 }
2346 break; }
2347 }
2348
2349 SetPciConfig4(0x40 + (dev<<2), timing);
2350 } // end hpt_timing()
2351
2352
2353 #define FIT(v,min,max) (((v)>(max)?(max):(v))<(min)?(min):(v))
2354
2355 VOID
2356 NTAPI
2357 via82c_timing(
2358 IN PHW_DEVICE_EXTENSION deviceExtension,
2359 IN ULONG dev, // physical device number (0-3)
2360 IN CHAR mode
2361 )
2362 {
2363 PVOID HwDeviceExtension = (PVOID)deviceExtension;
2364 ULONG slotNumber = deviceExtension->slotNumber;
2365 ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
2366
2367 USHORT T = 1000 / /* PciBusClockMHz()*/ 33;
2368
2369 USHORT setup = 0;
2370 USHORT active = 0;
2371 USHORT recover = 0;
2372 USHORT cycle = 0;
2373
2374 UCHAR t;
2375
2376 switch(mode) {
2377 default:
2378 case ATA_PIO0: setup = 70; active = 165; recover = 150; cycle = 600; break;
2379 case ATA_PIO1: setup = 50; active = 125; recover = 100; cycle = 383; break;
2380 case ATA_PIO2: setup = 30; active = 100; recover = 90; cycle = 240; break;
2381 case ATA_PIO3: setup = 30; active = 80; recover = 70; cycle = 180; break;
2382 case ATA_PIO4: setup = 25; active = 70; recover = 25; cycle = 120; break;
2383 case ATA_PIO5: setup = 20; active = 50; recover = 30; cycle = 100; break;
2384 }
2385
2386 setup = (setup -1)/(T+1);
2387 active = (active -1)/(T+1);
2388 recover = (recover-1)/(T+1);
2389 cycle = (cycle -1)/(T+1);
2390
2391 if (active + recover < cycle) {
2392 active += (cycle - (active + recover)) / 2;
2393 recover = cycle - active;
2394 }
2395
2396 // Newer chips dislike this:
2397 if(/*!(deviceExtension->HwFlags & VIAAST)*/
2398 deviceExtension->MaxTransferMode < ATA_UDMA6) {
2399 /* PIO address setup */
2400 GetPciConfig1(0x4c, t);
2401 t = (t & ~(3 << ((3 - dev) << 1))) | (FIT(setup - 1, 0, 3) << ((3 - dev) << 1));
2402 SetPciConfig1(0x4c, t);
2403 }
2404
2405 /* PIO active & recover */
2406 SetPciConfig1(0x4b-dev, (FIT(active - 1, 0, 0xf) << 4) | FIT(recover - 1, 0, 0xf) );
2407 } // end via82c_timing()
2408
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