reactos/drivers/storage/ide/uniata/uata_ctl.h

   1 /*++
   2
   3 Copyright (c) 2004-2005 Alexandr A. Telyatnikov (Alter)
   4
   5 Module Name:
   6     uata_ctl.h
   7
   8 Abstract:
   9     This header contains definitions for private UniATA SRB_IOCTL.
  10
  11 Author:
  12     Alexander A. Telyatnikov (Alter)
  13
  14 Environment:
  15     kernel mode only
  16
  17 Notes:
  18
  19     THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  20     IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  21     OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  22     IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  23     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  24     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  25     DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  26     THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  28     THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29
  30 Revision History:
  31
  32 --*/
  33
  34 #ifndef __UNIATA_IO_CONTROL_CODES__H__
  35 #define __UNIATA_IO_CONTROL_CODES__H__
  36
  37 //#include "scsi.h"
  38
  39 #pragma pack(push, 8)
  40
  41 #ifdef __cplusplus
  42 extern "C" {
  43 #endif //__cplusplus
  44
  45 #define AHCI_MAX_PORT                   32
  46 #define IDE_MAX_CHAN          16
  47 // Thanks to SATA Port Multipliers:
  48 #define IDE_MAX_LUN_PER_CHAN  2
  49 #define IDE_MAX_LUN           (AHCI_MAX_PORT*IDE_MAX_LUN_PER_CHAN)
  50
  51 #define MAX_QUEUE_STAT        8
  52
  53 #define UNIATA_COMM_PORT_VENDOR_STR "UNIATA  " "Management Port " UNIATA_VER_STR
  54
  55 #ifndef UNIATA_CORE
  56
  57 #define IOCTL_SCSI_MINIPORT_UNIATA_FIND_DEVICES    ((FILE_DEVICE_SCSI << 16) + 0x09a0)
  58 #define IOCTL_SCSI_MINIPORT_UNIATA_DELETE_DEVICE   ((FILE_DEVICE_SCSI << 16) + 0x09a1)
  59 #define IOCTL_SCSI_MINIPORT_UNIATA_SET_MAX_MODE    ((FILE_DEVICE_SCSI << 16) + 0x09a2)
  60 #define IOCTL_SCSI_MINIPORT_UNIATA_GET_MODE        ((FILE_DEVICE_SCSI << 16) + 0x09a3)
  61 #define IOCTL_SCSI_MINIPORT_UNIATA_ADAPTER_INFO    ((FILE_DEVICE_SCSI << 16) + 0x09a4)
  62 //#define IOCTL_SCSI_MINIPORT_UNIATA_LUN_IDENT       ((FILE_DEVICE_SCSI << 16) + 0x09a5) -> IOCTL_SCSI_MINIPORT_IDENTIFY
  63 #define IOCTL_SCSI_MINIPORT_UNIATA_RESETBB         ((FILE_DEVICE_SCSI << 16) + 0x09a5)
  64 #define IOCTL_SCSI_MINIPORT_UNIATA_RESET_DEVICE    ((FILE_DEVICE_SCSI << 16) + 0x09a6)
  65 #define IOCTL_SCSI_MINIPORT_UNIATA_REG_IO          ((FILE_DEVICE_SCSI << 16) + 0x09a7)
  66 #define IOCTL_SCSI_MINIPORT_UNIATA_GET_VERSION     ((FILE_DEVICE_SCSI << 16) + 0x09a8)
  67
  68 typedef struct _ADDREMOVEDEV {
  69     ULONG WaitForPhysicalLink; // us
  70     ULONG Flags;
  71
  72 #define UNIATA_REMOVE_FLAGS_HIDE   0x01
  73 #define UNIATA_ADD_FLAGS_UNHIDE    0x01
  74
  75 } ADDREMOVEDEV, *PADDREMOVEDEV;
  76
  77 typedef struct _SETTRANSFERMODE {
  78     ULONG MaxMode;
  79     ULONG OrigMode;
  80     BOOLEAN ApplyImmediately;
  81     UCHAR Reserved[3];
  82 } SETTRANSFERMODE, *PSETTRANSFERMODE;
  83
  84 typedef struct _GETTRANSFERMODE {
  85     ULONG MaxMode;
  86     ULONG OrigMode;
  87     ULONG CurrentMode;
  88     ULONG PhyMode; // since v0.42i6
  89 } GETTRANSFERMODE, *PGETTRANSFERMODE;
  90
  91 typedef struct _GETDRVVERSION {
  92     ULONG Length;
  93     USHORT VersionMj;
  94     USHORT VersionMn;
  95     USHORT SubVerMj;
  96     USHORT SubVerMn;
  97     ULONG Reserved;
  98 } GETDRVVERSION, *PGETDRVVERSION;
  99
 100 typedef struct _CHANINFO {
 101     ULONG               MaxTransferMode; // may differ from Controller's value due to 40-pin cable
 102     ULONG               ChannelCtrlFlags;
 103     LONGLONG QueueStat[MAX_QUEUE_STAT];
 104     LONGLONG ReorderCount;
 105     LONGLONG IntersectCount;
 106     LONGLONG TryReorderCount;
 107     LONGLONG TryReorderHeadCount;
 108     LONGLONG TryReorderTailCount; /* in-order requests */
 109 //    ULONG               opt_MaxTransferMode; // user-specified
 110 } CHANINFO, *PCHANINFO;
 111
 112 typedef struct _ADAPTERINFO {
 113     // Device identification
 114     ULONG HeaderLength;
 115     ULONG DevID;
 116     ULONG RevID;
 117     ULONG slotNumber;
 118     ULONG SystemIoBusNumber;
 119     ULONG DevIndex;
 120
 121     ULONG Channel;
 122
 123     ULONG   HbaCtrlFlags;
 124     BOOLEAN simplexOnly;
 125     BOOLEAN MemIo;
 126     BOOLEAN UnknownDev;
 127     BOOLEAN MasterDev;
 128
 129     ULONG   MaxTransferMode;
 130     ULONG   HwFlags;
 131     ULONG   OrigAdapterInterfaceType;
 132
 133     CHAR    DeviceName[64];
 134
 135     ULONG BusInterruptLevel;    // Interrupt level
 136     ULONG InterruptMode;        // Interrupt Mode (Level or Edge)
 137     ULONG BusInterruptVector;
 138     // Number of channels being supported by one instantiation
 139     // of the device extension. Normally (and correctly) one, but
 140     // with so many broken PCI IDE controllers being sold, we have
 141     // to support them.
 142     ULONG NumberChannels;
 143     BOOLEAN ChanInfoValid;
 144
 145     UCHAR   NumberLuns;  // per channel
 146     BOOLEAN LunInfoValid;
 147     BOOLEAN ChanHeaderLengthValid; // since v0.42i8
 148
 149     ULONG   AdapterInterfaceType;
 150     ULONG   ChanHeaderLength;
 151     ULONG   LunHeaderLength;
 152
 153     //CHANINFO Chan[0];
 154
 155 } ADAPTERINFO, *PADAPTERINFO;
 156
 157 #ifdef USER_MODE
 158
 159 typedef enum _INTERFACE_TYPE {
 160     InterfaceTypeUndefined = -1,
 161     Internal,
 162     Isa,
 163     Eisa,
 164     MicroChannel,
 165     TurboChannel,
 166     PCIBus,
 167     VMEBus,
 168     NuBus,
 169     PCMCIABus,
 170     CBus,
 171     MPIBus,
 172     MPSABus,
 173     ProcessorInternal,
 174     InternalPowerBus,
 175     PNPISABus,
 176     MaximumInterfaceType
 177 } INTERFACE_TYPE, *PINTERFACE_TYPE;
 178
 179 typedef struct _PCI_SLOT_NUMBER {
 180     union {
 181         struct {
 182             ULONG   DeviceNumber:5;
 183             ULONG   FunctionNumber:3;
 184             ULONG   Reserved:24;
 185         } bits;
 186         ULONG   AsULONG;
 187     } u;
 188 } PCI_SLOT_NUMBER, *PPCI_SLOT_NUMBER;
 189
 190 #endif
 191
 192 #ifndef ATA_FLAGS_DRDY_REQUIRED
 193
 194 //The ATA_PASS_THROUGH_DIRECT structure is used in conjunction with an IOCTL_ATA_PASS_THROUGH_DIRECT request to instruct the port driver to send an embedded ATA command to the target device.
 195
 196 typedef struct _ATA_PASS_THROUGH_DIRECT {
 197   USHORT  Length;
 198   USHORT  AtaFlags;
 199   UCHAR  PathId;
 200   UCHAR  TargetId;
 201   UCHAR  Lun;
 202   UCHAR  ReservedAsUchar;
 203   ULONG  DataTransferLength;
 204   ULONG  TimeOutValue;
 205   ULONG  ReservedAsUlong;
 206   PVOID  DataBuffer;
 207   union {
 208       UCHAR  PreviousTaskFile[8];
 209       IDEREGS Regs;
 210   };
 211   union {
 212       UCHAR  CurrentTaskFile[8];
 213       IDEREGS RegsH;
 214   };
 215 } ATA_PASS_THROUGH_DIRECT, *PATA_PASS_THROUGH_DIRECT;
 216
 217 #define    ATA_FLAGS_DRDY_REQUIRED 0x01 // Wait for DRDY status from the device before sending the command to the device.
 218 #define    ATA_FLAGS_DATA_OUT      0x02 // Write data to the device.
 219 #define    ATA_FLAGS_DATA_IN       0x04 // Read data from the device.
 220 #define    ATA_FLAGS_48BIT_COMMAND 0x08 // The ATA command to be send uses the 48 bit LBA feature set.
 221                                         //   When this flag is set, the contents of the PreviousTaskFile member in the
 222                                         //   ATA_PASS_THROUGH_DIRECT structure should be valid.
 223 #define    ATA_FLAGS_USE_DMA       0x10 // Set the transfer mode to DMA.
 224 #define    ATA_FLAGS_NO_MULTIPLE   0x20 // Read single sector only.
 225
 226 #endif //ATA_FLAGS_DRDY_REQUIRED
 227
 228 #pragma pack(pop)
 229
 230 #pragma pack(push, 1)
 231 typedef struct _IDEREGS_EX {
 232     union {
 233         UCHAR    bFeaturesReg;           // Used for specifying SMART "commands" on input.
 234         UCHAR    bErrorReg;              // Error on output.
 235     };
 236         UCHAR    bSectorCountReg;        // IDE sector count register
 237         UCHAR    bSectorNumberReg;       // IDE sector number register
 238         UCHAR    bCylLowReg;             // IDE low order cylinder value
 239         UCHAR    bCylHighReg;            // IDE high order cylinder value
 240         UCHAR    bDriveHeadReg;          // IDE drive/head register
 241     union {
 242         UCHAR    bCommandReg;            // Actual IDE command.
 243         UCHAR    bStatusReg;             // Status register.
 244     };
 245         UCHAR    bOpFlags;               // 00 - send
 246                                          // 01 - read regs
 247                                          // 08 - lba48
 248                                          // 10 - treat timeout as msec
 249
 250 #define UNIATA_SPTI_EX_SND               0x00
 251 #define UNIATA_SPTI_EX_RCV               0x01
 252 #define UNIATA_SPTI_EX_LBA48             0x08
 253 //#define UNIATA_SPTI_EX_SPEC_TO           0x10
 254 //#define UNIATA_SPTI_EX_FREEZE_TO         0x20 // do not reset device on timeout and keep interrupts disabled
 255 #define UNIATA_SPTI_EX_USE_DMA           0x10 // Force DMA transfer mode
 256
 257 // use 'invalid' combination to specify special TO options
 258 #define UNIATA_SPTI_EX_SPEC_TO           (ATA_FLAGS_DATA_OUT | ATA_FLAGS_DATA_IN)
 259
 260         UCHAR    bFeaturesRegH;          // feature (high part for LBA48 mode)
 261         UCHAR    bSectorCountRegH;       // IDE sector count register (high part for LBA48 mode)
 262         UCHAR    bSectorNumberRegH;      // IDE sector number register (high part for LBA48 mode)
 263         UCHAR    bCylLowRegH;            // IDE low order cylinder value (high part for LBA48 mode)
 264         UCHAR    bCylHighRegH;           // IDE high order cylinder value (high part for LBA48 mode)
 265         UCHAR    bReserved2;             // 0
 266 } IDEREGS_EX, *PIDEREGS_EX, *LPIDEREGS_EX;
 267
 268 typedef struct _UNIATA_REG_IO {
 269     USHORT RegIDX;
 270     UCHAR  RegSz:3;   // 0=1, 1=2, 2=4, 3=1+1 (for lba48) 4=2+2 (for lba48)
 271     UCHAR  InOut:1;   // 0=in, 1=out
 272     UCHAR  Reserved:4;
 273     UCHAR  Reserved1;
 274     union {
 275         ULONG  Data;
 276         ULONG  d32;
 277         USHORT d16[2];
 278         USHORT d8[2];
 279     };
 280 } UNIATA_REG_IO, *PUNIATA_REG_IO;
 281
 282 typedef struct _UNIATA_REG_IO_HDR {
 283     ULONG          ItemCount;
 284     UNIATA_REG_IO  r[1];
 285 } UNIATA_REG_IO_HDR, *PUNIATA_REG_IO_HDR;
 286
 287 #pragma pack(pop)
 288
 289 #pragma pack(push, 1)
 290
 291 typedef struct _UNIATA_CTL {
 292     SRB_IO_CONTROL hdr;
 293     SCSI_ADDRESS   addr;
 294     ULONG Reserved;
 295     union {
 296         UCHAR                   RawData[1];
 297         ADDREMOVEDEV            FindDelDev;
 298         SETTRANSFERMODE         SetMode;
 299         GETTRANSFERMODE         GetMode;
 300         ADAPTERINFO             AdapterInfo;
 301 //        IDENTIFY_DATA2        LunIdent;
 302 //        ATA_PASS_THROUGH_DIRECT AtaDirect;
 303         GETDRVVERSION           Version;
 304         UNIATA_REG_IO_HDR       RegIo;
 305     };
 306 } UNIATA_CTL, *PUNIATA_CTL;
 307
 308 typedef struct _SCSI_PASS_THROUGH_WITH_BUFFERS {
 309     SCSI_PASS_THROUGH spt;
 310     ULONG             Filler;      // realign buffers to double word boundary
 311     UCHAR             ucSenseBuf[32];
 312     UCHAR             ucDataBuf[512]; // recommended minimum
 313 } SCSI_PASS_THROUGH_WITH_BUFFERS, *PSCSI_PASS_THROUGH_WITH_BUFFERS;
 314
 315 typedef struct _SCSI_PASS_THROUGH_DIRECT_WITH_BUFFER {
 316     SCSI_PASS_THROUGH_DIRECT sptd;
 317     ULONG             Filler;      // realign buffer to double word boundary
 318     UCHAR             ucSenseBuf[32];
 319 } SCSI_PASS_THROUGH_DIRECT_WITH_BUFFER, *PSCSI_PASS_THROUGH_DIRECT_WITH_BUFFER;
 320
 321 #endif //UNIATA_CORE
 322
 323 #ifdef __cplusplus
 324 };
 325 #endif //__cplusplus
 326
 327 #pragma pack(pop)
 328
 329 #endif //__UNIATA_IO_CONTROL_CODES__H__