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[reactos.git] / reactos / drivers / usb / cromwell / host / ohci-q.c
1 /*
2 * OHCI HCD (Host Controller Driver) for USB.
3 *
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
6 *
7 * This file is licenced under the GPL.
8 */
9
10 static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv)
11 {
12 int last = urb_priv->length - 1;
13
14 if (last >= 0) {
15 int i;
16 struct td *td;
17
18 for (i = 0; i <= last; i++) {
19 td = urb_priv->td [i];
20 if (td)
21 td_free (hc, td);
22 }
23 }
24
25 kfree (urb_priv);
26 }
27
28 /*-------------------------------------------------------------------------*/
29
30 /*
31 * URB goes back to driver, and isn't reissued.
32 * It's completely gone from HC data structures.
33 * PRECONDITION: no locks held, irqs blocked (Giveback can call into HCD.)
34 */
35 static void
36 finish_urb (struct ohci_hcd *ohci, struct urb *urb, struct pt_regs *regs)
37 {
38 // ASSERT (urb->hcpriv != 0);
39
40 urb_free_priv (ohci, urb->hcpriv);
41 urb->hcpriv = NULL;
42
43 spin_lock (&urb->lock);
44 if (likely (urb->status == -EINPROGRESS))
45 urb->status = 0;
46 spin_unlock (&urb->lock);
47
48 // what lock protects these?
49 switch (usb_pipetype (urb->pipe)) {
50 case PIPE_ISOCHRONOUS:
51 hcd_to_bus (&ohci->hcd)->bandwidth_isoc_reqs--;
52 break;
53 case PIPE_INTERRUPT:
54 hcd_to_bus (&ohci->hcd)->bandwidth_int_reqs--;
55 break;
56 }
57
58 #ifdef OHCI_VERBOSE_DEBUG
59 urb_print (urb, "RET", usb_pipeout (urb->pipe));
60 #endif
61 usb_hcd_giveback_urb (&ohci->hcd, urb, regs);
62 }
63
64
65 /*-------------------------------------------------------------------------*
66 * ED handling functions
67 *-------------------------------------------------------------------------*/
68
69 /* search for the right schedule branch to use for a periodic ed.
70 * does some load balancing; returns the branch, or negative errno.
71 */
72 static int balance (struct ohci_hcd *ohci, int interval, int load)
73 {
74 int i, branch = -ENOSPC;
75
76 /* iso periods can be huge; iso tds specify frame numbers */
77 if (interval > NUM_INTS)
78 interval = NUM_INTS;
79
80 /* search for the least loaded schedule branch of that period
81 * that has enough bandwidth left unreserved.
82 */
83 for (i = 0; i < interval ; i++) {
84 if (branch < 0 || ohci->load [branch] > ohci->load [i]) {
85 #if 1 /* CONFIG_USB_BANDWIDTH */
86 int j;
87
88 /* usb 1.1 says 90% of one frame */
89 for (j = i; j < NUM_INTS; j += interval) {
90 if ((ohci->load [j] + load) > 900)
91 break;
92 }
93 if (j < NUM_INTS)
94 continue;
95 #endif
96 branch = i;
97 }
98 }
99 return branch;
100 }
101
102 /*-------------------------------------------------------------------------*/
103
104 /* both iso and interrupt requests have periods; this routine puts them
105 * into the schedule tree in the apppropriate place. most iso devices use
106 * 1msec periods, but that's not required.
107 */
108 static void periodic_link (struct ohci_hcd *ohci, struct ed *ed)
109 {
110 unsigned i;
111
112 ohci_vdbg (ohci, "link %sed %p branch %d [%dus.], interval %d\n",
113 (ed->hwINFO & ED_ISO) ? "iso " : "",
114 ed, ed->branch, ed->load, ed->interval);
115
116 for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
117 struct ed **prev = &ohci->periodic [i];
118 u32 *prev_p = &ohci->hcca->int_table [i];
119 struct ed *here = *prev;
120
121 /* sorting each branch by period (slow before fast)
122 * lets us share the faster parts of the tree.
123 * (plus maybe: put interrupt eds before iso)
124 */
125 while (here && ed != here) {
126 if (ed->interval > here->interval)
127 break;
128 prev = &here->ed_next;
129 prev_p = &here->hwNextED;
130 here = *prev;
131 }
132 if (ed != here) {
133 ed->ed_next = here;
134 if (here)
135 ed->hwNextED = *prev_p;
136 wmb ();
137 *prev = ed;
138 *prev_p = cpu_to_le32p (&ed->dma);
139 }
140 ohci->load [i] += ed->load;
141 }
142 hcd_to_bus (&ohci->hcd)->bandwidth_allocated += ed->load / ed->interval;
143 }
144
145 /* link an ed into one of the HC chains */
146
147 static int ed_schedule (struct ohci_hcd *ohci, struct ed *ed)
148 {
149 int branch;
150
151 ed->state = ED_OPER;
152 ed->ed_prev = 0;
153 ed->ed_next = 0;
154 ed->hwNextED = 0;
155 wmb ();
156
157 /* we care about rm_list when setting CLE/BLE in case the HC was at
158 * work on some TD when CLE/BLE was turned off, and isn't quiesced
159 * yet. finish_unlinks() restarts as needed, some upcoming INTR_SF.
160 *
161 * control and bulk EDs are doubly linked (ed_next, ed_prev), but
162 * periodic ones are singly linked (ed_next). that's because the
163 * periodic schedule encodes a tree like figure 3-5 in the ohci
164 * spec: each qh can have several "previous" nodes, and the tree
165 * doesn't have unused/idle descriptors.
166 */
167 switch (ed->type) {
168 case PIPE_CONTROL:
169 if (ohci->ed_controltail == NULL) {
170 writel (ed->dma, &ohci->regs->ed_controlhead);
171 } else {
172 ohci->ed_controltail->ed_next = ed;
173 ohci->ed_controltail->hwNextED = cpu_to_le32 (ed->dma);
174 }
175 ed->ed_prev = ohci->ed_controltail;
176 if (!ohci->ed_controltail && !ohci->ed_rm_list) {
177 ohci->hc_control |= OHCI_CTRL_CLE;
178 writel (0, &ohci->regs->ed_controlcurrent);
179 writel (ohci->hc_control, &ohci->regs->control);
180 }
181 ohci->ed_controltail = ed;
182 break;
183
184 case PIPE_BULK:
185 if (ohci->ed_bulktail == NULL) {
186 writel (ed->dma, &ohci->regs->ed_bulkhead);
187 } else {
188 ohci->ed_bulktail->ed_next = ed;
189 ohci->ed_bulktail->hwNextED = cpu_to_le32 (ed->dma);
190 }
191 ed->ed_prev = ohci->ed_bulktail;
192 if (!ohci->ed_bulktail && !ohci->ed_rm_list) {
193 ohci->hc_control |= OHCI_CTRL_BLE;
194 writel (0, &ohci->regs->ed_bulkcurrent);
195 writel (ohci->hc_control, &ohci->regs->control);
196 }
197 ohci->ed_bulktail = ed;
198 break;
199
200 // case PIPE_INTERRUPT:
201 // case PIPE_ISOCHRONOUS:
202 default:
203 branch = balance (ohci, ed->interval, ed->load);
204 if (branch < 0) {
205 ohci_dbg (ohci,
206 "ERR %d, interval %d msecs, load %d\n",
207 branch, ed->interval, ed->load);
208 // FIXME if there are TDs queued, fail them!
209 return branch;
210 }
211 ed->branch = branch;
212 periodic_link (ohci, ed);
213 }
214
215 /* the HC may not see the schedule updates yet, but if it does
216 * then they'll be properly ordered.
217 */
218 return 0;
219 }
220
221 /*-------------------------------------------------------------------------*/
222
223 /* scan the periodic table to find and unlink this ED */
224 static void periodic_unlink (struct ohci_hcd *ohci, struct ed *ed)
225 {
226 int i;
227
228 for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
229 struct ed *temp;
230 struct ed **prev = &ohci->periodic [i];
231 u32 *prev_p = &ohci->hcca->int_table [i];
232
233 while (*prev && (temp = *prev) != ed) {
234 prev_p = &temp->hwNextED;
235 prev = &temp->ed_next;
236 }
237 if (*prev) {
238 *prev_p = ed->hwNextED;
239 *prev = ed->ed_next;
240 }
241 ohci->load [i] -= ed->load;
242 }
243 hcd_to_bus (&ohci->hcd)->bandwidth_allocated -= ed->load / ed->interval;
244
245 ohci_vdbg (ohci, "unlink %sed %p branch %d [%dus.], interval %d\n",
246 (ed->hwINFO & ED_ISO) ? "iso " : "",
247 ed, ed->branch, ed->load, ed->interval);
248 }
249
250 /* unlink an ed from one of the HC chains.
251 * just the link to the ed is unlinked.
252 * the link from the ed still points to another operational ed or 0
253 * so the HC can eventually finish the processing of the unlinked ed
254 */
255 static void ed_deschedule (struct ohci_hcd *ohci, struct ed *ed)
256 {
257 ed->hwINFO |= ED_SKIP;
258
259 switch (ed->type) {
260 case PIPE_CONTROL:
261 if (ed->ed_prev == NULL) {
262 if (!ed->hwNextED) {
263 ohci->hc_control &= ~OHCI_CTRL_CLE;
264 writel (ohci->hc_control, &ohci->regs->control);
265 writel (0, &ohci->regs->ed_controlcurrent);
266 // post those pci writes
267 (void) readl (&ohci->regs->control);
268 }
269 writel (le32_to_cpup (&ed->hwNextED),
270 &ohci->regs->ed_controlhead);
271 } else {
272 ed->ed_prev->ed_next = ed->ed_next;
273 ed->ed_prev->hwNextED = ed->hwNextED;
274 }
275 if (ohci->ed_controltail == ed) {
276 ohci->ed_controltail = ed->ed_prev;
277 if (ohci->ed_controltail)
278 ohci->ed_controltail->ed_next = 0;
279 } else if (ed->ed_next) {
280 ed->ed_next->ed_prev = ed->ed_prev;
281 }
282 break;
283
284 case PIPE_BULK:
285 if (ed->ed_prev == NULL) {
286 if (!ed->hwNextED) {
287 ohci->hc_control &= ~OHCI_CTRL_BLE;
288 writel (ohci->hc_control, &ohci->regs->control);
289 writel (0, &ohci->regs->ed_bulkcurrent);
290 // post those pci writes
291 (void) readl (&ohci->regs->control);
292 }
293 writel (le32_to_cpup (&ed->hwNextED),
294 &ohci->regs->ed_bulkhead);
295 } else {
296 ed->ed_prev->ed_next = ed->ed_next;
297 ed->ed_prev->hwNextED = ed->hwNextED;
298 }
299 if (ohci->ed_bulktail == ed) {
300 ohci->ed_bulktail = ed->ed_prev;
301 if (ohci->ed_bulktail)
302 ohci->ed_bulktail->ed_next = 0;
303 } else if (ed->ed_next) {
304 ed->ed_next->ed_prev = ed->ed_prev;
305 }
306 break;
307
308 // case PIPE_INTERRUPT:
309 // case PIPE_ISOCHRONOUS:
310 default:
311 periodic_unlink (ohci, ed);
312 break;
313 }
314
315 /* NOTE: Except for a couple of exceptionally clean unlink cases
316 * (like unlinking the only c/b ED, with no TDs) HCs may still be
317 * caching this operational ED (or its address). Safe unlinking
318 * involves not marking it ED_IDLE till INTR_SF; we always do that
319 * if td_list isn't empty. Otherwise the race is small; but ...
320 */
321 if (ed->state == ED_OPER) {
322 ed->state = ED_IDLE;
323 ed->hwINFO &= ~(ED_SKIP | ED_DEQUEUE);
324 ed->hwHeadP &= ~ED_H;
325 wmb ();
326 }
327 }
328
329
330 /*-------------------------------------------------------------------------*/
331
332 /* get and maybe (re)init an endpoint. init _should_ be done only as part
333 * of usb_set_configuration() or usb_set_interface() ... but the USB stack
334 * isn't very stateful, so we re-init whenever the HC isn't looking.
335 */
336 static struct ed *ed_get (
337 struct ohci_hcd *ohci,
338 struct usb_device *udev,
339 unsigned int pipe,
340 int interval
341 ) {
342 int is_out = !usb_pipein (pipe);
343 int type = usb_pipetype (pipe);
344 struct hcd_dev *dev = (struct hcd_dev *) udev->hcpriv;
345 struct ed *ed;
346 unsigned ep;
347 unsigned long flags;
348
349 ep = usb_pipeendpoint (pipe) << 1;
350 if (type != PIPE_CONTROL && is_out)
351 ep |= 1;
352
353 spin_lock_irqsave (&ohci->lock, flags);
354
355 if (!(ed = dev->ep [ep])) {
356 struct td *td;
357
358 ed = ed_alloc (ohci, SLAB_ATOMIC);
359 if (!ed) {
360 /* out of memory */
361 goto done;
362 }
363 dev->ep [ep] = ed;
364
365 /* dummy td; end of td list for ed */
366 td = td_alloc (ohci, SLAB_ATOMIC);
367 if (!td) {
368 /* out of memory */
369 ed_free (ohci, ed);
370 ed = 0;
371 goto done;
372 }
373 ed->dummy = td;
374 ed->hwTailP = cpu_to_le32 (td->td_dma);
375 ed->hwHeadP = ed->hwTailP; /* ED_C, ED_H zeroed */
376 ed->state = ED_IDLE;
377 ed->type = type;
378 }
379
380 /* NOTE: only ep0 currently needs this "re"init logic, during
381 * enumeration (after set_address, or if ep0 maxpacket >8).
382 */
383 if (ed->state == ED_IDLE) {
384 u32 info;
385
386 info = usb_pipedevice (pipe);
387 info |= (ep >> 1) << 7;
388 info |= usb_maxpacket (udev, pipe, is_out) << 16;
389 info = cpu_to_le32 (info);
390 if (udev->speed == USB_SPEED_LOW)
391 info |= ED_LOWSPEED;
392 /* only control transfers store pids in tds */
393 if (type != PIPE_CONTROL) {
394 info |= is_out ? ED_OUT : ED_IN;
395 if (type != PIPE_BULK) {
396 /* periodic transfers... */
397 if (type == PIPE_ISOCHRONOUS)
398 info |= ED_ISO;
399 else if (interval > 32) /* iso can be bigger */
400 interval = 32;
401 ed->interval = interval;
402 ed->load = usb_calc_bus_time (
403 udev->speed, !is_out,
404 type == PIPE_ISOCHRONOUS,
405 usb_maxpacket (udev, pipe, is_out))
406 / 1000;
407 }
408 }
409 ed->hwINFO = info;
410 }
411
412 done:
413 spin_unlock_irqrestore (&ohci->lock, flags);
414 return ed;
415 }
416
417 /*-------------------------------------------------------------------------*/
418
419 /* request unlinking of an endpoint from an operational HC.
420 * put the ep on the rm_list
421 * real work is done at the next start frame (SF) hardware interrupt
422 */
423 static void start_urb_unlink (struct ohci_hcd *ohci, struct ed *ed)
424 {
425 ed->hwINFO |= ED_DEQUEUE;
426 ed->state = ED_UNLINK;
427 ed_deschedule (ohci, ed);
428
429 /* SF interrupt might get delayed; record the frame counter value that
430 * indicates when the HC isn't looking at it, so concurrent unlinks
431 * behave. frame_no wraps every 2^16 msec, and changes right before
432 * SF is triggered.
433 */
434 ed->tick = le16_to_cpu (ohci->hcca->frame_no) + 1;
435
436 /* rm_list is just singly linked, for simplicity */
437 ed->ed_next = ohci->ed_rm_list;
438 ed->ed_prev = 0;
439 ohci->ed_rm_list = ed;
440
441 /* enable SOF interrupt */
442 if (!ohci->sleeping) {
443 writel (OHCI_INTR_SF, &ohci->regs->intrstatus);
444 writel (OHCI_INTR_SF, &ohci->regs->intrenable);
445 // flush those pci writes
446 (void) readl (&ohci->regs->control);
447 }
448 }
449
450 /*-------------------------------------------------------------------------*
451 * TD handling functions
452 *-------------------------------------------------------------------------*/
453
454 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
455
456 static void
457 td_fill (struct ohci_hcd *ohci, u32 info,
458 dma_addr_t data, int len,
459 struct urb *urb, int index)
460 {
461 struct td *td, *td_pt;
462 struct urb_priv *urb_priv = urb->hcpriv;
463 int is_iso = info & TD_ISO;
464 int hash;
465
466 // ASSERT (index < urb_priv->length);
467
468 /* aim for only one interrupt per urb. mostly applies to control
469 * and iso; other urbs rarely need more than one TD per urb.
470 * this way, only final tds (or ones with an error) cause IRQs.
471 * at least immediately; use DI=6 in case any control request is
472 * tempted to die part way through.
473 *
474 * NOTE: could delay interrupts even for the last TD, and get fewer
475 * interrupts ... increasing per-urb latency by sharing interrupts.
476 * Drivers that queue bulk urbs may request that behavior.
477 */
478 if (index != (urb_priv->length - 1)
479 || (urb->transfer_flags & URB_NO_INTERRUPT))
480 info |= TD_DI_SET (6);
481
482 /* use this td as the next dummy */
483 td_pt = urb_priv->td [index];
484
485 /* fill the old dummy TD */
486 td = urb_priv->td [index] = urb_priv->ed->dummy;
487 urb_priv->ed->dummy = td_pt;
488
489 td->ed = urb_priv->ed;
490 td->next_dl_td = NULL;
491 td->index = index;
492 td->urb = urb;
493 td->data_dma = data;
494 if (!len)
495 data = 0;
496
497 td->hwINFO = cpu_to_le32 (info);
498 if (is_iso) {
499 td->hwCBP = cpu_to_le32 (data & 0xFFFFF000);
500 td->hwPSW [0] = cpu_to_le16 ((data & 0x0FFF) | 0xE000);
501 td->ed->last_iso = info & 0xffff;
502 } else {
503 td->hwCBP = cpu_to_le32 (data);
504 }
505 if (data)
506 td->hwBE = cpu_to_le32 (data + len - 1);
507 else
508 td->hwBE = 0;
509 td->hwNextTD = cpu_to_le32 (td_pt->td_dma);
510
511 /* append to queue */
512 list_add_tail (&td->td_list, &td->ed->td_list);
513
514 /* hash it for later reverse mapping */
515 hash = TD_HASH_FUNC (td->td_dma);
516 td->td_hash = ohci->td_hash [hash];
517 ohci->td_hash [hash] = td;
518
519 /* HC might read the TD (or cachelines) right away ... */
520 wmb ();
521 td->ed->hwTailP = td->hwNextTD;
522 }
523
524 /*-------------------------------------------------------------------------*/
525
526 /* Prepare all TDs of a transfer, and queue them onto the ED.
527 * Caller guarantees HC is active.
528 * Usually the ED is already on the schedule, so TDs might be
529 * processed as soon as they're queued.
530 */
531 static void td_submit_urb (
532 struct ohci_hcd *ohci,
533 struct urb *urb
534 ) {
535 struct urb_priv *urb_priv = urb->hcpriv;
536 dma_addr_t data;
537 int data_len = urb->transfer_buffer_length;
538 int cnt = 0;
539 u32 info = 0;
540 int is_out = usb_pipeout (urb->pipe);
541
542 /* OHCI handles the bulk/interrupt data toggles itself. We just
543 * use the device toggle bits for resetting, and rely on the fact
544 * that resetting toggle is meaningless if the endpoint is active.
545 */
546 if (!usb_gettoggle (urb->dev, usb_pipeendpoint (urb->pipe), is_out)) {
547 usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe),
548 is_out, 1);
549 urb_priv->ed->hwHeadP &= ~ED_C;
550 }
551
552 urb_priv->td_cnt = 0;
553
554 if (data_len)
555 data = urb->transfer_dma;
556 else
557 data = 0;
558
559 /* NOTE: TD_CC is set so we can tell which TDs the HC processed by
560 * using TD_CC_GET, as well as by seeing them on the done list.
561 * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
562 */
563 switch (urb_priv->ed->type) {
564
565 /* Bulk and interrupt are identical except for where in the schedule
566 * their EDs live.
567 */
568 case PIPE_INTERRUPT:
569 /* ... and periodic urbs have extra accounting */
570 hcd_to_bus (&ohci->hcd)->bandwidth_int_reqs++;
571 /* FALLTHROUGH */
572 case PIPE_BULK:
573 info = is_out
574 ? TD_T_TOGGLE | TD_CC | TD_DP_OUT
575 : TD_T_TOGGLE | TD_CC | TD_DP_IN;
576 /* TDs _could_ transfer up to 8K each */
577 while (data_len > 4096) {
578 td_fill (ohci, info, data, 4096, urb, cnt);
579 data += 4096;
580 data_len -= 4096;
581 cnt++;
582 }
583 /* maybe avoid ED halt on final TD short read */
584 if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
585 info |= TD_R;
586 td_fill (ohci, info, data, data_len, urb, cnt);
587 cnt++;
588 if ((urb->transfer_flags & URB_ZERO_PACKET)
589 && cnt < urb_priv->length) {
590 td_fill (ohci, info, 0, 0, urb, cnt);
591 cnt++;
592 }
593 /* maybe kickstart bulk list */
594 if (urb_priv->ed->type == PIPE_BULK) {
595 wmb ();
596 writel (OHCI_BLF, &ohci->regs->cmdstatus);
597 }
598 break;
599
600 /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
601 * any DATA phase works normally, and the STATUS ack is special.
602 */
603 case PIPE_CONTROL:
604 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
605 td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++);
606 if (data_len > 0) {
607 info = TD_CC | TD_R | TD_T_DATA1;
608 info |= is_out ? TD_DP_OUT : TD_DP_IN;
609 /* NOTE: mishandles transfers >8K, some >4K */
610 td_fill (ohci, info, data, data_len, urb, cnt++);
611 }
612 info = is_out
613 ? TD_CC | TD_DP_IN | TD_T_DATA1
614 : TD_CC | TD_DP_OUT | TD_T_DATA1;
615 td_fill (ohci, info, data, 0, urb, cnt++);
616 /* maybe kickstart control list */
617 wmb ();
618 writel (OHCI_CLF, &ohci->regs->cmdstatus);
619 break;
620
621 /* ISO has no retransmit, so no toggle; and it uses special TDs.
622 * Each TD could handle multiple consecutive frames (interval 1);
623 * we could often reduce the number of TDs here.
624 */
625 case PIPE_ISOCHRONOUS:
626 for (cnt = 0; cnt < urb->number_of_packets; cnt++) {
627 int frame = urb->start_frame;
628
629 // FIXME scheduling should handle frame counter
630 // roll-around ... exotic case (and OHCI has
631 // a 2^16 iso range, vs other HCs max of 2^10)
632 frame += cnt * urb->interval;
633 frame &= 0xffff;
634 td_fill (ohci, TD_CC | TD_ISO | frame,
635 data + urb->iso_frame_desc [cnt].offset,
636 urb->iso_frame_desc [cnt].length, urb, cnt);
637 }
638 hcd_to_bus (&ohci->hcd)->bandwidth_isoc_reqs++;
639 break;
640 }
641 // ASSERT (urb_priv->length == cnt);
642 }
643
644 /*-------------------------------------------------------------------------*
645 * Done List handling functions
646 *-------------------------------------------------------------------------*/
647
648 /* calculate transfer length/status and update the urb
649 * PRECONDITION: irqsafe (only for urb->status locking)
650 */
651 static void td_done (struct ohci_hcd *ohci, struct urb *urb, struct td *td)
652 {
653 u32 tdINFO = le32_to_cpup (&td->hwINFO);
654 int cc = 0;
655
656 list_del (&td->td_list);
657
658 /* ISO ... drivers see per-TD length/status */
659 if (tdINFO & TD_ISO) {
660 u16 tdPSW = le16_to_cpu (td->hwPSW [0]);
661 int dlen = 0;
662
663 /* NOTE: assumes FC in tdINFO == 0 (and MAXPSW == 1) */
664
665 cc = (tdPSW >> 12) & 0xF;
666 if (tdINFO & TD_CC) /* hc didn't touch? */
667 return;
668
669 if (usb_pipeout (urb->pipe))
670 dlen = urb->iso_frame_desc [td->index].length;
671 else {
672 /* short reads are always OK for ISO */
673 if (cc == TD_DATAUNDERRUN)
674 cc = TD_CC_NOERROR;
675 dlen = tdPSW & 0x3ff;
676 }
677 urb->actual_length += dlen;
678 urb->iso_frame_desc [td->index].actual_length = dlen;
679 urb->iso_frame_desc [td->index].status = cc_to_error [cc];
680
681 if (cc != TD_CC_NOERROR)
682 ohci_vdbg (ohci,
683 "urb %p iso td %p (%d) len %d cc %d\n",
684 urb, td, 1 + td->index, dlen, cc);
685
686 /* BULK, INT, CONTROL ... drivers see aggregate length/status,
687 * except that "setup" bytes aren't counted and "short" transfers
688 * might not be reported as errors.
689 */
690 } else {
691 int type = usb_pipetype (urb->pipe);
692 u32 tdBE = le32_to_cpup (&td->hwBE);
693
694 cc = TD_CC_GET (tdINFO);
695
696 /* control endpoints only have soft stalls */
697 if (type != PIPE_CONTROL && cc == TD_CC_STALL)
698 usb_endpoint_halt (urb->dev,
699 usb_pipeendpoint (urb->pipe),
700 usb_pipeout (urb->pipe));
701
702 /* update packet status if needed (short is normally ok) */
703 if (cc == TD_DATAUNDERRUN
704 && !(urb->transfer_flags & URB_SHORT_NOT_OK))
705 cc = TD_CC_NOERROR;
706 if (cc != TD_CC_NOERROR && cc < 0x0E) {
707 spin_lock (&urb->lock);
708 if (urb->status == -EINPROGRESS)
709 urb->status = cc_to_error [cc];
710 spin_unlock (&urb->lock);
711 }
712
713 /* count all non-empty packets except control SETUP packet */
714 if ((type != PIPE_CONTROL || td->index != 0) && tdBE != 0) {
715 if (td->hwCBP == 0)
716 urb->actual_length += tdBE - td->data_dma + 1;
717 else
718 urb->actual_length +=
719 le32_to_cpup (&td->hwCBP)
720 - td->data_dma;
721 }
722
723 if (cc != TD_CC_NOERROR && cc < 0x0E)
724 ohci_vdbg (ohci,
725 "urb %p td %p (%d) cc %d, len=%d/%d\n",
726 urb, td, 1 + td->index, cc,
727 urb->actual_length,
728 urb->transfer_buffer_length);
729 }
730 }
731
732 /*-------------------------------------------------------------------------*/
733
734 static inline struct td *
735 ed_halted (struct ohci_hcd *ohci, struct td *td, int cc, struct td *rev)
736 {
737 struct urb *urb = td->urb;
738 struct ed *ed = td->ed;
739 struct list_head *tmp = td->td_list.next;
740 u32 toggle = ed->hwHeadP & ED_C;
741
742 /* clear ed halt; this is the td that caused it, but keep it inactive
743 * until its urb->complete() has a chance to clean up.
744 */
745 ed->hwINFO |= ED_SKIP;
746 wmb ();
747 ed->hwHeadP &= ~ED_H;
748
749 /* put any later tds from this urb onto the donelist, after 'td',
750 * order won't matter here: no errors, and nothing was transferred.
751 * also patch the ed so it looks as if those tds completed normally.
752 */
753 while (tmp != &ed->td_list) {
754 struct td *next;
755 u32 info;
756
757 next = list_entry (tmp, struct td, td_list);
758 tmp = next->td_list.next;
759
760 if (next->urb != urb)
761 break;
762
763 /* NOTE: if multi-td control DATA segments get supported,
764 * this urb had one of them, this td wasn't the last td
765 * in that segment (TD_R clear), this ed halted because
766 * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
767 * then we need to leave the control STATUS packet queued
768 * and clear ED_SKIP.
769 */
770 info = next->hwINFO;
771 info |= cpu_to_le32 (TD_DONE);
772 info &= ~cpu_to_le32 (TD_CC);
773 next->hwINFO = info;
774
775 next->next_dl_td = rev;
776 rev = next;
777
778 if (ed->hwTailP == cpu_to_le32 (next->td_dma))
779 ed->hwTailP = next->hwNextTD;
780 ed->hwHeadP = next->hwNextTD | toggle;
781 }
782
783 /* help for troubleshooting: report anything that
784 * looks odd ... that doesn't include protocol stalls
785 * (or maybe some other things)
786 */
787 if (cc != TD_CC_STALL || !usb_pipecontrol (urb->pipe))
788 ohci_dbg (ohci,
789 "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
790 urb, urb->dev->devpath,
791 usb_pipeendpoint (urb->pipe),
792 usb_pipein (urb->pipe) ? "in" : "out",
793 le32_to_cpu (td->hwINFO),
794 cc, cc_to_error [cc]);
795
796 return rev;
797 }
798
799 /* replies to the request have to be on a FIFO basis so
800 * we unreverse the hc-reversed done-list
801 */
802 static struct td *dl_reverse_done_list (struct ohci_hcd *ohci)
803 {
804 u32 td_dma;
805 struct td *td_rev = NULL;
806 struct td *td = NULL;
807 unsigned long flags;
808
809 spin_lock_irqsave (&ohci->lock, flags);
810 td_dma = le32_to_cpup (&ohci->hcca->done_head);
811 ohci->hcca->done_head = 0;
812
813 /* get TD from hc's singly linked list, and
814 * prepend to ours. ed->td_list changes later.
815 */
816 while (td_dma) {
817 int cc;
818
819 td = dma_to_td (ohci, td_dma);
820 if (!td) {
821 ohci_err (ohci, "bad entry %8x\n", td_dma);
822 break;
823 }
824
825 td->hwINFO |= cpu_to_le32 (TD_DONE);
826 cc = TD_CC_GET (le32_to_cpup (&td->hwINFO));
827
828 /* Non-iso endpoints can halt on error; un-halt,
829 * and dequeue any other TDs from this urb.
830 * No other TD could have caused the halt.
831 */
832 if (cc != TD_CC_NOERROR && (td->ed->hwHeadP & ED_H))
833 td_rev = ed_halted (ohci, td, cc, td_rev);
834
835 td->next_dl_td = td_rev;
836 td_rev = td;
837 td_dma = le32_to_cpup (&td->hwNextTD);
838 }
839 spin_unlock_irqrestore (&ohci->lock, flags);
840 return td_rev;
841 }
842
843 /*-------------------------------------------------------------------------*/
844
845 /* wrap-aware logic stolen from <linux/jiffies.h> */
846 #define tick_before(t1,t2) ((((s16)(t1))-((s16)(t2))) < 0)
847
848 /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
849 static void
850 finish_unlinks (struct ohci_hcd *ohci, u16 tick, struct pt_regs *regs)
851 {
852 struct ed *ed, **last;
853
854 rescan_all:
855 for (last = &ohci->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
856 struct list_head *entry, *tmp;
857 int completed, modified;
858 u32 *prev;
859
860 /* only take off EDs that the HC isn't using, accounting for
861 * frame counter wraps.
862 */
863 if (tick_before (tick, ed->tick) && !ohci->disabled) {
864 last = &ed->ed_next;
865 continue;
866 }
867
868 /* reentrancy: if we drop the schedule lock, someone might
869 * have modified this list. normally it's just prepending
870 * entries (which we'd ignore), but paranoia won't hurt.
871 */
872 *last = ed->ed_next;
873 ed->ed_next = 0;
874 modified = 0;
875
876 /* unlink urbs as requested, but rescan the list after
877 * we call a completion since it might have unlinked
878 * another (earlier) urb
879 */
880 rescan_this:
881 completed = 0;
882 prev = &ed->hwHeadP;
883 list_for_each_safe (entry, tmp, &ed->td_list) {
884 struct td *td;
885 struct urb *urb;
886 urb_priv_t *urb_priv;
887 u32 savebits;
888
889 td = list_entry (entry, struct td, td_list);
890 urb = td->urb;
891 urb_priv = td->urb->hcpriv;
892
893 if (urb_priv->state != URB_DEL) {
894 prev = &td->hwNextTD;
895 continue;
896 }
897
898 /* patch pointers hc uses ... tail, if we're removing
899 * an otherwise active td, and whatever td pointer
900 * points to this td
901 */
902 if (ed->hwTailP == cpu_to_le32 (td->td_dma))
903 ed->hwTailP = td->hwNextTD;
904 savebits = *prev & ~cpu_to_le32 (TD_MASK);
905 *prev = td->hwNextTD | savebits;
906
907 /* HC may have partly processed this TD */
908 td_done (ohci, urb, td);
909 urb_priv->td_cnt++;
910
911 /* if URB is done, clean up */
912 if (urb_priv->td_cnt == urb_priv->length) {
913 modified = completed = 1;
914 spin_unlock (&ohci->lock);
915 finish_urb (ohci, urb, regs);
916 spin_lock (&ohci->lock);
917 }
918 }
919 if (completed && !list_empty (&ed->td_list))
920 goto rescan_this;
921
922 /* ED's now officially unlinked, hc doesn't see */
923 ed->state = ED_IDLE;
924 ed->hwINFO &= ~(ED_SKIP | ED_DEQUEUE);
925 ed->hwHeadP &= ~ED_H;
926 ed->hwNextED = 0;
927
928 /* but if there's work queued, reschedule */
929 if (!list_empty (&ed->td_list)) {
930 if (!ohci->disabled && !ohci->sleeping)
931 ed_schedule (ohci, ed);
932 }
933
934 if (modified)
935 goto rescan_all;
936 }
937
938 /* maybe reenable control and bulk lists */
939 if (!ohci->disabled && !ohci->ed_rm_list) {
940 u32 command = 0, control = 0;
941
942 if (ohci->ed_controltail) {
943 command |= OHCI_CLF;
944 if (!(ohci->hc_control & OHCI_CTRL_CLE)) {
945 control |= OHCI_CTRL_CLE;
946 writel (0, &ohci->regs->ed_controlcurrent);
947 }
948 }
949 if (ohci->ed_bulktail) {
950 command |= OHCI_BLF;
951 if (!(ohci->hc_control & OHCI_CTRL_BLE)) {
952 control |= OHCI_CTRL_BLE;
953 writel (0, &ohci->regs->ed_bulkcurrent);
954 }
955 }
956
957 /* CLE/BLE to enable, CLF/BLF to (maybe) kickstart */
958 if (control) {
959 ohci->hc_control |= control;
960 writel (ohci->hc_control, &ohci->regs->control);
961 }
962 if (command)
963 writel (command, &ohci->regs->cmdstatus);
964 }
965 }
966
967
968
969 /*-------------------------------------------------------------------------*/
970
971 /*
972 * Process normal completions (error or success) and clean the schedules.
973 *
974 * This is the main path for handing urbs back to drivers. The only other
975 * path is finish_unlinks(), which unlinks URBs using ed_rm_list, instead of
976 * scanning the (re-reversed) donelist as this does.
977 */
978 static void
979 dl_done_list (struct ohci_hcd *ohci, struct td *td, struct pt_regs *regs)
980 {
981 unsigned long flags;
982
983 spin_lock_irqsave (&ohci->lock, flags);
984 while (td) {
985 struct td *td_next = td->next_dl_td;
986 struct urb *urb = td->urb;
987 urb_priv_t *urb_priv = urb->hcpriv;
988 struct ed *ed = td->ed;
989
990 /* update URB's length and status from TD */
991 td_done (ohci, urb, td);
992 urb_priv->td_cnt++;
993
994 /* If all this urb's TDs are done, call complete() */
995 if (urb_priv->td_cnt == urb_priv->length) {
996 spin_unlock (&ohci->lock);
997 finish_urb (ohci, urb, regs);
998 spin_lock (&ohci->lock);
999 }
1000
1001 /* clean schedule: unlink EDs that are no longer busy */
1002 if (list_empty (&ed->td_list))
1003 ed_deschedule (ohci, ed);
1004 /* ... reenabling halted EDs only after fault cleanup */
1005 else if (!(ed->hwINFO & ED_DEQUEUE)) {
1006 td = list_entry (ed->td_list.next, struct td, td_list);
1007 if (!(td->hwINFO & TD_DONE))
1008 ed->hwINFO &= ~ED_SKIP;
1009 }
1010
1011 td = td_next;
1012 }
1013 spin_unlock_irqrestore (&ohci->lock, flags);
1014 }
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