reactos/drivers/usb/cromwell/uhci/uhci-hcd.h

   1 #ifndef __LINUX_UHCI_HCD_H
   2 #define __LINUX_UHCI_HCD_H
   3
   4 #if 0
   5 #include <linux/list.h>
   6 #include <linux/usb.h>
   7 #endif
   8
   9 #define usb_packetid(pipe)      (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT)
  10 #define PIPE_DEVEP_MASK         0x0007ff00
  11
  12 /*
  13  * Universal Host Controller Interface data structures and defines
  14  */
  15
  16 /* Command register */
  17 #define USBCMD          0
  18 #define   USBCMD_RS             0x0001  /* Run/Stop */
  19 #define   USBCMD_HCRESET        0x0002  /* Host reset */
  20 #define   USBCMD_GRESET         0x0004  /* Global reset */
  21 #define   USBCMD_EGSM           0x0008  /* Global Suspend Mode */
  22 #define   USBCMD_FGR            0x0010  /* Force Global Resume */
  23 #define   USBCMD_SWDBG          0x0020  /* SW Debug mode */
  24 #define   USBCMD_CF             0x0040  /* Config Flag (sw only) */
  25 #define   USBCMD_MAXP           0x0080  /* Max Packet (0 = 32, 1 = 64) */
  26
  27 /* Status register */
  28 #define USBSTS          2
  29 #define   USBSTS_USBINT         0x0001  /* Interrupt due to IOC */
  30 #define   USBSTS_ERROR          0x0002  /* Interrupt due to error */
  31 #define   USBSTS_RD             0x0004  /* Resume Detect */
  32 #define   USBSTS_HSE            0x0008  /* Host System Error - basically PCI problems */
  33 #define   USBSTS_HCPE           0x0010  /* Host Controller Process Error - the scripts were buggy */
  34 #define   USBSTS_HCH            0x0020  /* HC Halted */
  35
  36 /* Interrupt enable register */
  37 #define USBINTR         4
  38 #define   USBINTR_TIMEOUT       0x0001  /* Timeout/CRC error enable */
  39 #define   USBINTR_RESUME        0x0002  /* Resume interrupt enable */
  40 #define   USBINTR_IOC           0x0004  /* Interrupt On Complete enable */
  41 #define   USBINTR_SP            0x0008  /* Short packet interrupt enable */
  42
  43 #define USBFRNUM        6
  44 #define USBFLBASEADD    8
  45 #define USBSOF          12
  46
  47 /* USB port status and control registers */
  48 #define USBPORTSC1      16
  49 #define USBPORTSC2      18
  50 #define   USBPORTSC_CCS         0x0001  /* Current Connect Status ("device present") */
  51 #define   USBPORTSC_CSC         0x0002  /* Connect Status Change */
  52 #define   USBPORTSC_PE          0x0004  /* Port Enable */
  53 #define   USBPORTSC_PEC         0x0008  /* Port Enable Change */
  54 #define   USBPORTSC_LS          0x0030  /* Line Status */
  55 #define   USBPORTSC_RD          0x0040  /* Resume Detect */
  56 #define   USBPORTSC_LSDA        0x0100  /* Low Speed Device Attached */
  57 #define   USBPORTSC_PR          0x0200  /* Port Reset */
  58 #define   USBPORTSC_OC          0x0400  /* Over Current condition */
  59 #define   USBPORTSC_SUSP        0x1000  /* Suspend */
  60
  61 /* Legacy support register */
  62 #define USBLEGSUP               0xc0
  63 #define   USBLEGSUP_DEFAULT     0x2000  /* only PIRQ enable set */
  64
  65 #define UHCI_NULL_DATA_SIZE     0x7FF   /* for UHCI controller TD */
  66
  67 #define UHCI_PTR_BITS           cpu_to_le32(0x000F)
  68 #define UHCI_PTR_TERM           cpu_to_le32(0x0001)
  69 #define UHCI_PTR_QH             cpu_to_le32(0x0002)
  70 #define UHCI_PTR_DEPTH          cpu_to_le32(0x0004)
  71 #define UHCI_PTR_BREADTH        cpu_to_le32(0x0000)
  72
  73 #define UHCI_NUMFRAMES          1024    /* in the frame list [array] */
  74 #define UHCI_MAX_SOF_NUMBER     2047    /* in an SOF packet */
  75 #define CAN_SCHEDULE_FRAMES     1000    /* how far future frames can be scheduled */
  76
  77 struct uhci_frame_list {
  78         __u32 frame[UHCI_NUMFRAMES];
  79
  80         void *frame_cpu[UHCI_NUMFRAMES];
  81
  82         dma_addr_t dma_handle;
  83 };
  84
  85 struct urb_priv;
  86
  87 /*
  88  * One role of a QH is to hold a queue of TDs for some endpoint.  Each QH is
  89  * used with one URB, and qh->element (updated by the HC) is either:
  90  *   - the next unprocessed TD for the URB, or
  91  *   - UHCI_PTR_TERM (when there's no more traffic for this endpoint), or
  92  *   - the QH for the next URB queued to the same endpoint.
  93  *
  94  * The other role of a QH is to serve as a "skeleton" framelist entry, so we
  95  * can easily splice a QH for some endpoint into the schedule at the right
  96  * place.  Then qh->element is UHCI_PTR_TERM.
  97  *
  98  * In the frame list, qh->link maintains a list of QHs seen by the HC:
  99  *     skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ...
 100  */
 101 struct uhci_qh {
 102         /* Hardware fields */
 103         __u32 link;                     /* Next queue */
 104         __u32 element;                  /* Queue element pointer */
 105
 106         /* Software fields */
 107         dma_addr_t dma_handle;
 108
 109         struct usb_device *dev;
 110         struct urb_priv *urbp;
 111
 112         struct list_head list;          /* P: uhci->frame_list_lock */
 113         struct list_head remove_list;   /* P: uhci->remove_list_lock */
 114 } __attribute__((aligned(16)));
 115
 116 /*
 117  * for TD <status>:
 118  */
 119 #define td_status(td)           le32_to_cpu((td)->status)
 120 #define TD_CTRL_SPD             (1 << 29)       /* Short Packet Detect */
 121 #define TD_CTRL_C_ERR_MASK      (3 << 27)       /* Error Counter bits */
 122 #define TD_CTRL_C_ERR_SHIFT     27
 123 #define TD_CTRL_LS              (1 << 26)       /* Low Speed Device */
 124 #define TD_CTRL_IOS             (1 << 25)       /* Isochronous Select */
 125 #define TD_CTRL_IOC             (1 << 24)       /* Interrupt on Complete */
 126 #define TD_CTRL_ACTIVE          (1 << 23)       /* TD Active */
 127 #define TD_CTRL_STALLED         (1 << 22)       /* TD Stalled */
 128 #define TD_CTRL_DBUFERR         (1 << 21)       /* Data Buffer Error */
 129 #define TD_CTRL_BABBLE          (1 << 20)       /* Babble Detected */
 130 #define TD_CTRL_NAK             (1 << 19)       /* NAK Received */
 131 #define TD_CTRL_CRCTIMEO        (1 << 18)       /* CRC/Time Out Error */
 132 #define TD_CTRL_BITSTUFF        (1 << 17)       /* Bit Stuff Error */
 133 #define TD_CTRL_ACTLEN_MASK     0x7FF   /* actual length, encoded as n - 1 */
 134
 135 #define TD_CTRL_ANY_ERROR       (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
 136                                  TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF)
 137
 138 #define uhci_maxerr(err)                ((err) << TD_CTRL_C_ERR_SHIFT)
 139 #define uhci_status_bits(ctrl_sts)      ((ctrl_sts) & 0xFE0000)
 140 #define uhci_actual_length(ctrl_sts)    (((ctrl_sts) + 1) & TD_CTRL_ACTLEN_MASK) /* 1-based */
 141
 142 /*
 143  * for TD <info>: (a.k.a. Token)
 144  */
 145 #define td_token(td)            le32_to_cpu((td)->token)
 146 #define TD_TOKEN_DEVADDR_SHIFT  8
 147 #define TD_TOKEN_TOGGLE_SHIFT   19
 148 #define TD_TOKEN_TOGGLE         (1 << 19)
 149 #define TD_TOKEN_EXPLEN_SHIFT   21
 150 #define TD_TOKEN_EXPLEN_MASK    0x7FF           /* expected length, encoded as n - 1 */
 151 #define TD_TOKEN_PID_MASK       0xFF
 152
 153 #define uhci_explen(len)        ((len) << TD_TOKEN_EXPLEN_SHIFT)
 154
 155 #define uhci_expected_length(token) ((((token) >> 21) + 1) & TD_TOKEN_EXPLEN_MASK)
 156 #define uhci_toggle(token)      (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1)
 157 #define uhci_endpoint(token)    (((token) >> 15) & 0xf)
 158 #define uhci_devaddr(token)     (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f)
 159 #define uhci_devep(token)       (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff)
 160 #define uhci_packetid(token)    ((token) & TD_TOKEN_PID_MASK)
 161 #define uhci_packetout(token)   (uhci_packetid(token) != USB_PID_IN)
 162 #define uhci_packetin(token)    (uhci_packetid(token) == USB_PID_IN)
 163
 164 /*
 165  * The documentation says "4 words for hardware, 4 words for software".
 166  *
 167  * That's silly, the hardware doesn't care. The hardware only cares that
 168  * the hardware words are 16-byte aligned, and we can have any amount of
 169  * sw space after the TD entry as far as I can tell.
 170  *
 171  * But let's just go with the documentation, at least for 32-bit machines.
 172  * On 64-bit machines we probably want to take advantage of the fact that
 173  * hw doesn't really care about the size of the sw-only area.
 174  *
 175  * Alas, not anymore, we have more than 4 words for software, woops.
 176  * Everything still works tho, surprise! -jerdfelt
 177  *
 178  * td->link points to either another TD (not necessarily for the same urb or
 179  * even the same endpoint), or nothing (PTR_TERM), or a QH (for queued urbs)
 180  */
 181 struct uhci_td {
 182         /* Hardware fields */
 183         __u32 link;
 184         __u32 status;
 185         __u32 token;
 186         __u32 buffer;
 187
 188         /* Software fields */
 189         dma_addr_t dma_handle;
 190
 191         struct usb_device *dev;
 192         struct urb *urb;
 193
 194         struct list_head list;          /* P: urb->lock */
 195
 196         int frame;                      /* for iso: what frame? */
 197         struct list_head fl_list;       /* P: uhci->frame_list_lock */
 198 } __attribute__((aligned(16)));
 199
 200 /*
 201  * The UHCI driver places Interrupt, Control and Bulk into QH's both
 202  * to group together TD's for one transfer, and also to faciliate queuing
 203  * of URB's. To make it easy to insert entries into the schedule, we have
 204  * a skeleton of QH's for each predefined Interrupt latency, low speed
 205  * control, high speed control and terminating QH (see explanation for
 206  * the terminating QH below).
 207  *
 208  * When we want to add a new QH, we add it to the end of the list for the
 209  * skeleton QH.
 210  *
 211  * For instance, the queue can look like this:
 212  *
 213  * skel int128 QH
 214  * dev 1 interrupt QH
 215  * dev 5 interrupt QH
 216  * skel int64 QH
 217  * skel int32 QH
 218  * ...
 219  * skel int1 QH
 220  * skel low speed control QH
 221  * dev 5 control QH
 222  * skel high speed control QH
 223  * skel bulk QH
 224  * dev 1 bulk QH
 225  * dev 2 bulk QH
 226  * skel terminating QH
 227  *
 228  * The terminating QH is used for 2 reasons:
 229  * - To place a terminating TD which is used to workaround a PIIX bug
 230  *   (see Intel errata for explanation)
 231  * - To loop back to the high speed control queue for full speed bandwidth
 232  *   reclamation
 233  *
 234  * Isochronous transfers are stored before the start of the skeleton
 235  * schedule and don't use QH's. While the UHCI spec doesn't forbid the
 236  * use of QH's for Isochronous, it doesn't use them either. Since we don't
 237  * need to use them either, we follow the spec diagrams in hope that it'll
 238  * be more compatible with future UHCI implementations.
 239  */
 240
 241 #define UHCI_NUM_SKELQH         12
 242 #define skel_int128_qh          skelqh[0]
 243 #define skel_int64_qh           skelqh[1]
 244 #define skel_int32_qh           skelqh[2]
 245 #define skel_int16_qh           skelqh[3]
 246 #define skel_int8_qh            skelqh[4]
 247 #define skel_int4_qh            skelqh[5]
 248 #define skel_int2_qh            skelqh[6]
 249 #define skel_int1_qh            skelqh[7]
 250 #define skel_ls_control_qh      skelqh[8]
 251 #define skel_hs_control_qh      skelqh[9]
 252 #define skel_bulk_qh            skelqh[10]
 253 #define skel_term_qh            skelqh[11]
 254
 255 /*
 256  * Search tree for determining where <interval> fits in the skelqh[]
 257  * skeleton.
 258  *
 259  * An interrupt request should be placed into the slowest skelqh[]
 260  * which meets the interval/period/frequency requirement.
 261  * An interrupt request is allowed to be faster than <interval> but not slower.
 262  *
 263  * For a given <interval>, this function returns the appropriate/matching
 264  * skelqh[] index value.
 265  */
 266 static inline int __interval_to_skel(int interval)
 267 {
 268         if (interval < 16) {
 269                 if (interval < 4) {
 270                         if (interval < 2)
 271                                 return 7;       /* int1 for 0-1 ms */
 272                         return 6;               /* int2 for 2-3 ms */
 273                 }
 274                 if (interval < 8)
 275                         return 5;               /* int4 for 4-7 ms */
 276                 return 4;                       /* int8 for 8-15 ms */
 277         }
 278         if (interval < 64) {
 279                 if (interval < 32)
 280                         return 3;               /* int16 for 16-31 ms */
 281                 return 2;                       /* int32 for 32-63 ms */
 282         }
 283         if (interval < 128)
 284                 return 1;                       /* int64 for 64-127 ms */
 285         return 0;                               /* int128 for 128-255 ms (Max.) */
 286 }
 287
 288 /*
 289  * Device states for the host controller.
 290  *
 291  * To prevent "bouncing" in the presence of electrical noise,
 292  * we insist on a 1-second "grace" period, before switching to
 293  * the RUNNING or SUSPENDED states, during which the state is
 294  * not allowed to change.
 295  *
 296  * The resume process is divided into substates in order to avoid
 297  * potentially length delays during the timer handler.
 298  *
 299  * States in which the host controller is halted must have values <= 0.
 300  */
 301 enum uhci_state {
 302         UHCI_RESET,
 303         UHCI_RUNNING_GRACE,             /* Before RUNNING */
 304         UHCI_RUNNING,                   /* The normal state */
 305         UHCI_SUSPENDING_GRACE,          /* Before SUSPENDED */
 306         UHCI_SUSPENDED = -10,           /* When no devices are attached */
 307         UHCI_RESUMING_1,
 308         UHCI_RESUMING_2
 309 };
 310
 311 #define hcd_to_uhci(hcd_ptr) container_of(hcd_ptr, struct uhci_hcd, hcd)
 312
 313 /*
 314  * This describes the full uhci information.
 315  *
 316  * Note how the "proper" USB information is just
 317  * a subset of what the full implementation needs.
 318  */
 319 struct uhci_hcd {
 320         struct usb_hcd hcd;
 321
 322 #ifdef CONFIG_PROC_FS
 323         /* procfs */
 324         struct proc_dir_entry *proc_entry;
 325 #endif
 326
 327         /* Grabbed from PCI */
 328         unsigned long io_addr;
 329
 330         struct pci_pool *qh_pool;
 331         struct pci_pool *td_pool;
 332
 333         struct usb_bus *bus;
 334
 335         struct uhci_td *term_td;        /* Terminating TD, see UHCI bug */
 336         struct uhci_qh *skelqh[UHCI_NUM_SKELQH];        /* Skeleton QH's */
 337
 338         spinlock_t frame_list_lock;
 339         struct uhci_frame_list *fl;             /* P: uhci->frame_list_lock */
 340         int fsbr;                               /* Full speed bandwidth reclamation */
 341         unsigned long fsbrtimeout;              /* FSBR delay */
 342
 343         enum uhci_state state;                  /* FIXME: needs a spinlock */
 344         unsigned long state_end;                /* Time of next transition */
 345         int resume_detect;                      /* Need a Global Resume */
 346
 347         /* Main list of URB's currently controlled by this HC */
 348         spinlock_t urb_list_lock;
 349         struct list_head urb_list;              /* P: uhci->urb_list_lock */
 350
 351         /* List of QH's that are done, but waiting to be unlinked (race) */
 352         spinlock_t qh_remove_list_lock;
 353         struct list_head qh_remove_list;        /* P: uhci->qh_remove_list_lock */
 354
 355         /* List of asynchronously unlinked URB's */
 356         spinlock_t urb_remove_list_lock;
 357         struct list_head urb_remove_list;       /* P: uhci->urb_remove_list_lock */
 358
 359         /* List of URB's awaiting completion callback */
 360         spinlock_t complete_list_lock;
 361         struct list_head complete_list;         /* P: uhci->complete_list_lock */
 362
 363         int rh_numports;
 364
 365         struct timer_list stall_timer;
 366 };
 367
 368 struct urb_priv {
 369         struct list_head urb_list;
 370
 371         struct urb *urb;
 372         struct usb_device *dev;
 373
 374         struct uhci_qh *qh;             /* QH for this URB */
 375         struct list_head td_list;       /* P: urb->lock */
 376
 377         int fsbr : 1;                   /* URB turned on FSBR */
 378         int fsbr_timeout : 1;           /* URB timed out on FSBR */
 379         int queued : 1;                 /* QH was queued (not linked in) */
 380         int short_control_packet : 1;   /* If we get a short packet during */
 381                                         /*  a control transfer, retrigger */
 382                                         /*  the status phase */
 383
 384         int status;                     /* Final status */
 385
 386         unsigned long inserttime;       /* In jiffies */
 387         unsigned long fsbrtime;         /* In jiffies */
 388
 389         struct list_head queue_list;    /* P: uhci->frame_list_lock */
 390         struct list_head complete_list; /* P: uhci->complete_list_lock */
 391 };
 392
 393 /*
 394  * Locking in uhci.c
 395  *
 396  * spinlocks are used extensively to protect the many lists and data
 397  * structures we have. It's not that pretty, but it's necessary. We
 398  * need to be done with all of the locks (except complete_list_lock) when
 399  * we call urb->complete. I've tried to make it simple enough so I don't
 400  * have to spend hours racking my brain trying to figure out if the
 401  * locking is safe.
 402  *
 403  * Here's the safe locking order to prevent deadlocks:
 404  *
 405  * #1 uhci->urb_list_lock
 406  * #2 urb->lock
 407  * #3 uhci->urb_remove_list_lock, uhci->frame_list_lock,
 408  *   uhci->qh_remove_list_lock
 409  * #4 uhci->complete_list_lock
 410  *
 411  * If you're going to grab 2 or more locks at once, ALWAYS grab the lock
 412  * at the lowest level FIRST and NEVER grab locks at the same level at the
 413  * same time.
 414  *
 415  * So, if you need uhci->urb_list_lock, grab it before you grab urb->lock
 416  */
 417
 418 #endif
 419