reactos/drivers/usb/miniport/usbohci/ohci.h

   1 /*
   2  * OHCI HCD (Host Controller Driver) for USB.
   3  *
   4  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   5  * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
   6  *
   7  * This file is licenced under the GPL.
   8  */
   9
  10 /*
  11  * OHCI Endpoint Descriptor (ED) ... holds TD queue
  12  * See OHCI spec, section 4.2
  13  *
  14  * This is a "Queue Head" for those transfers, which is why
  15  * both EHCI and UHCI call similar structures a "QH".
  16  */
  17 struct ed {
  18         /* first fields are hardware-specified, le32 */
  19         __u32                   hwINFO;         /* endpoint config bitmap */
  20         /* info bits defined by hcd */
  21 #define ED_DEQUEUE      __constant_cpu_to_le32(1 << 27)
  22         /* info bits defined by the hardware */
  23 #define ED_ISO          __constant_cpu_to_le32(1 << 15)
  24 #define ED_SKIP         __constant_cpu_to_le32(1 << 14)
  25 #define ED_LOWSPEED     __constant_cpu_to_le32(1 << 13)
  26 #define ED_OUT          __constant_cpu_to_le32(0x01 << 11)
  27 #define ED_IN           __constant_cpu_to_le32(0x02 << 11)
  28         __u32                   hwTailP;        /* tail of TD list */
  29         __u32                   hwHeadP;        /* head of TD list (hc r/w) */
  30 #define ED_C            __constant_cpu_to_le32(0x02)    /* toggle carry */
  31 #define ED_H            __constant_cpu_to_le32(0x01)    /* halted */
  32         __u32                   hwNextED;       /* next ED in list */
  33
  34         /* rest are purely for the driver's use */
  35         dma_addr_t              dma;            /* addr of ED */
  36         struct td               *dummy;         /* next TD to activate */
  37
  38         /* host's view of schedule */
  39         struct ed               *ed_next;       /* on schedule or rm_list */
  40         struct ed               *ed_prev;       /* for non-interrupt EDs */
  41         struct list_head        td_list;        /* "shadow list" of our TDs */
  42
  43         /* create --> IDLE --> OPER --> ... --> IDLE --> destroy
  44          * usually:  OPER --> UNLINK --> (IDLE | OPER) --> ...
  45          * some special cases :  OPER --> IDLE ...
  46          */
  47         u8                      state;          /* ED_{IDLE,UNLINK,OPER} */
  48 #define ED_IDLE         0x00            /* NOT linked to HC */
  49 #define ED_UNLINK       0x01            /* being unlinked from hc */
  50 #define ED_OPER         0x02            /* IS linked to hc */
  51
  52         u8                      type;           /* PIPE_{BULK,...} */
  53
  54         /* periodic scheduling params (for intr and iso) */
  55         u8                      branch;
  56         u16                     interval;
  57         u16                     load;
  58         u16                     last_iso;       /* iso only */
  59
  60         /* HC may see EDs on rm_list until next frame (frame_no == tick) */
  61         u16                     tick;
  62 } __attribute__ ((aligned(16)));
  63
  64 #define ED_MASK ((u32)~0x0f)            /* strip hw status in low addr bits */
  65
  66
  67 /*
  68  * OHCI Transfer Descriptor (TD) ... one per transfer segment
  69  * See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt)
  70  * and 4.3.2 (iso)
  71  */
  72 struct td {
  73         /* first fields are hardware-specified, le32 */
  74         __u32           hwINFO;         /* transfer info bitmask */
  75
  76         /* hwINFO bits for both general and iso tds: */
  77 #define TD_CC       0xf0000000                  /* condition code */
  78 #define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
  79 //#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
  80 #define TD_DI       0x00E00000                  /* frames before interrupt */
  81 #define TD_DI_SET(X) (((X) & 0x07)<< 21)
  82         /* these two bits are available for definition/use by HCDs in both
  83          * general and iso tds ... others are available for only one type
  84          */
  85 #define TD_DONE     0x00020000                  /* retired to donelist */
  86 #define TD_ISO      0x00010000                  /* copy of ED_ISO */
  87
  88         /* hwINFO bits for general tds: */
  89 #define TD_EC       0x0C000000                  /* error count */
  90 #define TD_T        0x03000000                  /* data toggle state */
  91 #define TD_T_DATA0  0x02000000                          /* DATA0 */
  92 #define TD_T_DATA1  0x03000000                          /* DATA1 */
  93 #define TD_T_TOGGLE 0x00000000                          /* uses ED_C */
  94 #define TD_DP       0x00180000                  /* direction/pid */
  95 #define TD_DP_SETUP 0x00000000                  /* SETUP pid */
  96 #define TD_DP_IN    0x00100000                          /* IN pid */
  97 #define TD_DP_OUT   0x00080000                          /* OUT pid */
  98                                                         /* 0x00180000 rsvd */
  99 #define TD_R        0x00040000                  /* round: short packets OK? */
 100
 101         /* (no hwINFO #defines yet for iso tds) */
 102
 103         __u32           hwCBP;          /* Current Buffer Pointer (or 0) */
 104         __u32           hwNextTD;       /* Next TD Pointer */
 105         __u32           hwBE;           /* Memory Buffer End Pointer */
 106
 107         /* PSW is only for ISO */
 108 #define MAXPSW 1                /* hardware allows 8 */
 109         __u16           hwPSW [MAXPSW];
 110
 111         /* rest are purely for the driver's use */
 112         __u8            index;
 113         struct ed       *ed;
 114         struct td       *td_hash;       /* dma-->td hashtable */
 115         struct td       *next_dl_td;
 116         struct urb      *urb;
 117
 118         dma_addr_t      td_dma;         /* addr of this TD */
 119         dma_addr_t      data_dma;       /* addr of data it points to */
 120
 121         struct list_head td_list;       /* "shadow list", TDs on same ED */
 122 } __attribute__ ((aligned(32)));        /* c/b/i need 16; only iso needs 32 */
 123
 124 #define TD_MASK ((u32)~0x1f)            /* strip hw status in low addr bits */
 125
 126 /*
 127  * Hardware transfer status codes -- CC from td->hwINFO or td->hwPSW
 128  */
 129 #define TD_CC_NOERROR      0x00
 130 #define TD_CC_CRC          0x01
 131 #define TD_CC_BITSTUFFING  0x02
 132 #define TD_CC_DATATOGGLEM  0x03
 133 #define TD_CC_STALL        0x04
 134 #define TD_DEVNOTRESP      0x05
 135 #define TD_PIDCHECKFAIL    0x06
 136 #define TD_UNEXPECTEDPID   0x07
 137 #define TD_DATAOVERRUN     0x08
 138 #define TD_DATAUNDERRUN    0x09
 139     /* 0x0A, 0x0B reserved for hardware */
 140 #define TD_BUFFEROVERRUN   0x0C
 141 #define TD_BUFFERUNDERRUN  0x0D
 142     /* 0x0E, 0x0F reserved for HCD */
 143 #define TD_NOTACCESSED     0x0F
 144
 145
 146 /* map OHCI TD status codes (CC) to errno values */
 147 static const int cc_to_error [16] = {
 148         /* No  Error  */               0,
 149         /* CRC Error  */               -EILSEQ,
 150         /* Bit Stuff  */               -EPROTO,
 151         /* Data Togg  */               -EILSEQ,
 152         /* Stall      */               -EPIPE,
 153         /* DevNotResp */               -ETIMEDOUT,
 154         /* PIDCheck   */               -EPROTO,
 155         /* UnExpPID   */               -EPROTO,
 156         /* DataOver   */               -EOVERFLOW,
 157         /* DataUnder  */               -EREMOTEIO,
 158         /* (for hw)   */               -EIO,
 159         /* (for hw)   */               -EIO,
 160         /* BufferOver */               -ECOMM,
 161         /* BuffUnder  */               -ENOSR,
 162         /* (for HCD)  */               -EALREADY,
 163         /* (for HCD)  */               -EALREADY
 164 };
 165
 166
 167 /*
 168  * The HCCA (Host Controller Communications Area) is a 256 byte
 169  * structure defined section 4.4.1 of the OHCI spec. The HC is
 170  * told the base address of it.  It must be 256-byte aligned.
 171  */
 172 struct ohci_hcca {
 173 #define NUM_INTS 32
 174         __u32   int_table [NUM_INTS];   /* periodic schedule */
 175         __u16   frame_no;               /* current frame number */
 176         __u16   pad1;                   /* set to 0 on each frame_no change */
 177         __u32   done_head;              /* info returned for an interrupt */
 178         u8      reserved_for_hc [116];
 179         u8      what [4];               /* spec only identifies 252 bytes :) */
 180 } __attribute__ ((aligned(256)));
 181
 182
 183 /*
 184  * This is the structure of the OHCI controller's memory mapped I/O region.
 185  * You must use readl() and writel() (in <asm/io.h>) to access these fields!!
 186  * Layout is in section 7 (and appendix B) of the spec.
 187  */
 188 struct ohci_regs {
 189         /* control and status registers (section 7.1) */
 190         __u32   revision;
 191         __u32   control;
 192         __u32   cmdstatus;
 193         __u32   intrstatus;
 194         __u32   intrenable;
 195         __u32   intrdisable;
 196
 197         /* memory pointers (section 7.2) */
 198         __u32   hcca;
 199         __u32   ed_periodcurrent;
 200         __u32   ed_controlhead;
 201         __u32   ed_controlcurrent;
 202         __u32   ed_bulkhead;
 203         __u32   ed_bulkcurrent;
 204         __u32   donehead;
 205
 206         /* frame counters (section 7.3) */
 207         __u32   fminterval;
 208         __u32   fmremaining;
 209         __u32   fmnumber;
 210         __u32   periodicstart;
 211         __u32   lsthresh;
 212
 213         /* Root hub ports (section 7.4) */
 214         struct  ohci_roothub_regs {
 215                 __u32   a;
 216                 __u32   b;
 217                 __u32   status;
 218 #define MAX_ROOT_PORTS  15      /* maximum OHCI root hub ports (RH_A_NDP) */
 219                 __u32   portstatus [MAX_ROOT_PORTS];
 220         } roothub;
 221
 222         /* and optional "legacy support" registers (appendix B) at 0x0100 */
 223
 224 } __attribute__ ((aligned(32)));
 225
 226
 227 /* OHCI CONTROL AND STATUS REGISTER MASKS */
 228
 229 /*
 230  * HcControl (control) register masks
 231  */
 232 #define OHCI_CTRL_CBSR  (3 << 0)        /* control/bulk service ratio */
 233 #define OHCI_CTRL_PLE   (1 << 2)        /* periodic list enable */
 234 #define OHCI_CTRL_IE    (1 << 3)        /* isochronous enable */
 235 #define OHCI_CTRL_CLE   (1 << 4)        /* control list enable */
 236 #define OHCI_CTRL_BLE   (1 << 5)        /* bulk list enable */
 237 #define OHCI_CTRL_HCFS  (3 << 6)        /* host controller functional state */
 238 #define OHCI_CTRL_IR    (1 << 8)        /* interrupt routing */
 239 #define OHCI_CTRL_RWC   (1 << 9)        /* remote wakeup connected */
 240 #define OHCI_CTRL_RWE   (1 << 10)       /* remote wakeup enable */
 241
 242 /* pre-shifted values for HCFS */
 243 #define OHCI_USB_RESET  (0 << 6)
 244 #define OHCI_USB_RESUME (1 << 6)
 245 #define OHCI_USB_OPER   (2 << 6)
 246 #define OHCI_USB_SUSPEND (3 << 6)
 247
 248 // HCFS itself
 249 static char *hcfs2string (int state)
 250 {
 251         switch (state) {
 252                 case OHCI_USB_RESET: return "reset";
 253                 case OHCI_USB_RESUME: return "resume";
 254                 case OHCI_USB_OPER: return "operational";
 255                 case OHCI_USB_SUSPEND: return "suspend";
 256         }
 257         return "?";
 258 }
 259
 260 /*
 261  * HcCommandStatus (cmdstatus) register masks
 262  */
 263 #define OHCI_HCR        (1 << 0)        /* host controller reset */
 264 #define OHCI_CLF        (1 << 1)        /* control list filled */
 265 #define OHCI_BLF        (1 << 2)        /* bulk list filled */
 266 #define OHCI_OCR        (1 << 3)        /* ownership change request */
 267 #define OHCI_SOC        (3 << 16)       /* scheduling overrun count */
 268
 269 /*
 270  * masks used with interrupt registers:
 271  * HcInterruptStatus (intrstatus)
 272  * HcInterruptEnable (intrenable)
 273  * HcInterruptDisable (intrdisable)
 274  */
 275 #define OHCI_INTR_SO    (1 << 0)        /* scheduling overrun */
 276 #define OHCI_INTR_WDH   (1 << 1)        /* writeback of done_head */
 277 #define OHCI_INTR_SF    (1 << 2)        /* start frame */
 278 #define OHCI_INTR_RD    (1 << 3)        /* resume detect */
 279 #define OHCI_INTR_UE    (1 << 4)        /* unrecoverable error */
 280 #define OHCI_INTR_FNO   (1 << 5)        /* frame number overflow */
 281 #define OHCI_INTR_RHSC  (1 << 6)        /* root hub status change */
 282 #define OHCI_INTR_OC    (1 << 30)       /* ownership change */
 283 #define OHCI_INTR_MIE   (1 << 31)       /* master interrupt enable */
 284
 285
 286 /* OHCI ROOT HUB REGISTER MASKS */
 287
 288 /* roothub.portstatus [i] bits */
 289 #define RH_PS_CCS            0x00000001         /* current connect status */
 290 #define RH_PS_PES            0x00000002         /* port enable status*/
 291 #define RH_PS_PSS            0x00000004         /* port suspend status */
 292 #define RH_PS_POCI           0x00000008         /* port over current indicator */
 293 #define RH_PS_PRS            0x00000010         /* port reset status */
 294 #define RH_PS_PPS            0x00000100         /* port power status */
 295 #define RH_PS_LSDA           0x00000200         /* low speed device attached */
 296 #define RH_PS_CSC            0x00010000         /* connect status change */
 297 #define RH_PS_PESC           0x00020000         /* port enable status change */
 298 #define RH_PS_PSSC           0x00040000         /* port suspend status change */
 299 #define RH_PS_OCIC           0x00080000         /* over current indicator change */
 300 #define RH_PS_PRSC           0x00100000         /* port reset status change */
 301
 302 /* roothub.status bits */
 303 #define RH_HS_LPS            0x00000001         /* local power status */
 304 #define RH_HS_OCI            0x00000002         /* over current indicator */
 305 #define RH_HS_DRWE           0x00008000         /* device remote wakeup enable */
 306 #define RH_HS_LPSC           0x00010000         /* local power status change */
 307 #define RH_HS_OCIC           0x00020000         /* over current indicator change */
 308 #define RH_HS_CRWE           0x80000000         /* clear remote wakeup enable */
 309
 310 /* roothub.b masks */
 311 #define RH_B_DR         0x0000ffff              /* device removable flags */
 312 #define RH_B_PPCM       0xffff0000              /* port power control mask */
 313
 314 /* roothub.a masks */
 315 #define RH_A_NDP        (0xff << 0)             /* number of downstream ports */
 316 #define RH_A_PSM        (1 << 8)                /* power switching mode */
 317 #define RH_A_NPS        (1 << 9)                /* no power switching */
 318 #define RH_A_DT         (1 << 10)               /* device type (mbz) */
 319 #define RH_A_OCPM       (1 << 11)               /* over current protection mode */
 320 #define RH_A_NOCP       (1 << 12)               /* no over current protection */
 321 #define RH_A_POTPGT     (0xff << 24)            /* power on to power good time */
 322
 323
 324 /* hcd-private per-urb state */
 325 typedef struct urb_priv {
 326         struct ed               *ed;
 327         __u16                   length;         // # tds in this request
 328         __u16                   td_cnt;         // tds already serviced
 329         int                     state;
 330         struct td               *td [0];        // all TDs in this request
 331
 332 } urb_priv_t;
 333
 334 #define URB_DEL 1
 335
 336 #define TD_HASH_SIZE    64    /* power'o'two */
 337 // sizeof (struct td) ~= 64 == 2^6 ...
 338 #define TD_HASH_FUNC(td_dma) ((td_dma ^ (td_dma >> 6)) % TD_HASH_SIZE)
 339
 340
 341 /*
 342  * This is the full ohci controller description
 343  *
 344  * Note how the "proper" USB information is just
 345  * a subset of what the full implementation needs. (Linus)
 346  */
 347
 348 struct ohci_hcd {
 349         spinlock_t              lock;
 350
 351         /*
 352          * I/O memory used to communicate with the HC (dma-consistent)
 353          */
 354         struct ohci_regs        *regs;
 355
 356         /*
 357          * main memory used to communicate with the HC (dma-consistent).
 358          * hcd adds to schedule for a live hc any time, but removals finish
 359          * only at the start of the next frame.
 360          */
 361         struct ohci_hcca        *hcca;
 362         dma_addr_t              hcca_dma;
 363
 364         struct ed               *ed_rm_list;            /* to be removed */
 365
 366         struct ed               *ed_bulktail;           /* last in bulk list */
 367         struct ed               *ed_controltail;        /* last in ctrl list */
 368         struct ed               *periodic [NUM_INTS];   /* shadow int_table */
 369
 370         /*
 371          * memory management for queue data structures
 372          */
 373         struct pci_pool         *td_cache;
 374         struct pci_pool         *ed_cache;
 375         struct td               *td_hash [TD_HASH_SIZE];
 376
 377         /*
 378          * driver state
 379          */
 380         int                     disabled;       /* e.g. got a UE, we're hung */
 381         int                     sleeping;
 382         int                     load [NUM_INTS];
 383         u32                     hc_control;     /* copy of hc control reg */
 384
 385         unsigned long           flags;          /* for HC bugs */
 386 #define OHCI_QUIRK_AMD756       0x01                    /* erratum #4 */
 387 #define OHCI_QUIRK_SUPERIO      0x02                    /* natsemi */
 388         // there are also chip quirks/bugs in init logic
 389
 390         /*
 391          * framework state
 392          */
 393         struct usb_hcd          hcd;
 394 };
 395
 396 #define hcd_to_ohci(hcd_ptr) container_of(hcd_ptr, struct ohci_hcd, hcd)
 397
 398 /*-------------------------------------------------------------------------*/
 399
 400 #ifndef DEBUG
 401 #define STUB_DEBUG_FILES
 402 #endif  /* DEBUG */
 403
 404 #define ohci_dbg(ohci, fmt, args...) \
 405         dev_dbg ((ohci)->hcd.controller , fmt , ## args )
 406 #define ohci_err(ohci, fmt, args...) \
 407         dev_err ((ohci)->hcd.controller , fmt , ## args )
 408 #define ohci_info(ohci, fmt, args...) \
 409         dev_info ((ohci)->hcd.controller , fmt , ## args )
 410 #define ohci_warn(ohci, fmt, args...) \
 411         dev_warn ((ohci)->hcd.controller , fmt , ## args )
 412
 413 #ifdef OHCI_VERBOSE_DEBUG
 414 #       define ohci_vdbg ohci_dbg
 415 #else
 416 #       define ohci_vdbg(ohci, fmt, args...) do { } while (0)
 417 #endif
 418