2 * Universal Host Controller Interface driver for USB.
4 * Maintainer: Johannes Erdfelt <johannes@erdfelt.com>
6 * (C) Copyright 1999 Linus Torvalds
7 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
8 * (C) Copyright 1999 Randy Dunlap
9 * (C) Copyright 1999 Georg Acher, acher@in.tum.de
10 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
11 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
12 * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
13 * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
14 * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
15 * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
17 * Intel documents this fairly well, and as far as I know there
18 * are no royalties or anything like that, but even so there are
19 * people who decided that they want to do the same thing in a
20 * completely different way.
22 * WARNING! The USB documentation is downright evil. Most of it
23 * is just crap, written by a committee. You're better off ignoring
24 * most of it, the important stuff is:
25 * - the low-level protocol (fairly simple but lots of small details)
26 * - working around the horridness of the rest
30 #include <linux/config.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/kernel.h>
34 #include <linux/init.h>
35 #include <linux/delay.h>
36 #include <linux/ioport.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/smp_lock.h>
40 #include <linux/errno.h>
41 #include <linux/unistd.h>
42 #include <linux/interrupt.h>
43 #include <linux/spinlock.h>
44 #include <linux/proc_fs.h>
47 //#ifdef CONFIG_USB_DEBUG
54 #include <linux/usb.h>
56 #include <asm/uaccess.h>
59 #include <asm/system.h>
62 #include "uhci_config.h"
63 #include "../usb_wrapper.h"
74 #define DRIVER_VERSION "v2.1"
75 #define DRIVER_AUTHOR "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber"
76 #define DRIVER_DESC "USB Universal Host Controller Interface driver"
79 * debug = 0, no debugging messages
80 * debug = 1, dump failed URB's except for stalls
81 * debug = 2, dump all failed URB's (including stalls)
82 * show all queues in /proc/driver/uhci/[pci_addr]
83 * debug = 3, show all TD's in URB's when dumping
90 MODULE_PARM(debug
, "i");
91 MODULE_PARM_DESC(debug
, "Debug level");
93 #define ERRBUF_LEN (PAGE_SIZE * 8)
96 #include "uhci-debug.c"
98 static kmem_cache_t
*uhci_up_cachep
; /* urb_priv */
100 static int uhci_get_current_frame_number(struct uhci_hcd
*uhci
);
101 static int uhci_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
);
102 static void uhci_unlink_generic(struct uhci_hcd
*uhci
, struct urb
*urb
);
104 static void hc_state_transitions(struct uhci_hcd
*uhci
);
106 /* If a transfer is still active after this much time, turn off FSBR */
107 #define IDLE_TIMEOUT (HZ / 20) /* 50 ms */
108 #define FSBR_DELAY (HZ / 20) /* 50 ms */
110 /* When we timeout an idle transfer for FSBR, we'll switch it over to */
111 /* depth first traversal. We'll do it in groups of this number of TD's */
112 /* to make sure it doesn't hog all of the bandwidth */
113 #define DEPTH_INTERVAL 5
116 * Technically, updating td->status here is a race, but it's not really a
117 * problem. The worst that can happen is that we set the IOC bit again
118 * generating a spurious interrupt. We could fix this by creating another
119 * QH and leaving the IOC bit always set, but then we would have to play
120 * games with the FSBR code to make sure we get the correct order in all
121 * the cases. I don't think it's worth the effort
123 static inline void uhci_set_next_interrupt(struct uhci_hcd
*uhci
)
127 spin_lock_irqsave(&uhci
->frame_list_lock
, flags
);
128 uhci
->term_td
->status
|= cpu_to_le32(TD_CTRL_IOC
);
129 spin_unlock_irqrestore(&uhci
->frame_list_lock
, flags
);
132 static inline void uhci_clear_next_interrupt(struct uhci_hcd
*uhci
)
136 spin_lock_irqsave(&uhci
->frame_list_lock
, flags
);
137 uhci
->term_td
->status
&= ~cpu_to_le32(TD_CTRL_IOC
);
138 spin_unlock_irqrestore(&uhci
->frame_list_lock
, flags
);
141 static inline void uhci_add_complete(struct uhci_hcd
*uhci
, struct urb
*urb
)
143 struct urb_priv
*urbp
= (struct urb_priv
*)urb
->hcpriv
;
146 spin_lock_irqsave(&uhci
->complete_list_lock
, flags
);
147 list_add_tail(&urbp
->complete_list
, &uhci
->complete_list
);
148 spin_unlock_irqrestore(&uhci
->complete_list_lock
, flags
);
151 static struct uhci_td
*uhci_alloc_td(struct uhci_hcd
*uhci
, struct usb_device
*dev
)
153 dma_addr_t dma_handle
;
156 td
= pci_pool_alloc(uhci
->td_pool
, GFP_ATOMIC
, &dma_handle
);
160 td
->dma_handle
= dma_handle
;
162 td
->link
= UHCI_PTR_TERM
;
168 INIT_LIST_HEAD(&td
->list
);
169 INIT_LIST_HEAD(&td
->fl_list
);
176 static inline void uhci_fill_td(struct uhci_td
*td
, __u32 status
,
177 __u32 token
, __u32 buffer
)
179 td
->status
= cpu_to_le32(status
);
180 td
->token
= cpu_to_le32(token
);
181 td
->buffer
= cpu_to_le32(buffer
);
185 * We insert Isochronous URB's directly into the frame list at the beginning
187 static void uhci_insert_td_frame_list(struct uhci_hcd
*uhci
, struct uhci_td
*td
, unsigned framenum
)
191 framenum
%= UHCI_NUMFRAMES
;
193 spin_lock_irqsave(&uhci
->frame_list_lock
, flags
);
195 td
->frame
= framenum
;
197 /* Is there a TD already mapped there? */
198 if (uhci
->fl
->frame_cpu
[framenum
]) {
199 struct uhci_td
*ftd
, *ltd
;
201 ftd
= uhci
->fl
->frame_cpu
[framenum
];
202 ltd
= list_entry(ftd
->fl_list
.prev
, struct uhci_td
, fl_list
);
204 list_add_tail(&td
->fl_list
, &ftd
->fl_list
);
206 td
->link
= ltd
->link
;
208 ltd
->link
= cpu_to_le32(td
->dma_handle
);
210 td
->link
= uhci
->fl
->frame
[framenum
];
212 uhci
->fl
->frame
[framenum
] = cpu_to_le32(td
->dma_handle
);
213 uhci
->fl
->frame_cpu
[framenum
] = td
;
216 spin_unlock_irqrestore(&uhci
->frame_list_lock
, flags
);
219 static void uhci_remove_td(struct uhci_hcd
*uhci
, struct uhci_td
*td
)
223 /* If it's not inserted, don't remove it */
224 spin_lock_irqsave(&uhci
->frame_list_lock
, flags
);
225 if (td
->frame
== -1 && list_empty(&td
->fl_list
))
228 if (td
->frame
!= -1 && uhci
->fl
->frame_cpu
[td
->frame
] == td
) {
229 if (list_empty(&td
->fl_list
)) {
230 uhci
->fl
->frame
[td
->frame
] = td
->link
;
231 uhci
->fl
->frame_cpu
[td
->frame
] = NULL
;
235 ntd
= list_entry(td
->fl_list
.next
, struct uhci_td
, fl_list
);
236 uhci
->fl
->frame
[td
->frame
] = cpu_to_le32(ntd
->dma_handle
);
237 uhci
->fl
->frame_cpu
[td
->frame
] = ntd
;
242 ptd
= list_entry(td
->fl_list
.prev
, struct uhci_td
, fl_list
);
243 ptd
->link
= td
->link
;
247 td
->link
= UHCI_PTR_TERM
;
249 list_del_init(&td
->fl_list
);
253 spin_unlock_irqrestore(&uhci
->frame_list_lock
, flags
);
257 * Inserts a td into qh list at the top.
259 static void uhci_insert_tds_in_qh(struct uhci_qh
*qh
, struct urb
*urb
, u32 breadth
)
261 struct list_head
*tmp
, *head
;
262 struct urb_priv
*urbp
= (struct urb_priv
*)urb
->hcpriv
;
263 struct uhci_td
*td
, *ptd
;
265 if (list_empty(&urbp
->td_list
))
268 head
= &urbp
->td_list
;
271 /* Ordering isn't important here yet since the QH hasn't been */
272 /* inserted into the schedule yet */
273 td
= list_entry(tmp
, struct uhci_td
, list
);
275 /* Add the first TD to the QH element pointer */
276 qh
->element
= cpu_to_le32(td
->dma_handle
) | breadth
;
280 /* Then link the rest of the TD's */
282 while (tmp
!= head
) {
283 td
= list_entry(tmp
, struct uhci_td
, list
);
287 ptd
->link
= cpu_to_le32(td
->dma_handle
) | breadth
;
292 ptd
->link
= UHCI_PTR_TERM
;
295 static void uhci_free_td(struct uhci_hcd
*uhci
, struct uhci_td
*td
)
297 if (!list_empty(&td
->list
))
298 dbg("td %p is still in list!", td
);
299 if (!list_empty(&td
->fl_list
))
300 dbg("td %p is still in fl_list!", td
);
303 usb_put_dev(td
->dev
);
305 pci_pool_free(uhci
->td_pool
, td
, td
->dma_handle
);
308 static struct uhci_qh
*uhci_alloc_qh(struct uhci_hcd
*uhci
, struct usb_device
*dev
)
310 dma_addr_t dma_handle
;
313 qh
= pci_pool_alloc(uhci
->qh_pool
, GFP_ATOMIC
, &dma_handle
);
317 qh
->dma_handle
= dma_handle
;
319 qh
->element
= UHCI_PTR_TERM
;
320 qh
->link
= UHCI_PTR_TERM
;
325 INIT_LIST_HEAD(&qh
->list
);
326 INIT_LIST_HEAD(&qh
->remove_list
);
333 static void uhci_free_qh(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
)
335 if (!list_empty(&qh
->list
))
336 dbg("qh %p list not empty!", qh
);
337 if (!list_empty(&qh
->remove_list
))
338 dbg("qh %p still in remove_list!", qh
);
341 usb_put_dev(qh
->dev
);
343 pci_pool_free(uhci
->qh_pool
, qh
, qh
->dma_handle
);
347 * Append this urb's qh after the last qh in skelqh->list
348 * MUST be called with uhci->frame_list_lock acquired
350 * Note that urb_priv.queue_list doesn't have a separate queue head;
351 * it's a ring with every element "live".
353 static void _uhci_insert_qh(struct uhci_hcd
*uhci
, struct uhci_qh
*skelqh
, struct urb
*urb
)
355 struct urb_priv
*urbp
= (struct urb_priv
*)urb
->hcpriv
;
356 struct list_head
*tmp
;
359 /* Grab the last QH */
360 lqh
= list_entry(skelqh
->list
.prev
, struct uhci_qh
, list
);
363 * Patch this endpoint's URB's QHs to point to the next skelqh:
364 * skelqh --> ... lqh --> newqh --> next skelqh
365 * Do this first, so the HC always sees the right QH after this one.
367 list_for_each (tmp
, &urbp
->queue_list
) {
368 struct urb_priv
*turbp
=
369 list_entry(tmp
, struct urb_priv
, queue_list
);
371 turbp
->qh
->link
= lqh
->link
;
373 urbp
->qh
->link
= lqh
->link
;
374 wmb(); /* Ordering is important */
377 * Patch QHs for previous endpoint's queued URBs? HC goes
378 * here next, not to the next skelqh it now points to.
380 * lqh --> td ... --> qh ... --> td --> qh ... --> td
383 * +<----------------+-----------------+
385 * newqh --> td ... --> td
390 * The HC could see (and use!) any of these as we write them.
393 list_for_each (tmp
, &lqh
->urbp
->queue_list
) {
394 struct urb_priv
*turbp
=
395 list_entry(tmp
, struct urb_priv
, queue_list
);
397 turbp
->qh
->link
= cpu_to_le32(urbp
->qh
->dma_handle
) | UHCI_PTR_QH
;
400 lqh
->link
= cpu_to_le32(urbp
->qh
->dma_handle
) | UHCI_PTR_QH
;
402 list_add_tail(&urbp
->qh
->list
, &skelqh
->list
);
405 static void uhci_insert_qh(struct uhci_hcd
*uhci
, struct uhci_qh
*skelqh
, struct urb
*urb
)
409 spin_lock_irqsave(&uhci
->frame_list_lock
, flags
);
410 _uhci_insert_qh(uhci
, skelqh
, urb
);
411 spin_unlock_irqrestore(&uhci
->frame_list_lock
, flags
);
415 * Start removal of QH from schedule; it finishes next frame.
416 * TDs should be unlinked before this is called.
418 static void uhci_remove_qh(struct uhci_hcd
*uhci
, struct uhci_qh
*qh
)
429 * Only go through the hoops if it's actually linked in
430 * Queued QHs are removed in uhci_delete_queued_urb,
431 * since (for queued URBs) the pqh is pointed to the next
432 * QH in the queue, not the next endpoint's QH.
434 spin_lock_irqsave(&uhci
->frame_list_lock
, flags
);
435 if (!list_empty(&qh
->list
)) {
436 pqh
= list_entry(qh
->list
.prev
, struct uhci_qh
, list
);
439 struct list_head
*head
, *tmp
;
441 head
= &pqh
->urbp
->queue_list
;
443 while (head
!= tmp
) {
444 struct urb_priv
*turbp
=
445 list_entry(tmp
, struct urb_priv
, queue_list
);
449 turbp
->qh
->link
= qh
->link
;
453 pqh
->link
= qh
->link
;
455 /* Leave qh->link in case the HC is on the QH now, it will */
456 /* continue the rest of the schedule */
457 qh
->element
= UHCI_PTR_TERM
;
459 list_del_init(&qh
->list
);
461 spin_unlock_irqrestore(&uhci
->frame_list_lock
, flags
);
463 spin_lock_irqsave(&uhci
->qh_remove_list_lock
, flags
);
465 /* Check to see if the remove list is empty. Set the IOC bit */
466 /* to force an interrupt so we can remove the QH */
467 if (list_empty(&uhci
->qh_remove_list
))
468 uhci_set_next_interrupt(uhci
);
470 list_add(&qh
->remove_list
, &uhci
->qh_remove_list
);
472 spin_unlock_irqrestore(&uhci
->qh_remove_list_lock
, flags
);
475 static int uhci_fixup_toggle(struct urb
*urb
, unsigned int toggle
)
477 struct urb_priv
*urbp
= (struct urb_priv
*)urb
->hcpriv
;
478 struct list_head
*head
, *tmp
;
480 head
= &urbp
->td_list
;
482 while (head
!= tmp
) {
483 struct uhci_td
*td
= list_entry(tmp
, struct uhci_td
, list
);
488 td
->token
|= cpu_to_le32(TD_TOKEN_TOGGLE
);
490 td
->token
&= ~cpu_to_le32(TD_TOKEN_TOGGLE
);
499 /* This function will append one URB's QH to another URB's QH. This is for */
500 /* queuing interrupt, control or bulk transfers */
501 static void uhci_append_queued_urb(struct uhci_hcd
*uhci
, struct urb
*eurb
, struct urb
*urb
)
503 struct urb_priv
*eurbp
, *urbp
, *furbp
, *lurbp
;
504 struct list_head
*tmp
;
505 struct uhci_td
*lltd
;
508 eurbp
= eurb
->hcpriv
;
511 spin_lock_irqsave(&uhci
->frame_list_lock
, flags
);
513 /* Find the first URB in the queue */
515 struct list_head
*head
= &eurbp
->queue_list
;
518 while (tmp
!= head
) {
519 struct urb_priv
*turbp
=
520 list_entry(tmp
, struct urb_priv
, queue_list
);
528 tmp
= &eurbp
->queue_list
;
530 furbp
= list_entry(tmp
, struct urb_priv
, queue_list
);
531 lurbp
= list_entry(furbp
->queue_list
.prev
, struct urb_priv
, queue_list
);
533 lltd
= list_entry(lurbp
->td_list
.prev
, struct uhci_td
, list
);
535 usb_settoggle(urb
->dev
, usb_pipeendpoint(urb
->pipe
), usb_pipeout(urb
->pipe
),
536 uhci_fixup_toggle(urb
, uhci_toggle(td_token(lltd
)) ^ 1));
538 /* All qh's in the queue need to link to the next queue */
539 urbp
->qh
->link
= eurbp
->qh
->link
;
541 mb(); /* Make sure we flush everything */
543 lltd
->link
= cpu_to_le32(urbp
->qh
->dma_handle
) | UHCI_PTR_QH
;
545 list_add_tail(&urbp
->queue_list
, &furbp
->queue_list
);
549 spin_unlock_irqrestore(&uhci
->frame_list_lock
, flags
);
552 static void uhci_delete_queued_urb(struct uhci_hcd
*uhci
, struct urb
*urb
)
554 struct urb_priv
*urbp
, *nurbp
;
555 struct list_head
*head
, *tmp
;
556 struct urb_priv
*purbp
;
557 struct uhci_td
*pltd
;
563 spin_lock_irqsave(&uhci
->frame_list_lock
, flags
);
565 if (list_empty(&urbp
->queue_list
))
568 nurbp
= list_entry(urbp
->queue_list
.next
, struct urb_priv
, queue_list
);
570 /* Fix up the toggle for the next URB's */
572 /* We just set the toggle in uhci_unlink_generic */
573 toggle
= usb_gettoggle(urb
->dev
, usb_pipeendpoint(urb
->pipe
), usb_pipeout(urb
->pipe
));
575 /* If we're in the middle of the queue, grab the toggle */
576 /* from the TD previous to us */
577 purbp
= list_entry(urbp
->queue_list
.prev
, struct urb_priv
,
580 pltd
= list_entry(purbp
->td_list
.prev
, struct uhci_td
, list
);
582 toggle
= uhci_toggle(td_token(pltd
)) ^ 1;
585 head
= &urbp
->queue_list
;
587 while (head
!= tmp
) {
588 struct urb_priv
*turbp
;
590 turbp
= list_entry(tmp
, struct urb_priv
, queue_list
);
597 toggle
= uhci_fixup_toggle(turbp
->urb
, toggle
);
600 usb_settoggle(urb
->dev
, usb_pipeendpoint(urb
->pipe
),
601 usb_pipeout(urb
->pipe
), toggle
);
609 * Fixup the previous QH's queue to link to the new head
612 pqh
= list_entry(urbp
->qh
->list
.prev
, struct uhci_qh
, list
);
615 struct list_head
*head
, *tmp
;
617 head
= &pqh
->urbp
->queue_list
;
619 while (head
!= tmp
) {
620 struct urb_priv
*turbp
=
621 list_entry(tmp
, struct urb_priv
, queue_list
);
625 turbp
->qh
->link
= cpu_to_le32(nurbp
->qh
->dma_handle
) | UHCI_PTR_QH
;
629 pqh
->link
= cpu_to_le32(nurbp
->qh
->dma_handle
) | UHCI_PTR_QH
;
631 list_add_tail(&nurbp
->qh
->list
, &urbp
->qh
->list
);
632 list_del_init(&urbp
->qh
->list
);
634 /* We're somewhere in the middle (or end). A bit trickier */
635 /* than the head scenario */
636 purbp
= list_entry(urbp
->queue_list
.prev
, struct urb_priv
,
639 pltd
= list_entry(purbp
->td_list
.prev
, struct uhci_td
, list
);
641 pltd
->link
= cpu_to_le32(nurbp
->qh
->dma_handle
) | UHCI_PTR_QH
;
643 /* The next URB happens to be the beginning, so */
644 /* we're the last, end the chain */
645 pltd
->link
= UHCI_PTR_TERM
;
648 list_del_init(&urbp
->queue_list
);
651 spin_unlock_irqrestore(&uhci
->frame_list_lock
, flags
);
654 static struct urb_priv
*uhci_alloc_urb_priv(struct uhci_hcd
*uhci
, struct urb
*urb
)
656 struct urb_priv
*urbp
;
658 urbp
= kmem_cache_alloc(uhci_up_cachep
, SLAB_ATOMIC
);
660 err("uhci_alloc_urb_priv: couldn't allocate memory for urb_priv\n");
664 memset((void *)urbp
, 0, sizeof(*urbp
));
666 urbp
->inserttime
= jiffies
;
667 urbp
->fsbrtime
= jiffies
;
669 urbp
->dev
= urb
->dev
;
671 INIT_LIST_HEAD(&urbp
->td_list
);
672 INIT_LIST_HEAD(&urbp
->queue_list
);
673 INIT_LIST_HEAD(&urbp
->complete_list
);
674 INIT_LIST_HEAD(&urbp
->urb_list
);
676 list_add_tail(&urbp
->urb_list
, &uhci
->urb_list
);
684 * MUST be called with urb->lock acquired
686 static void uhci_add_td_to_urb(struct urb
*urb
, struct uhci_td
*td
)
688 struct urb_priv
*urbp
= (struct urb_priv
*)urb
->hcpriv
;
692 list_add_tail(&td
->list
, &urbp
->td_list
);
696 * MUST be called with urb->lock acquired
698 static void uhci_remove_td_from_urb(struct uhci_td
*td
)
700 if (list_empty(&td
->list
))
703 list_del_init(&td
->list
);
709 * MUST be called with urb->lock acquired
711 static void uhci_destroy_urb_priv(struct uhci_hcd
*uhci
, struct urb
*urb
)
713 struct list_head
*head
, *tmp
;
714 struct urb_priv
*urbp
;
716 urbp
= (struct urb_priv
*)urb
->hcpriv
;
720 if (!list_empty(&urbp
->urb_list
))
721 warn("uhci_destroy_urb_priv: urb %p still on uhci->urb_list or uhci->remove_list", urb
);
723 if (!list_empty(&urbp
->complete_list
))
724 warn("uhci_destroy_urb_priv: urb %p still on uhci->complete_list", urb
);
726 head
= &urbp
->td_list
;
728 while (tmp
!= head
) {
729 struct uhci_td
*td
= list_entry(tmp
, struct uhci_td
, list
);
733 uhci_remove_td_from_urb(td
);
734 uhci_remove_td(uhci
, td
);
735 uhci_free_td(uhci
, td
);
739 kmem_cache_free(uhci_up_cachep
, urbp
);
742 static void uhci_inc_fsbr(struct uhci_hcd
*uhci
, struct urb
*urb
)
745 struct urb_priv
*urbp
= (struct urb_priv
*)urb
->hcpriv
;
747 spin_lock_irqsave(&uhci
->frame_list_lock
, flags
);
749 if ((!(urb
->transfer_flags
& URB_NO_FSBR
)) && !urbp
->fsbr
) {
751 if (!uhci
->fsbr
++ && !uhci
->fsbrtimeout
)
752 uhci
->skel_term_qh
->link
= cpu_to_le32(uhci
->skel_hs_control_qh
->dma_handle
) | UHCI_PTR_QH
;
755 spin_unlock_irqrestore(&uhci
->frame_list_lock
, flags
);
758 static void uhci_dec_fsbr(struct uhci_hcd
*uhci
, struct urb
*urb
)
761 struct urb_priv
*urbp
= (struct urb_priv
*)urb
->hcpriv
;
763 spin_lock_irqsave(&uhci
->frame_list_lock
, flags
);
765 if ((!(urb
->transfer_flags
& URB_NO_FSBR
)) && urbp
->fsbr
) {
768 uhci
->fsbrtimeout
= jiffies
+ FSBR_DELAY
;
771 spin_unlock_irqrestore(&uhci
->frame_list_lock
, flags
);
775 * Map status to standard result codes
777 * <status> is (td->status & 0xFE0000) [a.k.a. uhci_status_bits(td->status)]
778 * <dir_out> is True for output TDs and False for input TDs.
780 static int uhci_map_status(int status
, int dir_out
)
784 if (status
& TD_CTRL_BITSTUFF
) /* Bitstuff error */
786 if (status
& TD_CTRL_CRCTIMEO
) { /* CRC/Timeout */
792 if (status
& TD_CTRL_NAK
) /* NAK */
794 if (status
& TD_CTRL_BABBLE
) /* Babble */
796 if (status
& TD_CTRL_DBUFERR
) /* Buffer error */
798 if (status
& TD_CTRL_STALLED
) /* Stalled */
800 if (status
& TD_CTRL_ACTIVE
) /* Active */
809 static int uhci_submit_control(struct uhci_hcd
*uhci
, struct urb
*urb
, struct urb
*eurb
)
811 struct urb_priv
*urbp
= (struct urb_priv
*)urb
->hcpriv
;
813 struct uhci_qh
*qh
, *skelqh
;
814 unsigned long destination
, status
;
815 int maxsze
= usb_maxpacket(urb
->dev
, urb
->pipe
, usb_pipeout(urb
->pipe
));
816 int len
= urb
->transfer_buffer_length
;
817 dma_addr_t data
= urb
->transfer_dma
;
819 /* The "pipe" thing contains the destination in bits 8--18 */
820 destination
= (urb
->pipe
& PIPE_DEVEP_MASK
) | USB_PID_SETUP
;
823 status
= TD_CTRL_ACTIVE
| uhci_maxerr(3);
824 if (urb
->dev
->speed
== USB_SPEED_LOW
)
825 status
|= TD_CTRL_LS
;
828 * Build the TD for the control request
830 td
= uhci_alloc_td(uhci
, urb
->dev
);
834 uhci_add_td_to_urb(urb
, td
);
835 uhci_fill_td(td
, status
, destination
| uhci_explen(7),
839 * If direction is "send", change the frame from SETUP (0x2D)
840 * to OUT (0xE1). Else change it from SETUP to IN (0x69).
842 destination
^= (USB_PID_SETUP
^ usb_packetid(urb
->pipe
));
844 if (!(urb
->transfer_flags
& URB_SHORT_NOT_OK
))
845 status
|= TD_CTRL_SPD
;
848 * Build the DATA TD's
856 td
= uhci_alloc_td(uhci
, urb
->dev
);
860 /* Alternate Data0/1 (start with Data1) */
861 destination
^= TD_TOKEN_TOGGLE
;
863 uhci_add_td_to_urb(urb
, td
);
864 uhci_fill_td(td
, status
, destination
| uhci_explen(pktsze
- 1),
872 * Build the final TD for control status
874 td
= uhci_alloc_td(uhci
, urb
->dev
);
879 * It's IN if the pipe is an output pipe or we're not expecting
882 destination
&= ~TD_TOKEN_PID_MASK
;
883 if (usb_pipeout(urb
->pipe
) || !urb
->transfer_buffer_length
)
884 destination
|= USB_PID_IN
;
886 destination
|= USB_PID_OUT
;
888 destination
|= TD_TOKEN_TOGGLE
; /* End in Data1 */
890 status
&= ~TD_CTRL_SPD
;
892 uhci_add_td_to_urb(urb
, td
);
893 uhci_fill_td(td
, status
| TD_CTRL_IOC
,
894 destination
| uhci_explen(UHCI_NULL_DATA_SIZE
), 0);
896 qh
= uhci_alloc_qh(uhci
, urb
->dev
);
903 uhci_insert_tds_in_qh(qh
, urb
, UHCI_PTR_BREADTH
);
905 /* Low speed transfers get a different queue, and won't hog the bus */
906 if (urb
->dev
->speed
== USB_SPEED_LOW
)
907 skelqh
= uhci
->skel_ls_control_qh
;
909 skelqh
= uhci
->skel_hs_control_qh
;
910 uhci_inc_fsbr(uhci
, urb
);
914 uhci_append_queued_urb(uhci
, eurb
, urb
);
916 uhci_insert_qh(uhci
, skelqh
, urb
);
922 * If control was short, then end status packet wasn't sent, so this
923 * reorganize s so it's sent to finish the transfer. The original QH is
924 * removed from the skel and discarded; all TDs except the last (status)
925 * are deleted; the last (status) TD is put on a new QH which is reinserted
926 * into the skel. Since the last TD and urb_priv are reused, the TD->link
927 * and urb_priv maintain any queued QHs.
929 static int usb_control_retrigger_status(struct uhci_hcd
*uhci
, struct urb
*urb
)
931 struct list_head
*tmp
, *head
;
932 struct urb_priv
*urbp
= (struct urb_priv
*)urb
->hcpriv
;
934 urbp
->short_control_packet
= 1;
936 /* Create a new QH to avoid pointer overwriting problems */
937 uhci_remove_qh(uhci
, urbp
->qh
);
939 /* Delete all of the TD's except for the status TD at the end */
940 head
= &urbp
->td_list
;
942 while (tmp
!= head
&& tmp
->next
!= head
) {
943 struct uhci_td
*td
= list_entry(tmp
, struct uhci_td
, list
);
947 uhci_remove_td_from_urb(td
);
948 uhci_remove_td(uhci
, td
);
949 uhci_free_td(uhci
, td
);
952 urbp
->qh
= uhci_alloc_qh(uhci
, urb
->dev
);
954 err("unable to allocate new QH for control retrigger");
958 urbp
->qh
->urbp
= urbp
;
960 /* One TD, who cares about Breadth first? */
961 uhci_insert_tds_in_qh(urbp
->qh
, urb
, UHCI_PTR_DEPTH
);
963 /* Low speed transfers get a different queue */
964 if (urb
->dev
->speed
== USB_SPEED_LOW
)
965 uhci_insert_qh(uhci
, uhci
->skel_ls_control_qh
, urb
);
967 uhci_insert_qh(uhci
, uhci
->skel_hs_control_qh
, urb
);
973 static int uhci_result_control(struct uhci_hcd
*uhci
, struct urb
*urb
)
975 struct list_head
*tmp
, *head
;
976 struct urb_priv
*urbp
= urb
->hcpriv
;
981 if (list_empty(&urbp
->td_list
))
984 head
= &urbp
->td_list
;
986 if (urbp
->short_control_packet
) {
992 td
= list_entry(tmp
, struct uhci_td
, list
);
994 /* The first TD is the SETUP phase, check the status, but skip */
996 status
= uhci_status_bits(td_status(td
));
997 if (status
& TD_CTRL_ACTIVE
)
1003 urb
->actual_length
= 0;
1005 /* The rest of the TD's (but the last) are data */
1007 while (tmp
!= head
&& tmp
->next
!= head
) {
1008 td
= list_entry(tmp
, struct uhci_td
, list
);
1012 status
= uhci_status_bits(td_status(td
));
1013 if (status
& TD_CTRL_ACTIVE
)
1014 return -EINPROGRESS
;
1016 urb
->actual_length
+= uhci_actual_length(td_status(td
));
1021 /* Check to see if we received a short packet */
1022 if (uhci_actual_length(td_status(td
)) < uhci_expected_length(td_token(td
))) {
1023 if (urb
->transfer_flags
& URB_SHORT_NOT_OK
) {
1028 if (uhci_packetid(td_token(td
)) == USB_PID_IN
)
1029 return usb_control_retrigger_status(uhci
, urb
);
1036 td
= list_entry(tmp
, struct uhci_td
, list
);
1038 /* Control status phase */
1039 status
= td_status(td
);
1041 #ifdef I_HAVE_BUGGY_APC_BACKUPS
1042 /* APC BackUPS Pro kludge */
1043 /* It tries to send all of the descriptor instead of the amount */
1045 if (status
& TD_CTRL_IOC
&& /* IOC is masked out by uhci_status_bits */
1046 status
& TD_CTRL_ACTIVE
&&
1047 status
& TD_CTRL_NAK
)
1051 if (status
& TD_CTRL_ACTIVE
)
1052 return -EINPROGRESS
;
1054 if (uhci_status_bits(status
))
1060 ret
= uhci_map_status(status
, uhci_packetout(td_token(td
)));
1063 if ((debug
== 1 && ret
!= -EPIPE
) || debug
> 1) {
1064 /* Some debugging code */
1065 dbg("uhci_result_control() failed with status %x", status
);
1068 /* Print the chain for debugging purposes */
1069 uhci_show_qh(urbp
->qh
, errbuf
, ERRBUF_LEN
, 0);
1079 * Common submit for bulk and interrupt
1081 static int uhci_submit_common(struct uhci_hcd
*uhci
, struct urb
*urb
, struct urb
*eurb
, struct uhci_qh
*skelqh
)
1085 unsigned long destination
, status
;
1086 int maxsze
= usb_maxpacket(urb
->dev
, urb
->pipe
, usb_pipeout(urb
->pipe
));
1087 int len
= urb
->transfer_buffer_length
;
1088 struct urb_priv
*urbp
= (struct urb_priv
*)urb
->hcpriv
;
1089 dma_addr_t data
= urb
->transfer_dma
;
1094 /* The "pipe" thing contains the destination in bits 8--18 */
1095 destination
= (urb
->pipe
& PIPE_DEVEP_MASK
) | usb_packetid(urb
->pipe
);
1097 status
= uhci_maxerr(3) | TD_CTRL_ACTIVE
;
1098 if (urb
->dev
->speed
== USB_SPEED_LOW
)
1099 status
|= TD_CTRL_LS
;
1100 if (!(urb
->transfer_flags
& URB_SHORT_NOT_OK
))
1101 status
|= TD_CTRL_SPD
;
1104 * Build the DATA TD's
1106 do { /* Allow zero length packets */
1109 if (pktsze
> maxsze
)
1112 td
= uhci_alloc_td(uhci
, urb
->dev
);
1116 uhci_add_td_to_urb(urb
, td
);
1117 uhci_fill_td(td
, status
, destination
| uhci_explen(pktsze
- 1) |
1118 (usb_gettoggle(urb
->dev
, usb_pipeendpoint(urb
->pipe
),
1119 usb_pipeout(urb
->pipe
)) << TD_TOKEN_TOGGLE_SHIFT
),
1125 usb_dotoggle(urb
->dev
, usb_pipeendpoint(urb
->pipe
),
1126 usb_pipeout(urb
->pipe
));
1130 * URB_ZERO_PACKET means adding a 0-length packet, if direction
1131 * is OUT and the transfer_length was an exact multiple of maxsze,
1132 * hence (len = transfer_length - N * maxsze) == 0
1133 * however, if transfer_length == 0, the zero packet was already
1136 if (usb_pipeout(urb
->pipe
) && (urb
->transfer_flags
& URB_ZERO_PACKET
) &&
1137 !len
&& urb
->transfer_buffer_length
) {
1138 td
= uhci_alloc_td(uhci
, urb
->dev
);
1142 uhci_add_td_to_urb(urb
, td
);
1143 uhci_fill_td(td
, status
, destination
| uhci_explen(UHCI_NULL_DATA_SIZE
) |
1144 (usb_gettoggle(urb
->dev
, usb_pipeendpoint(urb
->pipe
),
1145 usb_pipeout(urb
->pipe
)) << TD_TOKEN_TOGGLE_SHIFT
),
1148 usb_dotoggle(urb
->dev
, usb_pipeendpoint(urb
->pipe
),
1149 usb_pipeout(urb
->pipe
));
1152 /* Set the flag on the last packet */
1153 td
->status
|= cpu_to_le32(TD_CTRL_IOC
);
1155 qh
= uhci_alloc_qh(uhci
, urb
->dev
);
1162 /* Always breadth first */
1163 uhci_insert_tds_in_qh(qh
, urb
, UHCI_PTR_BREADTH
);
1166 uhci_append_queued_urb(uhci
, eurb
, urb
);
1168 uhci_insert_qh(uhci
, skelqh
, urb
);
1170 return -EINPROGRESS
;
1174 * Common result for bulk and interrupt
1176 static int uhci_result_common(struct uhci_hcd
*uhci
, struct urb
*urb
)
1178 struct list_head
*tmp
, *head
;
1179 struct urb_priv
*urbp
= urb
->hcpriv
;
1181 unsigned int status
= 0;
1184 urb
->actual_length
= 0;
1186 head
= &urbp
->td_list
;
1188 while (tmp
!= head
) {
1189 td
= list_entry(tmp
, struct uhci_td
, list
);
1193 status
= uhci_status_bits(td_status(td
));
1194 if (status
& TD_CTRL_ACTIVE
)
1195 return -EINPROGRESS
;
1197 urb
->actual_length
+= uhci_actual_length(td_status(td
));
1202 if (uhci_actual_length(td_status(td
)) < uhci_expected_length(td_token(td
))) {
1203 if (urb
->transfer_flags
& URB_SHORT_NOT_OK
) {
1214 ret
= uhci_map_status(status
, uhci_packetout(td_token(td
)));
1216 /* endpoint has stalled - mark it halted */
1217 usb_endpoint_halt(urb
->dev
, uhci_endpoint(td_token(td
)),
1218 uhci_packetout(td_token(td
)));
1222 * Enable this chunk of code if you want to see some more debugging.
1223 * But be careful, it has the tendancy to starve out khubd and prevent
1224 * disconnects from happening successfully if you have a slow debug
1225 * log interface (like a serial console.
1228 if ((debug
== 1 && ret
!= -EPIPE
) || debug
> 1) {
1229 /* Some debugging code */
1230 dbg("uhci_result_common() failed with status %x", status
);
1233 /* Print the chain for debugging purposes */
1234 uhci_show_qh(urbp
->qh
, errbuf
, ERRBUF_LEN
, 0);
1243 static inline int uhci_submit_bulk(struct uhci_hcd
*uhci
, struct urb
*urb
, struct urb
*eurb
)
1247 /* Can't have low speed bulk transfers */
1248 if (urb
->dev
->speed
== USB_SPEED_LOW
)
1251 ret
= uhci_submit_common(uhci
, urb
, eurb
, uhci
->skel_bulk_qh
);
1252 if (ret
== -EINPROGRESS
)
1253 uhci_inc_fsbr(uhci
, urb
);
1258 static inline int uhci_submit_interrupt(struct uhci_hcd
*uhci
, struct urb
*urb
, struct urb
*eurb
)
1260 /* USB 1.1 interrupt transfers only involve one packet per interval;
1261 * that's the uhci_submit_common() "breadth first" policy. Drivers
1262 * can submit urbs of any length, but longer ones might need many
1263 * intervals to complete.
1265 return uhci_submit_common(uhci
, urb
, eurb
, uhci
->skelqh
[__interval_to_skel(urb
->interval
)]);
1269 * Bulk and interrupt use common result
1271 #define uhci_result_bulk uhci_result_common
1272 #define uhci_result_interrupt uhci_result_common
1275 * Isochronous transfers
1277 static int isochronous_find_limits(struct uhci_hcd
*uhci
, struct urb
*urb
, unsigned int *start
, unsigned int *end
)
1279 struct urb
*last_urb
= NULL
;
1280 struct list_head
*tmp
, *head
;
1283 head
= &uhci
->urb_list
;
1285 while (tmp
!= head
) {
1286 struct urb_priv
*up
= list_entry(tmp
, struct urb_priv
, urb_list
);
1287 struct urb
*u
= up
->urb
;
1291 /* look for pending URB's with identical pipe handle */
1292 if ((urb
->pipe
== u
->pipe
) && (urb
->dev
== u
->dev
) &&
1293 (u
->status
== -EINPROGRESS
) && (u
!= urb
)) {
1295 *start
= u
->start_frame
;
1301 *end
= (last_urb
->start_frame
+ last_urb
->number_of_packets
*
1302 last_urb
->interval
) & (UHCI_NUMFRAMES
-1);
1305 ret
= -1; /* no previous urb found */
1310 static int isochronous_find_start(struct uhci_hcd
*uhci
, struct urb
*urb
)
1313 unsigned int start
= 0, end
= 0;
1315 if (urb
->number_of_packets
> 900) /* 900? Why? */
1318 limits
= isochronous_find_limits(uhci
, urb
, &start
, &end
);
1320 if (urb
->transfer_flags
& URB_ISO_ASAP
) {
1324 curframe
= uhci_get_current_frame_number(uhci
) % UHCI_NUMFRAMES
;
1325 urb
->start_frame
= (curframe
+ 10) % UHCI_NUMFRAMES
;
1327 urb
->start_frame
= end
;
1329 urb
->start_frame
%= UHCI_NUMFRAMES
;
1330 /* FIXME: Sanity check */
1337 * Isochronous transfers
1339 static int uhci_submit_isochronous(struct uhci_hcd
*uhci
, struct urb
*urb
)
1343 int status
, destination
;
1345 status
= TD_CTRL_ACTIVE
| TD_CTRL_IOS
;
1346 destination
= (urb
->pipe
& PIPE_DEVEP_MASK
) | usb_packetid(urb
->pipe
);
1348 ret
= isochronous_find_start(uhci
, urb
);
1352 frame
= urb
->start_frame
;
1353 for (i
= 0; i
< urb
->number_of_packets
; i
++, frame
+= urb
->interval
) {
1354 if (!urb
->iso_frame_desc
[i
].length
)
1357 td
= uhci_alloc_td(uhci
, urb
->dev
);
1361 uhci_add_td_to_urb(urb
, td
);
1362 uhci_fill_td(td
, status
, destination
| uhci_explen(urb
->iso_frame_desc
[i
].length
- 1),
1363 urb
->transfer_dma
+ urb
->iso_frame_desc
[i
].offset
);
1365 if (i
+ 1 >= urb
->number_of_packets
)
1366 td
->status
|= cpu_to_le32(TD_CTRL_IOC
);
1368 uhci_insert_td_frame_list(uhci
, td
, frame
);
1371 return -EINPROGRESS
;
1374 static int uhci_result_isochronous(struct uhci_hcd
*uhci
, struct urb
*urb
)
1376 struct list_head
*tmp
, *head
;
1377 struct urb_priv
*urbp
= (struct urb_priv
*)urb
->hcpriv
;
1381 urb
->actual_length
= 0;
1384 head
= &urbp
->td_list
;
1386 while (tmp
!= head
) {
1387 struct uhci_td
*td
= list_entry(tmp
, struct uhci_td
, list
);
1392 if (td_status(td
) & TD_CTRL_ACTIVE
)
1393 return -EINPROGRESS
;
1395 actlength
= uhci_actual_length(td_status(td
));
1396 urb
->iso_frame_desc
[i
].actual_length
= actlength
;
1397 urb
->actual_length
+= actlength
;
1399 status
= uhci_map_status(uhci_status_bits(td_status(td
)), usb_pipeout(urb
->pipe
));
1400 urb
->iso_frame_desc
[i
].status
= status
;
1413 * MUST be called with uhci->urb_list_lock acquired
1415 static struct urb
*uhci_find_urb_ep(struct uhci_hcd
*uhci
, struct urb
*urb
)
1417 struct list_head
*tmp
, *head
;
1419 /* We don't match Isoc transfers since they are special */
1420 if (usb_pipeisoc(urb
->pipe
))
1423 head
= &uhci
->urb_list
;
1425 while (tmp
!= head
) {
1426 struct urb_priv
*up
= list_entry(tmp
, struct urb_priv
, urb_list
);
1427 struct urb
*u
= up
->urb
;
1431 if (u
->dev
== urb
->dev
&& u
->status
== -EINPROGRESS
) {
1432 /* For control, ignore the direction */
1433 if (usb_pipecontrol(urb
->pipe
) &&
1434 (u
->pipe
& ~USB_DIR_IN
) == (urb
->pipe
& ~USB_DIR_IN
))
1436 else if (u
->pipe
== urb
->pipe
)
1444 static int uhci_urb_enqueue(struct usb_hcd
*hcd
, struct urb
*urb
, int mem_flags
)
1447 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
1448 unsigned long flags
;
1452 spin_lock_irqsave(&uhci
->urb_list_lock
, flags
);
1454 eurb
= uhci_find_urb_ep(uhci
, urb
);
1456 if (!uhci_alloc_urb_priv(uhci
, urb
)) {
1457 spin_unlock_irqrestore(&uhci
->urb_list_lock
, flags
);
1461 switch (usb_pipetype(urb
->pipe
)) {
1463 ret
= uhci_submit_control(uhci
, urb
, eurb
);
1465 case PIPE_INTERRUPT
:
1467 bustime
= usb_check_bandwidth(urb
->dev
, urb
);
1471 ret
= uhci_submit_interrupt(uhci
, urb
, eurb
);
1472 if (ret
== -EINPROGRESS
)
1473 usb_claim_bandwidth(urb
->dev
, urb
, bustime
, 0);
1475 } else { /* inherit from parent */
1476 urb
->bandwidth
= eurb
->bandwidth
;
1477 ret
= uhci_submit_interrupt(uhci
, urb
, eurb
);
1481 ret
= uhci_submit_bulk(uhci
, urb
, eurb
);
1483 case PIPE_ISOCHRONOUS
:
1484 bustime
= usb_check_bandwidth(urb
->dev
, urb
);
1490 ret
= uhci_submit_isochronous(uhci
, urb
);
1491 if (ret
== -EINPROGRESS
)
1492 usb_claim_bandwidth(urb
->dev
, urb
, bustime
, 1);
1496 if (ret
!= -EINPROGRESS
) {
1497 /* Submit failed, so delete it from the urb_list */
1498 struct urb_priv
*urbp
= urb
->hcpriv
;
1500 list_del_init(&urbp
->urb_list
);
1501 spin_unlock_irqrestore(&uhci
->urb_list_lock
, flags
);
1502 uhci_destroy_urb_priv (uhci
, urb
);
1507 spin_unlock_irqrestore(&uhci
->urb_list_lock
, flags
);
1513 * Return the result of a transfer
1515 * MUST be called with urb_list_lock acquired
1517 static void uhci_transfer_result(struct uhci_hcd
*uhci
, struct urb
*urb
)
1520 unsigned long flags
;
1521 struct urb_priv
*urbp
;
1523 spin_lock_irqsave(&urb
->lock
, flags
);
1525 urbp
= (struct urb_priv
*)urb
->hcpriv
;
1527 if (urb
->status
!= -EINPROGRESS
) {
1528 info("uhci_transfer_result: called for URB %p not in flight?", urb
);
1532 switch (usb_pipetype(urb
->pipe
)) {
1534 ret
= uhci_result_control(uhci
, urb
);
1536 case PIPE_INTERRUPT
:
1537 ret
= uhci_result_interrupt(uhci
, urb
);
1540 ret
= uhci_result_bulk(uhci
, urb
);
1542 case PIPE_ISOCHRONOUS
:
1543 ret
= uhci_result_isochronous(uhci
, urb
);
1549 if (ret
== -EINPROGRESS
)
1552 switch (usb_pipetype(urb
->pipe
)) {
1555 case PIPE_ISOCHRONOUS
:
1556 /* Release bandwidth for Interrupt or Isoc. transfers */
1557 /* Spinlock needed ? */
1559 usb_release_bandwidth(urb
->dev
, urb
, 1);
1560 uhci_unlink_generic(uhci
, urb
);
1562 case PIPE_INTERRUPT
:
1563 /* Release bandwidth for Interrupt or Isoc. transfers */
1564 /* Make sure we don't release if we have a queued URB */
1565 spin_lock(&uhci
->frame_list_lock
);
1566 /* Spinlock needed ? */
1567 if (list_empty(&urbp
->queue_list
) && urb
->bandwidth
)
1568 usb_release_bandwidth(urb
->dev
, urb
, 0);
1570 /* bandwidth was passed on to queued URB, */
1571 /* so don't let usb_unlink_urb() release it */
1573 spin_unlock(&uhci
->frame_list_lock
);
1574 uhci_unlink_generic(uhci
, urb
);
1577 info("uhci_transfer_result: unknown pipe type %d for urb %p\n",
1578 usb_pipetype(urb
->pipe
), urb
);
1581 /* Remove it from uhci->urb_list */
1582 list_del_init(&urbp
->urb_list
);
1584 uhci_add_complete(uhci
, urb
);
1587 spin_unlock_irqrestore(&urb
->lock
, flags
);
1591 * MUST be called with urb->lock acquired
1593 static void uhci_unlink_generic(struct uhci_hcd
*uhci
, struct urb
*urb
)
1595 struct list_head
*head
, *tmp
;
1596 struct urb_priv
*urbp
= (struct urb_priv
*)urb
->hcpriv
;
1599 /* We can get called when urbp allocation fails, so check */
1603 uhci_dec_fsbr(uhci
, urb
); /* Safe since it checks */
1606 * Now we need to find out what the last successful toggle was
1607 * so we can update the local data toggle for the next transfer
1609 * There's 3 way's the last successful completed TD is found:
1611 * 1) The TD is NOT active and the actual length < expected length
1612 * 2) The TD is NOT active and it's the last TD in the chain
1613 * 3) The TD is active and the previous TD is NOT active
1615 * Control and Isochronous ignore the toggle, so this is safe
1618 head
= &urbp
->td_list
;
1620 while (tmp
!= head
) {
1621 struct uhci_td
*td
= list_entry(tmp
, struct uhci_td
, list
);
1625 if (!(td_status(td
) & TD_CTRL_ACTIVE
) &&
1626 (uhci_actual_length(td_status(td
)) < uhci_expected_length(td_token(td
)) ||
1628 usb_settoggle(urb
->dev
, uhci_endpoint(td_token(td
)),
1629 uhci_packetout(td_token(td
)),
1630 uhci_toggle(td_token(td
)) ^ 1);
1631 else if ((td_status(td
) & TD_CTRL_ACTIVE
) && !prevactive
)
1632 usb_settoggle(urb
->dev
, uhci_endpoint(td_token(td
)),
1633 uhci_packetout(td_token(td
)),
1634 uhci_toggle(td_token(td
)));
1636 prevactive
= td_status(td
) & TD_CTRL_ACTIVE
;
1639 uhci_delete_queued_urb(uhci
, urb
);
1641 /* The interrupt loop will reclaim the QH's */
1642 uhci_remove_qh(uhci
, urbp
->qh
);
1646 static int uhci_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
)
1648 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
1649 unsigned long flags
;
1650 struct urb_priv
*urbp
= urb
->hcpriv
;
1652 /* If this is an interrupt URB that is being killed in urb->complete, */
1653 /* then just set its status and return */
1655 urb
->status
= -ECONNRESET
;
1659 spin_lock_irqsave(&uhci
->urb_list_lock
, flags
);
1661 list_del_init(&urbp
->urb_list
);
1663 uhci_unlink_generic(uhci
, urb
);
1665 spin_lock(&uhci
->urb_remove_list_lock
);
1667 /* If we're the first, set the next interrupt bit */
1668 if (list_empty(&uhci
->urb_remove_list
))
1669 uhci_set_next_interrupt(uhci
);
1670 list_add(&urbp
->urb_list
, &uhci
->urb_remove_list
);
1672 spin_unlock(&uhci
->urb_remove_list_lock
);
1673 spin_unlock_irqrestore(&uhci
->urb_list_lock
, flags
);
1677 static int uhci_fsbr_timeout(struct uhci_hcd
*uhci
, struct urb
*urb
)
1679 struct urb_priv
*urbp
= (struct urb_priv
*)urb
->hcpriv
;
1680 struct list_head
*head
, *tmp
;
1683 uhci_dec_fsbr(uhci
, urb
);
1685 urbp
->fsbr_timeout
= 1;
1688 * Ideally we would want to fix qh->element as well, but it's
1689 * read/write by the HC, so that can introduce a race. It's not
1690 * really worth the hassle
1693 head
= &urbp
->td_list
;
1695 while (tmp
!= head
) {
1696 struct uhci_td
*td
= list_entry(tmp
, struct uhci_td
, list
);
1701 * Make sure we don't do the last one (since it'll have the
1702 * TERM bit set) as well as we skip every so many TD's to
1703 * make sure it doesn't hog the bandwidth
1705 if (tmp
!= head
&& (count
% DEPTH_INTERVAL
) == (DEPTH_INTERVAL
- 1))
1706 td
->link
|= UHCI_PTR_DEPTH
;
1715 * uhci_get_current_frame_number()
1717 * returns the current frame number for a USB bus/controller.
1719 static int uhci_get_current_frame_number(struct uhci_hcd
*uhci
)
1721 return inw(uhci
->io_addr
+ USBFRNUM
);
1724 static int init_stall_timer(struct usb_hcd
*hcd
);
1726 static void stall_callback(unsigned long ptr
)
1728 struct usb_hcd
*hcd
= (struct usb_hcd
*)ptr
;
1729 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
1730 struct list_head list
, *tmp
, *head
;
1731 unsigned long flags
;
1733 INIT_LIST_HEAD(&list
);
1735 spin_lock_irqsave(&uhci
->urb_list_lock
, flags
);
1736 head
= &uhci
->urb_list
;
1738 while (tmp
!= head
) {
1739 struct urb_priv
*up
= list_entry(tmp
, struct urb_priv
, urb_list
);
1740 struct urb
*u
= up
->urb
;
1744 spin_lock(&u
->lock
);
1746 /* Check if the FSBR timed out */
1747 if (up
->fsbr
&& !up
->fsbr_timeout
&& time_after_eq(jiffies
, up
->fsbrtime
+ IDLE_TIMEOUT
))
1748 uhci_fsbr_timeout(uhci
, u
);
1750 /* Check if the URB timed out */
1751 if (u
->timeout
&& time_after_eq(jiffies
, up
->inserttime
+ u
->timeout
))
1752 list_move_tail(&up
->urb_list
, &list
);
1754 spin_unlock(&u
->lock
);
1756 spin_unlock_irqrestore(&uhci
->urb_list_lock
, flags
);
1760 while (tmp
!= head
) {
1761 struct urb_priv
*up
= list_entry(tmp
, struct urb_priv
, urb_list
);
1762 struct urb
*u
= up
->urb
;
1766 uhci_urb_dequeue(hcd
, u
);
1769 /* Really disable FSBR */
1770 if (!uhci
->fsbr
&& uhci
->fsbrtimeout
&& time_after_eq(jiffies
, uhci
->fsbrtimeout
)) {
1771 uhci
->fsbrtimeout
= 0;
1772 uhci
->skel_term_qh
->link
= UHCI_PTR_TERM
;
1775 /* Poll for and perform state transitions */
1776 hc_state_transitions(uhci
);
1778 init_stall_timer(hcd
);
1781 static int init_stall_timer(struct usb_hcd
*hcd
)
1783 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
1785 init_timer(&uhci
->stall_timer
);
1786 uhci
->stall_timer
.function
= stall_callback
;
1787 uhci
->stall_timer
.data
= (unsigned long)hcd
;
1788 uhci
->stall_timer
.expires
= jiffies
+ (HZ
/ 10);
1789 add_timer(&uhci
->stall_timer
);
1794 static void uhci_free_pending_qhs(struct uhci_hcd
*uhci
)
1796 struct list_head
*tmp
, *head
;
1797 unsigned long flags
;
1799 spin_lock_irqsave(&uhci
->qh_remove_list_lock
, flags
);
1800 head
= &uhci
->qh_remove_list
;
1802 while (tmp
!= head
) {
1803 struct uhci_qh
*qh
= list_entry(tmp
, struct uhci_qh
, remove_list
);
1807 list_del_init(&qh
->remove_list
);
1809 uhci_free_qh(uhci
, qh
);
1811 spin_unlock_irqrestore(&uhci
->qh_remove_list_lock
, flags
);
1814 static void uhci_finish_urb(struct usb_hcd
*hcd
, struct urb
*urb
, struct pt_regs
*regs
)
1816 struct urb_priv
*urbp
= (struct urb_priv
*)urb
->hcpriv
;
1817 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
1819 unsigned long flags
;
1821 spin_lock_irqsave(&urb
->lock
, flags
);
1822 status
= urbp
->status
;
1823 uhci_destroy_urb_priv(uhci
, urb
);
1825 if (urb
->status
!= -ENOENT
&& urb
->status
!= -ECONNRESET
)
1826 urb
->status
= status
;
1827 spin_unlock_irqrestore(&urb
->lock
, flags
);
1829 usb_hcd_giveback_urb(hcd
, urb
, regs
);
1832 static void uhci_finish_completion(struct usb_hcd
*hcd
, struct pt_regs
*regs
)
1834 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
1835 struct list_head
*tmp
, *head
;
1836 unsigned long flags
;
1838 spin_lock_irqsave(&uhci
->complete_list_lock
, flags
);
1839 head
= &uhci
->complete_list
;
1841 while (tmp
!= head
) {
1842 struct urb_priv
*urbp
= list_entry(tmp
, struct urb_priv
, complete_list
);
1843 struct urb
*urb
= urbp
->urb
;
1845 list_del_init(&urbp
->complete_list
);
1846 spin_unlock_irqrestore(&uhci
->complete_list_lock
, flags
);
1848 uhci_finish_urb(hcd
, urb
, regs
);
1850 spin_lock_irqsave(&uhci
->complete_list_lock
, flags
);
1851 head
= &uhci
->complete_list
;
1854 spin_unlock_irqrestore(&uhci
->complete_list_lock
, flags
);
1857 static void uhci_remove_pending_qhs(struct uhci_hcd
*uhci
)
1859 struct list_head
*tmp
, *head
;
1860 unsigned long flags
;
1862 spin_lock_irqsave(&uhci
->urb_remove_list_lock
, flags
);
1863 head
= &uhci
->urb_remove_list
;
1865 while (tmp
!= head
) {
1866 struct urb_priv
*urbp
= list_entry(tmp
, struct urb_priv
, urb_list
);
1867 struct urb
*urb
= urbp
->urb
;
1871 list_del_init(&urbp
->urb_list
);
1873 urbp
->status
= urb
->status
= -ECONNRESET
;
1875 uhci_add_complete(uhci
, urb
);
1877 spin_unlock_irqrestore(&uhci
->urb_remove_list_lock
, flags
);
1880 static int uhci_irq(struct usb_hcd
*hcd
, struct pt_regs
*regs
)
1882 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
1883 unsigned int io_addr
= uhci
->io_addr
;
1884 unsigned short status
;
1885 struct list_head
*tmp
, *head
;
1888 * Read the interrupt status, and write it back to clear the
1891 status
= inw(io_addr
+ USBSTS
);
1892 if (!status
) /* shared interrupt, not mine */
1894 outw(status
, io_addr
+ USBSTS
); /* Clear it */
1896 if (status
& ~(USBSTS_USBINT
| USBSTS_ERROR
| USBSTS_RD
)) {
1897 if (status
& USBSTS_HSE
)
1898 err("%x: host system error, PCI problems?", io_addr
);
1899 if (status
& USBSTS_HCPE
)
1900 err("%x: host controller process error. something bad happened", io_addr
);
1901 if ((status
& USBSTS_HCH
) && uhci
->state
> 0) {
1902 err("%x: host controller halted. very bad", io_addr
);
1903 /* FIXME: Reset the controller, fix the offending TD */
1907 if (status
& USBSTS_RD
)
1908 uhci
->resume_detect
= 1;
1910 uhci_free_pending_qhs(uhci
);
1912 uhci_remove_pending_qhs(uhci
);
1914 uhci_clear_next_interrupt(uhci
);
1916 /* Walk the list of pending URB's to see which ones completed */
1917 spin_lock(&uhci
->urb_list_lock
);
1918 head
= &uhci
->urb_list
;
1920 while (tmp
!= head
) {
1921 struct urb_priv
*urbp
= list_entry(tmp
, struct urb_priv
, urb_list
);
1922 struct urb
*urb
= urbp
->urb
;
1926 /* Checks the status and does all of the magic necessary */
1927 uhci_transfer_result(uhci
, urb
);
1929 spin_unlock(&uhci
->urb_list_lock
);
1931 uhci_finish_completion(hcd
, regs
);
1936 static void reset_hc(struct uhci_hcd
*uhci
)
1938 unsigned int io_addr
= uhci
->io_addr
;
1940 /* Global reset for 50ms */
1941 uhci
->state
= UHCI_RESET
;
1942 outw(USBCMD_GRESET
, io_addr
+ USBCMD
);
1943 set_current_state(TASK_UNINTERRUPTIBLE
);
1944 schedule_timeout((HZ
*50+999) / 1000);
1945 set_current_state(TASK_RUNNING
);
1946 outw(0, io_addr
+ USBCMD
);
1948 /* Another 10ms delay */
1949 set_current_state(TASK_UNINTERRUPTIBLE
);
1950 schedule_timeout((HZ
*10+999) / 1000);
1951 set_current_state(TASK_RUNNING
);
1952 uhci
->resume_detect
= 0;
1955 static void suspend_hc(struct uhci_hcd
*uhci
)
1957 unsigned int io_addr
= uhci
->io_addr
;
1959 dbg("%x: suspend_hc", io_addr
);
1960 uhci
->state
= UHCI_SUSPENDED
;
1961 uhci
->resume_detect
= 0;
1962 outw(USBCMD_EGSM
, io_addr
+ USBCMD
);
1965 static void wakeup_hc(struct uhci_hcd
*uhci
)
1967 unsigned int io_addr
= uhci
->io_addr
;
1969 switch (uhci
->state
) {
1970 case UHCI_SUSPENDED
: /* Start the resume */
1971 dbg("%x: wakeup_hc", io_addr
);
1973 /* Global resume for >= 20ms */
1974 outw(USBCMD_FGR
| USBCMD_EGSM
, io_addr
+ USBCMD
);
1975 uhci
->state
= UHCI_RESUMING_1
;
1976 uhci
->state_end
= jiffies
+ (20*HZ
+999) / 1000;
1979 case UHCI_RESUMING_1
: /* End global resume */
1980 uhci
->state
= UHCI_RESUMING_2
;
1981 outw(0, io_addr
+ USBCMD
);
1984 case UHCI_RESUMING_2
: /* Wait for EOP to be sent */
1985 if (inw(io_addr
+ USBCMD
) & USBCMD_FGR
)
1988 /* Run for at least 1 second, and
1989 * mark it configured with a 64-byte max packet */
1990 uhci
->state
= UHCI_RUNNING_GRACE
;
1991 uhci
->state_end
= jiffies
+ HZ
;
1992 outw(USBCMD_RS
| USBCMD_CF
| USBCMD_MAXP
,
1996 case UHCI_RUNNING_GRACE
: /* Now allowed to suspend */
1997 uhci
->state
= UHCI_RUNNING
;
2005 static int ports_active(struct uhci_hcd
*uhci
)
2007 unsigned int io_addr
= uhci
->io_addr
;
2011 for (i
= 0; i
< uhci
->rh_numports
; i
++)
2012 connection
|= (inw(io_addr
+ USBPORTSC1
+ i
* 2) & USBPORTSC_CCS
);
2017 static int suspend_allowed(struct uhci_hcd
*uhci
)
2019 unsigned int io_addr
= uhci
->io_addr
;
2022 if (!uhci
->hcd
.pdev
||
2023 uhci
->hcd
.pdev
->vendor
!= PCI_VENDOR_ID_INTEL
||
2024 uhci
->hcd
.pdev
->device
!= PCI_DEVICE_ID_INTEL_82371AB_2
)
2027 /* This is a 82371AB/EB/MB USB controller which has a bug that
2028 * causes false resume indications if any port has an
2029 * over current condition. To prevent problems, we will not
2030 * allow a global suspend if any ports are OC.
2032 * Some motherboards using the 82371AB/EB/MB (but not the USB portion)
2033 * appear to hardwire the over current inputs active to disable
2037 /* check for over current condition on any port */
2038 for (i
= 0; i
< uhci
->rh_numports
; i
++) {
2039 if (inw(io_addr
+ USBPORTSC1
+ i
* 2) & USBPORTSC_OC
)
2046 static void hc_state_transitions(struct uhci_hcd
*uhci
)
2048 switch (uhci
->state
) {
2051 /* global suspend if nothing connected for 1 second */
2052 if (!ports_active(uhci
) && suspend_allowed(uhci
)) {
2053 uhci
->state
= UHCI_SUSPENDING_GRACE
;
2054 uhci
->state_end
= jiffies
+ HZ
;
2058 case UHCI_SUSPENDING_GRACE
:
2059 if (ports_active(uhci
))
2060 uhci
->state
= UHCI_RUNNING
;
2061 else if (time_after_eq(jiffies
, uhci
->state_end
))
2065 case UHCI_SUSPENDED
:
2067 /* wakeup if requested by a device */
2068 if (uhci
->resume_detect
)
2072 case UHCI_RESUMING_1
:
2073 case UHCI_RESUMING_2
:
2074 case UHCI_RUNNING_GRACE
:
2075 if (time_after_eq(jiffies
, uhci
->state_end
))
2084 static void start_hc(struct uhci_hcd
*uhci
)
2086 unsigned int io_addr
= uhci
->io_addr
;
2090 * Reset the HC - this will force us to get a
2091 * new notification of any already connected
2092 * ports due to the virtual disconnect that it
2095 outw(USBCMD_HCRESET
, io_addr
+ USBCMD
);
2096 while (inw(io_addr
+ USBCMD
) & USBCMD_HCRESET
) {
2098 printk(KERN_ERR
"uhci: USBCMD_HCRESET timed out!\n");
2103 /* Turn on all interrupts */
2104 outw(USBINTR_TIMEOUT
| USBINTR_RESUME
| USBINTR_IOC
| USBINTR_SP
,
2107 /* Start at frame 0 */
2108 outw(0, io_addr
+ USBFRNUM
);
2109 outl(uhci
->fl
->dma_handle
, io_addr
+ USBFLBASEADD
);
2111 /* Run and mark it configured with a 64-byte max packet */
2112 uhci
->state
= UHCI_RUNNING_GRACE
;
2113 uhci
->state_end
= jiffies
+ HZ
;
2114 outw(USBCMD_RS
| USBCMD_CF
| USBCMD_MAXP
, io_addr
+ USBCMD
);
2116 uhci
->hcd
.state
= USB_STATE_READY
;
2120 * De-allocate all resources..
2122 static void release_uhci(struct uhci_hcd
*uhci
)
2126 for (i
= 0; i
< UHCI_NUM_SKELQH
; i
++)
2127 if (uhci
->skelqh
[i
]) {
2128 uhci_free_qh(uhci
, uhci
->skelqh
[i
]);
2129 uhci
->skelqh
[i
] = NULL
;
2132 if (uhci
->term_td
) {
2133 uhci_free_td(uhci
, uhci
->term_td
);
2134 uhci
->term_td
= NULL
;
2137 if (uhci
->qh_pool
) {
2138 pci_pool_destroy(uhci
->qh_pool
);
2139 uhci
->qh_pool
= NULL
;
2142 if (uhci
->td_pool
) {
2143 pci_pool_destroy(uhci
->td_pool
);
2144 uhci
->td_pool
= NULL
;
2148 pci_free_consistent(uhci
->hcd
.pdev
, sizeof(*uhci
->fl
), uhci
->fl
, uhci
->fl
->dma_handle
);
2152 #ifdef CONFIG_PROC_FS
2153 if (uhci
->proc_entry
) {
2154 remove_proc_entry(uhci
->hcd
.self
.bus_name
, uhci_proc_root
);
2155 uhci
->proc_entry
= NULL
;
2161 * Allocate a frame list, and then setup the skeleton
2163 * The hardware doesn't really know any difference
2164 * in the queues, but the order does matter for the
2165 * protocols higher up. The order is:
2167 * - any isochronous events handled before any
2168 * of the queues. We don't do that here, because
2169 * we'll create the actual TD entries on demand.
2170 * - The first queue is the interrupt queue.
2171 * - The second queue is the control queue, split into low and high speed
2172 * - The third queue is bulk queue.
2173 * - The fourth queue is the bandwidth reclamation queue, which loops back
2174 * to the high speed control queue.
2176 static int __devinit
uhci_start(struct usb_hcd
*hcd
)
2178 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
2179 int retval
= -EBUSY
;
2182 dma_addr_t dma_handle
;
2183 struct usb_device
*udev
;
2184 #ifdef CONFIG_PROC_FS
2185 struct proc_dir_entry
*ent
;
2188 uhci
->io_addr
= (unsigned long) hcd
->regs
;
2189 io_size
= pci_resource_len(hcd
->pdev
, hcd
->region
);
2191 #ifdef CONFIG_PROC_FS
2192 ent
= create_proc_entry(hcd
->self
.bus_name
, S_IFREG
|S_IRUGO
|S_IWUSR
, uhci_proc_root
);
2194 err("couldn't create uhci proc entry");
2196 goto err_create_proc_entry
;
2200 ent
->proc_fops
= &uhci_proc_operations
;
2202 uhci
->proc_entry
= ent
;
2205 /* Reset here so we don't get any interrupts from an old setup */
2206 /* or broken setup */
2210 uhci
->fsbrtimeout
= 0;
2212 spin_lock_init(&uhci
->qh_remove_list_lock
);
2213 INIT_LIST_HEAD(&uhci
->qh_remove_list
);
2215 spin_lock_init(&uhci
->urb_remove_list_lock
);
2216 INIT_LIST_HEAD(&uhci
->urb_remove_list
);
2218 spin_lock_init(&uhci
->urb_list_lock
);
2219 INIT_LIST_HEAD(&uhci
->urb_list
);
2221 spin_lock_init(&uhci
->complete_list_lock
);
2222 INIT_LIST_HEAD(&uhci
->complete_list
);
2224 spin_lock_init(&uhci
->frame_list_lock
);
2226 uhci
->fl
= pci_alloc_consistent(hcd
->pdev
, sizeof(*uhci
->fl
), &dma_handle
);
2228 err("unable to allocate consistent memory for frame list");
2232 memset((void *)uhci
->fl
, 0, sizeof(*uhci
->fl
));
2234 uhci
->fl
->dma_handle
= dma_handle
;
2236 uhci
->td_pool
= pci_pool_create("uhci_td", hcd
->pdev
,
2237 sizeof(struct uhci_td
), 16, 0);
2238 if (!uhci
->td_pool
) {
2239 err("unable to create td pci_pool");
2240 goto err_create_td_pool
;
2243 uhci
->qh_pool
= pci_pool_create("uhci_qh", hcd
->pdev
,
2244 sizeof(struct uhci_qh
), 16, 0);
2245 if (!uhci
->qh_pool
) {
2246 err("unable to create qh pci_pool");
2247 goto err_create_qh_pool
;
2250 /* Initialize the root hub */
2252 /* UHCI specs says devices must have 2 ports, but goes on to say */
2253 /* they may have more but give no way to determine how many they */
2254 /* have. However, according to the UHCI spec, Bit 7 is always set */
2255 /* to 1. So we try to use this to our advantage */
2256 for (port
= 0; port
< (io_size
- 0x10) / 2; port
++) {
2257 unsigned int portstatus
;
2259 portstatus
= inw(uhci
->io_addr
+ 0x10 + (port
* 2));
2260 if (!(portstatus
& 0x0080))
2264 info("detected %d ports", port
);
2266 /* This is experimental so anything less than 2 or greater than 8 is */
2267 /* something weird and we'll ignore it */
2268 if (port
< 2 || port
> 8) {
2269 info("port count misdetected? forcing to 2 ports");
2273 uhci
->rh_numports
= port
;
2275 hcd
->self
.root_hub
= udev
= usb_alloc_dev(NULL
, &hcd
->self
);
2277 err("unable to allocate root hub");
2278 goto err_alloc_root_hub
;
2280 hcd
->pdev
->bus
= (struct pci_bus
*)udev
; /* Fix bus pointer for initial device */
2282 uhci
->term_td
= uhci_alloc_td(uhci
, udev
);
2283 if (!uhci
->term_td
) {
2284 err("unable to allocate terminating TD");
2285 goto err_alloc_term_td
;
2288 for (i
= 0; i
< UHCI_NUM_SKELQH
; i
++) {
2289 uhci
->skelqh
[i
] = uhci_alloc_qh(uhci
, udev
);
2290 if (!uhci
->skelqh
[i
]) {
2291 err("unable to allocate QH %d", i
);
2292 goto err_alloc_skelqh
;
2297 * 8 Interrupt queues; link int2 to int1, int4 to int2, etc
2298 * then link int1 to control and control to bulk
2300 uhci
->skel_int128_qh
->link
= cpu_to_le32(uhci
->skel_int64_qh
->dma_handle
) | UHCI_PTR_QH
;
2301 uhci
->skel_int64_qh
->link
= cpu_to_le32(uhci
->skel_int32_qh
->dma_handle
) | UHCI_PTR_QH
;
2302 uhci
->skel_int32_qh
->link
= cpu_to_le32(uhci
->skel_int16_qh
->dma_handle
) | UHCI_PTR_QH
;
2303 uhci
->skel_int16_qh
->link
= cpu_to_le32(uhci
->skel_int8_qh
->dma_handle
) | UHCI_PTR_QH
;
2304 uhci
->skel_int8_qh
->link
= cpu_to_le32(uhci
->skel_int4_qh
->dma_handle
) | UHCI_PTR_QH
;
2305 uhci
->skel_int4_qh
->link
= cpu_to_le32(uhci
->skel_int2_qh
->dma_handle
) | UHCI_PTR_QH
;
2306 uhci
->skel_int2_qh
->link
= cpu_to_le32(uhci
->skel_int1_qh
->dma_handle
) | UHCI_PTR_QH
;
2307 uhci
->skel_int1_qh
->link
= cpu_to_le32(uhci
->skel_ls_control_qh
->dma_handle
) | UHCI_PTR_QH
;
2309 uhci
->skel_ls_control_qh
->link
= cpu_to_le32(uhci
->skel_hs_control_qh
->dma_handle
) | UHCI_PTR_QH
;
2310 uhci
->skel_hs_control_qh
->link
= cpu_to_le32(uhci
->skel_bulk_qh
->dma_handle
) | UHCI_PTR_QH
;
2311 uhci
->skel_bulk_qh
->link
= cpu_to_le32(uhci
->skel_term_qh
->dma_handle
) | UHCI_PTR_QH
;
2313 /* This dummy TD is to work around a bug in Intel PIIX controllers */
2314 uhci_fill_td(uhci
->term_td
, 0, (UHCI_NULL_DATA_SIZE
<< 21) |
2315 (0x7f << TD_TOKEN_DEVADDR_SHIFT
) | USB_PID_IN
, 0);
2316 uhci
->term_td
->link
= cpu_to_le32(uhci
->term_td
->dma_handle
);
2318 uhci
->skel_term_qh
->link
= UHCI_PTR_TERM
;
2319 uhci
->skel_term_qh
->element
= cpu_to_le32(uhci
->term_td
->dma_handle
);
2322 * Fill the frame list: make all entries point to
2323 * the proper interrupt queue.
2325 * This is probably silly, but it's a simple way to
2326 * scatter the interrupt queues in a way that gives
2327 * us a reasonable dynamic range for irq latencies.
2329 for (i
= 0; i
< UHCI_NUMFRAMES
; i
++) {
2353 /* Only place we don't use the frame list routines */
2354 uhci
->fl
->frame
[i
] = cpu_to_le32(uhci
->skelqh
[7 - irq
]->dma_handle
);
2359 init_stall_timer(hcd
);
2361 /* disable legacy emulation */
2362 pci_write_config_word(hcd
->pdev
, USBLEGSUP
, USBLEGSUP_DEFAULT
);
2365 udev
->speed
= USB_SPEED_FULL
;
2367 if (usb_register_root_hub(udev
, &hcd
->pdev
->dev
) != 0) {
2368 err("unable to start root hub");
2370 goto err_start_root_hub
;
2381 del_timer_sync(&uhci
->stall_timer
);
2384 for (i
= 0; i
< UHCI_NUM_SKELQH
; i
++)
2385 if (uhci
->skelqh
[i
]) {
2386 uhci_free_qh(uhci
, uhci
->skelqh
[i
]);
2387 uhci
->skelqh
[i
] = NULL
;
2390 uhci_free_td(uhci
, uhci
->term_td
);
2391 uhci
->term_td
= NULL
;
2395 hcd
->self
.root_hub
= NULL
;
2398 pci_pool_destroy(uhci
->qh_pool
);
2399 uhci
->qh_pool
= NULL
;
2402 pci_pool_destroy(uhci
->td_pool
);
2403 uhci
->td_pool
= NULL
;
2406 pci_free_consistent(hcd
->pdev
, sizeof(*uhci
->fl
), uhci
->fl
, uhci
->fl
->dma_handle
);
2410 #ifdef CONFIG_PROC_FS
2411 remove_proc_entry(hcd
->self
.bus_name
, uhci_proc_root
);
2412 uhci
->proc_entry
= NULL
;
2414 err_create_proc_entry
:
2420 static void uhci_stop(struct usb_hcd
*hcd
)
2422 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
2424 del_timer_sync(&uhci
->stall_timer
);
2427 * At this point, we're guaranteed that no new connects can be made
2428 * to this bus since there are no more parents
2430 uhci_free_pending_qhs(uhci
);
2431 uhci_remove_pending_qhs(uhci
);
2435 uhci_free_pending_qhs(uhci
);
2441 static int uhci_suspend(struct usb_hcd
*hcd
, u32 state
)
2443 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
2445 /* Don't try to suspend broken motherboards, reset instead */
2446 if (suspend_allowed(uhci
))
2453 static int uhci_resume(struct usb_hcd
*hcd
)
2455 struct uhci_hcd
*uhci
= hcd_to_uhci(hcd
);
2457 pci_set_master(uhci
->hcd
.pdev
);
2459 if (uhci
->state
== UHCI_SUSPENDED
)
2460 uhci
->resume_detect
= 1;
2465 uhci
->hcd
.state
= USB_STATE_READY
;
2470 static struct usb_hcd
*uhci_hcd_alloc(void)
2472 struct uhci_hcd
*uhci
;
2474 uhci
= (struct uhci_hcd
*)kmalloc(sizeof(*uhci
), GFP_KERNEL
);
2478 memset(uhci
, 0, sizeof(*uhci
));
2482 static void uhci_hcd_free(struct usb_hcd
*hcd
)
2484 kfree(hcd_to_uhci(hcd
));
2487 static int uhci_hcd_get_frame_number(struct usb_hcd
*hcd
)
2489 return uhci_get_current_frame_number(hcd_to_uhci(hcd
));
2492 static const char hcd_name
[] = "uhci-hcd";
2494 static struct hc_driver uhci_driver
= {
2495 .description
= hcd_name
,
2497 /* Generic hardware linkage */
2501 /* Basic lifecycle operations */
2502 .start
= uhci_start
,
2504 .suspend
= uhci_suspend
,
2505 .resume
= uhci_resume
,
2509 .hcd_alloc
= uhci_hcd_alloc
,
2510 .hcd_free
= uhci_hcd_free
,
2512 .urb_enqueue
= uhci_urb_enqueue
,
2513 .urb_dequeue
= uhci_urb_dequeue
,
2515 .get_frame_number
= uhci_hcd_get_frame_number
,
2517 .hub_status_data
= uhci_hub_status_data
,
2518 .hub_control
= uhci_hub_control
,
2521 const struct pci_device_id __devinitdata uhci_pci_ids
[] = { {
2523 /* handle any USB UHCI controller */
2524 .class = ((PCI_CLASS_SERIAL_USB
<< 8) | 0x00),
2526 .driver_data
= (unsigned long) &uhci_driver
,
2528 /* no matter who makes it */
2529 .vendor
= PCI_ANY_ID
,
2530 .device
= PCI_ANY_ID
,
2531 .subvendor
= PCI_ANY_ID
,
2532 .subdevice
= PCI_ANY_ID
,
2534 }, { /* end: all zeroes */ }
2537 MODULE_DEVICE_TABLE(pci
, uhci_pci_ids
);
2539 struct pci_driver uhci_pci_driver
= {
2540 .name
= (char *)hcd_name
,
2541 .id_table
= uhci_pci_ids
,
2543 .probe
= usb_hcd_pci_probe
,
2544 .remove
= usb_hcd_pci_remove
,
2547 .suspend
= usb_hcd_pci_suspend
,
2548 .resume
= usb_hcd_pci_resume
,
2552 int __init
uhci_hcd_init(void)
2554 int retval
= -ENOMEM
;
2556 info(DRIVER_DESC
" " DRIVER_VERSION
);
2562 errbuf
= kmalloc(ERRBUF_LEN
, GFP_KERNEL
);
2567 #ifdef CONFIG_PROC_FS
2568 uhci_proc_root
= create_proc_entry("driver/uhci", S_IFDIR
, 0);
2569 if (!uhci_proc_root
)
2573 uhci_up_cachep
= kmem_cache_create("uhci_urb_priv",
2574 sizeof(struct urb_priv
), 0, 0, NULL
, NULL
);
2575 if (!uhci_up_cachep
)
2578 retval
= pci_module_init(&uhci_pci_driver
);
2585 if (kmem_cache_destroy(uhci_up_cachep
))
2586 printk(KERN_INFO
"uhci: not all urb_priv's were freed\n");
2590 #ifdef CONFIG_PROC_FS
2591 remove_proc_entry("driver/uhci", 0);
2603 void __exit
uhci_hcd_cleanup(void)
2605 pci_unregister_driver(&uhci_pci_driver
);
2607 if (kmem_cache_destroy(uhci_up_cachep
))
2608 printk(KERN_INFO
"uhci: not all urb_priv's were freed\n");
2610 #ifdef CONFIG_PROC_FS
2611 remove_proc_entry("driver/uhci", 0);
2618 /*module_init(uhci_hcd_init);*/
2619 module_exit(uhci_hcd_cleanup
);
2621 MODULE_AUTHOR(DRIVER_AUTHOR
);
2622 MODULE_DESCRIPTION(DRIVER_DESC
);
2623 MODULE_LICENSE("GPL");