Fix build, by correcting include paths and updating xml files of USB components
[reactos.git] / reactos / drivers / usb / miniport / usbuhci / uhci-hcd.c
1 /*
2 * Universal Host Controller Interface driver for USB.
3 *
4 * Maintainer: Johannes Erdfelt <johannes@erdfelt.com>
5 *
6 * (C) Copyright 1999 Linus Torvalds
7 * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
8 * (C) Copyright 1999 Randy Dunlap
9 * (C) Copyright 1999 Georg Acher, acher@in.tum.de
10 * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
11 * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
12 * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
13 * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
14 * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
15 * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
16 *
17 * Intel documents this fairly well, and as far as I know there
18 * are no royalties or anything like that, but even so there are
19 * people who decided that they want to do the same thing in a
20 * completely different way.
21 *
22 * WARNING! The USB documentation is downright evil. Most of it
23 * is just crap, written by a committee. You're better off ignoring
24 * most of it, the important stuff is:
25 * - the low-level protocol (fairly simple but lots of small details)
26 * - working around the horridness of the rest
27 */
28
29 #if 0
30 #include <linux/config.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/kernel.h>
34 #include <linux/init.h>
35 #include <linux/delay.h>
36 #include <linux/ioport.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/smp_lock.h>
40 #include <linux/errno.h>
41 #include <linux/unistd.h>
42 #include <linux/interrupt.h>
43 #include <linux/spinlock.h>
44 #include <linux/proc_fs.h>
45 #endif
46
47 //#ifdef CONFIG_USB_DEBUG
48 #define DEBUG
49 //#else
50 //#undef DEBUG
51 //#endif
52
53 #if 0
54 #include <linux/usb.h>
55
56 #include <asm/uaccess.h>
57 #include <asm/io.h>
58 #include <asm/irq.h>
59 #include <asm/system.h>
60 #endif
61
62 #include "uhci_config.h"
63 #include "../usb_wrapper.h"
64 #include "hcd.h"
65 #include "uhci-hcd.h"
66
67 #if 0
68 #include <linux/pm.h>
69 #endif
70
71 /*
72 * Version Information
73 */
74 #define DRIVER_VERSION "v2.1"
75 #define DRIVER_AUTHOR "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber"
76 #define DRIVER_DESC "USB Universal Host Controller Interface driver"
77
78 /*
79 * debug = 0, no debugging messages
80 * debug = 1, dump failed URB's except for stalls
81 * debug = 2, dump all failed URB's (including stalls)
82 * show all queues in /proc/driver/uhci/[pci_addr]
83 * debug = 3, show all TD's in URB's when dumping
84 */
85 #ifdef DEBUG
86 static int debug = 3;
87 #else
88 static int debug = 2;
89 #endif
90 MODULE_PARM(debug, "i");
91 MODULE_PARM_DESC(debug, "Debug level");
92 static char *errbuf;
93 #define ERRBUF_LEN (PAGE_SIZE * 8)
94
95 #include "uhci-hub.c"
96 #include "uhci-debug.c"
97
98 static kmem_cache_t *uhci_up_cachep; /* urb_priv */
99
100 static int uhci_get_current_frame_number(struct uhci_hcd *uhci);
101 static int uhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb);
102 static void uhci_unlink_generic(struct uhci_hcd *uhci, struct urb *urb);
103
104 static void hc_state_transitions(struct uhci_hcd *uhci);
105
106 /* If a transfer is still active after this much time, turn off FSBR */
107 #define IDLE_TIMEOUT (HZ / 20) /* 50 ms */
108 #define FSBR_DELAY (HZ / 20) /* 50 ms */
109
110 /* When we timeout an idle transfer for FSBR, we'll switch it over to */
111 /* depth first traversal. We'll do it in groups of this number of TD's */
112 /* to make sure it doesn't hog all of the bandwidth */
113 #define DEPTH_INTERVAL 5
114
115 /*
116 * Technically, updating td->status here is a race, but it's not really a
117 * problem. The worst that can happen is that we set the IOC bit again
118 * generating a spurious interrupt. We could fix this by creating another
119 * QH and leaving the IOC bit always set, but then we would have to play
120 * games with the FSBR code to make sure we get the correct order in all
121 * the cases. I don't think it's worth the effort
122 */
123 static inline void uhci_set_next_interrupt(struct uhci_hcd *uhci)
124 {
125 unsigned long flags;
126
127 spin_lock_irqsave(&uhci->frame_list_lock, flags);
128 uhci->term_td->status |= cpu_to_le32(TD_CTRL_IOC);
129 spin_unlock_irqrestore(&uhci->frame_list_lock, flags);
130 }
131
132 static inline void uhci_clear_next_interrupt(struct uhci_hcd *uhci)
133 {
134 unsigned long flags;
135
136 spin_lock_irqsave(&uhci->frame_list_lock, flags);
137 uhci->term_td->status &= ~cpu_to_le32(TD_CTRL_IOC);
138 spin_unlock_irqrestore(&uhci->frame_list_lock, flags);
139 }
140
141 static inline void uhci_add_complete(struct uhci_hcd *uhci, struct urb *urb)
142 {
143 struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
144 unsigned long flags;
145
146 spin_lock_irqsave(&uhci->complete_list_lock, flags);
147 list_add_tail(&urbp->complete_list, &uhci->complete_list);
148 spin_unlock_irqrestore(&uhci->complete_list_lock, flags);
149 }
150
151 static struct uhci_td *uhci_alloc_td(struct uhci_hcd *uhci, struct usb_device *dev)
152 {
153 dma_addr_t dma_handle;
154 struct uhci_td *td;
155
156 td = pci_pool_alloc(uhci->td_pool, GFP_ATOMIC, &dma_handle);
157 if (!td)
158 return NULL;
159
160 td->dma_handle = dma_handle;
161
162 td->link = UHCI_PTR_TERM;
163 td->buffer = 0;
164
165 td->frame = -1;
166 td->dev = dev;
167
168 INIT_LIST_HEAD(&td->list);
169 INIT_LIST_HEAD(&td->fl_list);
170
171 usb_get_dev(dev);
172
173 return td;
174 }
175
176 static inline void uhci_fill_td(struct uhci_td *td, __u32 status,
177 __u32 token, __u32 buffer)
178 {
179 td->status = cpu_to_le32(status);
180 td->token = cpu_to_le32(token);
181 td->buffer = cpu_to_le32(buffer);
182 }
183
184 /*
185 * We insert Isochronous URB's directly into the frame list at the beginning
186 */
187 static void uhci_insert_td_frame_list(struct uhci_hcd *uhci, struct uhci_td *td, unsigned framenum)
188 {
189 unsigned long flags;
190
191 framenum %= UHCI_NUMFRAMES;
192
193 spin_lock_irqsave(&uhci->frame_list_lock, flags);
194
195 td->frame = framenum;
196
197 /* Is there a TD already mapped there? */
198 if (uhci->fl->frame_cpu[framenum]) {
199 struct uhci_td *ftd, *ltd;
200
201 ftd = uhci->fl->frame_cpu[framenum];
202 ltd = list_entry(ftd->fl_list.prev, struct uhci_td, fl_list);
203
204 list_add_tail(&td->fl_list, &ftd->fl_list);
205
206 td->link = ltd->link;
207 mb();
208 ltd->link = cpu_to_le32(td->dma_handle);
209 } else {
210 td->link = uhci->fl->frame[framenum];
211 mb();
212 uhci->fl->frame[framenum] = cpu_to_le32(td->dma_handle);
213 uhci->fl->frame_cpu[framenum] = td;
214 }
215
216 spin_unlock_irqrestore(&uhci->frame_list_lock, flags);
217 }
218
219 static void uhci_remove_td(struct uhci_hcd *uhci, struct uhci_td *td)
220 {
221 unsigned long flags;
222
223 /* If it's not inserted, don't remove it */
224 spin_lock_irqsave(&uhci->frame_list_lock, flags);
225 if (td->frame == -1 && list_empty(&td->fl_list))
226 goto out;
227
228 if (td->frame != -1 && uhci->fl->frame_cpu[td->frame] == td) {
229 if (list_empty(&td->fl_list)) {
230 uhci->fl->frame[td->frame] = td->link;
231 uhci->fl->frame_cpu[td->frame] = NULL;
232 } else {
233 struct uhci_td *ntd;
234
235 ntd = list_entry(td->fl_list.next, struct uhci_td, fl_list);
236 uhci->fl->frame[td->frame] = cpu_to_le32(ntd->dma_handle);
237 uhci->fl->frame_cpu[td->frame] = ntd;
238 }
239 } else {
240 struct uhci_td *ptd;
241
242 ptd = list_entry(td->fl_list.prev, struct uhci_td, fl_list);
243 ptd->link = td->link;
244 }
245
246 mb();
247 td->link = UHCI_PTR_TERM;
248
249 list_del_init(&td->fl_list);
250 td->frame = -1;
251
252 out:
253 spin_unlock_irqrestore(&uhci->frame_list_lock, flags);
254 }
255
256 /*
257 * Inserts a td into qh list at the top.
258 */
259 static void uhci_insert_tds_in_qh(struct uhci_qh *qh, struct urb *urb, u32 breadth)
260 {
261 struct list_head *tmp, *head;
262 struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
263 struct uhci_td *td, *ptd;
264
265 if (list_empty(&urbp->td_list))
266 return;
267
268 head = &urbp->td_list;
269 tmp = head->next;
270
271 /* Ordering isn't important here yet since the QH hasn't been */
272 /* inserted into the schedule yet */
273 td = list_entry(tmp, struct uhci_td, list);
274
275 /* Add the first TD to the QH element pointer */
276 qh->element = cpu_to_le32(td->dma_handle) | breadth;
277
278 ptd = td;
279
280 /* Then link the rest of the TD's */
281 tmp = tmp->next;
282 while (tmp != head) {
283 td = list_entry(tmp, struct uhci_td, list);
284
285 tmp = tmp->next;
286
287 ptd->link = cpu_to_le32(td->dma_handle) | breadth;
288
289 ptd = td;
290 }
291
292 ptd->link = UHCI_PTR_TERM;
293 }
294
295 static void uhci_free_td(struct uhci_hcd *uhci, struct uhci_td *td)
296 {
297 if (!list_empty(&td->list))
298 dbg("td %p is still in list!", td);
299 if (!list_empty(&td->fl_list))
300 dbg("td %p is still in fl_list!", td);
301
302 if (td->dev)
303 usb_put_dev(td->dev);
304
305 pci_pool_free(uhci->td_pool, td, td->dma_handle);
306 }
307
308 static struct uhci_qh *uhci_alloc_qh(struct uhci_hcd *uhci, struct usb_device *dev)
309 {
310 dma_addr_t dma_handle;
311 struct uhci_qh *qh;
312
313 qh = pci_pool_alloc(uhci->qh_pool, GFP_ATOMIC, &dma_handle);
314 if (!qh)
315 return NULL;
316
317 qh->dma_handle = dma_handle;
318
319 qh->element = UHCI_PTR_TERM;
320 qh->link = UHCI_PTR_TERM;
321
322 qh->dev = dev;
323 qh->urbp = NULL;
324
325 INIT_LIST_HEAD(&qh->list);
326 INIT_LIST_HEAD(&qh->remove_list);
327
328 usb_get_dev(dev);
329
330 return qh;
331 }
332
333 static void uhci_free_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
334 {
335 if (!list_empty(&qh->list))
336 dbg("qh %p list not empty!", qh);
337 if (!list_empty(&qh->remove_list))
338 dbg("qh %p still in remove_list!", qh);
339
340 if (qh->dev)
341 usb_put_dev(qh->dev);
342
343 pci_pool_free(uhci->qh_pool, qh, qh->dma_handle);
344 }
345
346 /*
347 * Append this urb's qh after the last qh in skelqh->list
348 * MUST be called with uhci->frame_list_lock acquired
349 *
350 * Note that urb_priv.queue_list doesn't have a separate queue head;
351 * it's a ring with every element "live".
352 */
353 static void _uhci_insert_qh(struct uhci_hcd *uhci, struct uhci_qh *skelqh, struct urb *urb)
354 {
355 struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
356 struct list_head *tmp;
357 struct uhci_qh *lqh;
358
359 /* Grab the last QH */
360 lqh = list_entry(skelqh->list.prev, struct uhci_qh, list);
361
362 /*
363 * Patch this endpoint's URB's QHs to point to the next skelqh:
364 * skelqh --> ... lqh --> newqh --> next skelqh
365 * Do this first, so the HC always sees the right QH after this one.
366 */
367 list_for_each (tmp, &urbp->queue_list) {
368 struct urb_priv *turbp =
369 list_entry(tmp, struct urb_priv, queue_list);
370
371 turbp->qh->link = lqh->link;
372 }
373 urbp->qh->link = lqh->link;
374 wmb(); /* Ordering is important */
375
376 /*
377 * Patch QHs for previous endpoint's queued URBs? HC goes
378 * here next, not to the next skelqh it now points to.
379 *
380 * lqh --> td ... --> qh ... --> td --> qh ... --> td
381 * | | |
382 * v v v
383 * +<----------------+-----------------+
384 * v
385 * newqh --> td ... --> td
386 * |
387 * v
388 * ...
389 *
390 * The HC could see (and use!) any of these as we write them.
391 */
392 if (lqh->urbp) {
393 list_for_each (tmp, &lqh->urbp->queue_list) {
394 struct urb_priv *turbp =
395 list_entry(tmp, struct urb_priv, queue_list);
396
397 turbp->qh->link = cpu_to_le32(urbp->qh->dma_handle) | UHCI_PTR_QH;
398 }
399 }
400 lqh->link = cpu_to_le32(urbp->qh->dma_handle) | UHCI_PTR_QH;
401
402 list_add_tail(&urbp->qh->list, &skelqh->list);
403 }
404
405 static void uhci_insert_qh(struct uhci_hcd *uhci, struct uhci_qh *skelqh, struct urb *urb)
406 {
407 unsigned long flags;
408
409 spin_lock_irqsave(&uhci->frame_list_lock, flags);
410 _uhci_insert_qh(uhci, skelqh, urb);
411 spin_unlock_irqrestore(&uhci->frame_list_lock, flags);
412 }
413
414 /*
415 * Start removal of QH from schedule; it finishes next frame.
416 * TDs should be unlinked before this is called.
417 */
418 static void uhci_remove_qh(struct uhci_hcd *uhci, struct uhci_qh *qh)
419 {
420 unsigned long flags;
421 struct uhci_qh *pqh;
422
423 if (!qh)
424 return;
425
426 qh->urbp = NULL;
427
428 /*
429 * Only go through the hoops if it's actually linked in
430 * Queued QHs are removed in uhci_delete_queued_urb,
431 * since (for queued URBs) the pqh is pointed to the next
432 * QH in the queue, not the next endpoint's QH.
433 */
434 spin_lock_irqsave(&uhci->frame_list_lock, flags);
435 if (!list_empty(&qh->list)) {
436 pqh = list_entry(qh->list.prev, struct uhci_qh, list);
437
438 if (pqh->urbp) {
439 struct list_head *head, *tmp;
440
441 head = &pqh->urbp->queue_list;
442 tmp = head->next;
443 while (head != tmp) {
444 struct urb_priv *turbp =
445 list_entry(tmp, struct urb_priv, queue_list);
446
447 tmp = tmp->next;
448
449 turbp->qh->link = qh->link;
450 }
451 }
452
453 pqh->link = qh->link;
454 mb();
455 /* Leave qh->link in case the HC is on the QH now, it will */
456 /* continue the rest of the schedule */
457 qh->element = UHCI_PTR_TERM;
458
459 list_del_init(&qh->list);
460 }
461 spin_unlock_irqrestore(&uhci->frame_list_lock, flags);
462
463 spin_lock_irqsave(&uhci->qh_remove_list_lock, flags);
464
465 /* Check to see if the remove list is empty. Set the IOC bit */
466 /* to force an interrupt so we can remove the QH */
467 if (list_empty(&uhci->qh_remove_list))
468 uhci_set_next_interrupt(uhci);
469
470 list_add(&qh->remove_list, &uhci->qh_remove_list);
471
472 spin_unlock_irqrestore(&uhci->qh_remove_list_lock, flags);
473 }
474
475 static int uhci_fixup_toggle(struct urb *urb, unsigned int toggle)
476 {
477 struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
478 struct list_head *head, *tmp;
479
480 head = &urbp->td_list;
481 tmp = head->next;
482 while (head != tmp) {
483 struct uhci_td *td = list_entry(tmp, struct uhci_td, list);
484
485 tmp = tmp->next;
486
487 if (toggle)
488 td->token |= cpu_to_le32(TD_TOKEN_TOGGLE);
489 else
490 td->token &= ~cpu_to_le32(TD_TOKEN_TOGGLE);
491
492
493 toggle ^= 1;
494 }
495
496 return toggle;
497 }
498
499 /* This function will append one URB's QH to another URB's QH. This is for */
500 /* queuing interrupt, control or bulk transfers */
501 static void uhci_append_queued_urb(struct uhci_hcd *uhci, struct urb *eurb, struct urb *urb)
502 {
503 struct urb_priv *eurbp, *urbp, *furbp, *lurbp;
504 struct list_head *tmp;
505 struct uhci_td *lltd;
506 unsigned long flags;
507
508 eurbp = eurb->hcpriv;
509 urbp = urb->hcpriv;
510
511 spin_lock_irqsave(&uhci->frame_list_lock, flags);
512
513 /* Find the first URB in the queue */
514 if (eurbp->queued) {
515 struct list_head *head = &eurbp->queue_list;
516
517 tmp = head->next;
518 while (tmp != head) {
519 struct urb_priv *turbp =
520 list_entry(tmp, struct urb_priv, queue_list);
521
522 if (!turbp->queued)
523 break;
524
525 tmp = tmp->next;
526 }
527 } else
528 tmp = &eurbp->queue_list;
529
530 furbp = list_entry(tmp, struct urb_priv, queue_list);
531 lurbp = list_entry(furbp->queue_list.prev, struct urb_priv, queue_list);
532
533 lltd = list_entry(lurbp->td_list.prev, struct uhci_td, list);
534
535 usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), usb_pipeout(urb->pipe),
536 uhci_fixup_toggle(urb, uhci_toggle(td_token(lltd)) ^ 1));
537
538 /* All qh's in the queue need to link to the next queue */
539 urbp->qh->link = eurbp->qh->link;
540
541 mb(); /* Make sure we flush everything */
542
543 lltd->link = cpu_to_le32(urbp->qh->dma_handle) | UHCI_PTR_QH;
544
545 list_add_tail(&urbp->queue_list, &furbp->queue_list);
546
547 urbp->queued = 1;
548
549 spin_unlock_irqrestore(&uhci->frame_list_lock, flags);
550 }
551
552 static void uhci_delete_queued_urb(struct uhci_hcd *uhci, struct urb *urb)
553 {
554 struct urb_priv *urbp, *nurbp;
555 struct list_head *head, *tmp;
556 struct urb_priv *purbp;
557 struct uhci_td *pltd;
558 unsigned int toggle;
559 unsigned long flags;
560
561 urbp = urb->hcpriv;
562
563 spin_lock_irqsave(&uhci->frame_list_lock, flags);
564
565 if (list_empty(&urbp->queue_list))
566 goto out;
567
568 nurbp = list_entry(urbp->queue_list.next, struct urb_priv, queue_list);
569
570 /* Fix up the toggle for the next URB's */
571 if (!urbp->queued)
572 /* We just set the toggle in uhci_unlink_generic */
573 toggle = usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe), usb_pipeout(urb->pipe));
574 else {
575 /* If we're in the middle of the queue, grab the toggle */
576 /* from the TD previous to us */
577 purbp = list_entry(urbp->queue_list.prev, struct urb_priv,
578 queue_list);
579
580 pltd = list_entry(purbp->td_list.prev, struct uhci_td, list);
581
582 toggle = uhci_toggle(td_token(pltd)) ^ 1;
583 }
584
585 head = &urbp->queue_list;
586 tmp = head->next;
587 while (head != tmp) {
588 struct urb_priv *turbp;
589
590 turbp = list_entry(tmp, struct urb_priv, queue_list);
591
592 tmp = tmp->next;
593
594 if (!turbp->queued)
595 break;
596
597 toggle = uhci_fixup_toggle(turbp->urb, toggle);
598 }
599
600 usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
601 usb_pipeout(urb->pipe), toggle);
602
603 if (!urbp->queued) {
604 struct uhci_qh *pqh;
605
606 nurbp->queued = 0;
607
608 /*
609 * Fixup the previous QH's queue to link to the new head
610 * of this queue.
611 */
612 pqh = list_entry(urbp->qh->list.prev, struct uhci_qh, list);
613
614 if (pqh->urbp) {
615 struct list_head *head, *tmp;
616
617 head = &pqh->urbp->queue_list;
618 tmp = head->next;
619 while (head != tmp) {
620 struct urb_priv *turbp =
621 list_entry(tmp, struct urb_priv, queue_list);
622
623 tmp = tmp->next;
624
625 turbp->qh->link = cpu_to_le32(nurbp->qh->dma_handle) | UHCI_PTR_QH;
626 }
627 }
628
629 pqh->link = cpu_to_le32(nurbp->qh->dma_handle) | UHCI_PTR_QH;
630
631 list_add_tail(&nurbp->qh->list, &urbp->qh->list);
632 list_del_init(&urbp->qh->list);
633 } else {
634 /* We're somewhere in the middle (or end). A bit trickier */
635 /* than the head scenario */
636 purbp = list_entry(urbp->queue_list.prev, struct urb_priv,
637 queue_list);
638
639 pltd = list_entry(purbp->td_list.prev, struct uhci_td, list);
640 if (nurbp->queued)
641 pltd->link = cpu_to_le32(nurbp->qh->dma_handle) | UHCI_PTR_QH;
642 else
643 /* The next URB happens to be the beginning, so */
644 /* we're the last, end the chain */
645 pltd->link = UHCI_PTR_TERM;
646 }
647
648 list_del_init(&urbp->queue_list);
649
650 out:
651 spin_unlock_irqrestore(&uhci->frame_list_lock, flags);
652 }
653
654 static struct urb_priv *uhci_alloc_urb_priv(struct uhci_hcd *uhci, struct urb *urb)
655 {
656 struct urb_priv *urbp;
657
658 urbp = kmem_cache_alloc(uhci_up_cachep, SLAB_ATOMIC);
659 if (!urbp) {
660 err("uhci_alloc_urb_priv: couldn't allocate memory for urb_priv\n");
661 return NULL;
662 }
663
664 memset((void *)urbp, 0, sizeof(*urbp));
665
666 urbp->inserttime = jiffies;
667 urbp->fsbrtime = jiffies;
668 urbp->urb = urb;
669 urbp->dev = urb->dev;
670
671 INIT_LIST_HEAD(&urbp->td_list);
672 INIT_LIST_HEAD(&urbp->queue_list);
673 INIT_LIST_HEAD(&urbp->complete_list);
674 INIT_LIST_HEAD(&urbp->urb_list);
675
676 list_add_tail(&urbp->urb_list, &uhci->urb_list);
677
678 urb->hcpriv = urbp;
679
680 return urbp;
681 }
682
683 /*
684 * MUST be called with urb->lock acquired
685 */
686 static void uhci_add_td_to_urb(struct urb *urb, struct uhci_td *td)
687 {
688 struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
689
690 td->urb = urb;
691
692 list_add_tail(&td->list, &urbp->td_list);
693 }
694
695 /*
696 * MUST be called with urb->lock acquired
697 */
698 static void uhci_remove_td_from_urb(struct uhci_td *td)
699 {
700 if (list_empty(&td->list))
701 return;
702
703 list_del_init(&td->list);
704
705 td->urb = NULL;
706 }
707
708 /*
709 * MUST be called with urb->lock acquired
710 */
711 static void uhci_destroy_urb_priv(struct uhci_hcd *uhci, struct urb *urb)
712 {
713 struct list_head *head, *tmp;
714 struct urb_priv *urbp;
715
716 urbp = (struct urb_priv *)urb->hcpriv;
717 if (!urbp)
718 return;
719
720 if (!list_empty(&urbp->urb_list))
721 warn("uhci_destroy_urb_priv: urb %p still on uhci->urb_list or uhci->remove_list", urb);
722
723 if (!list_empty(&urbp->complete_list))
724 warn("uhci_destroy_urb_priv: urb %p still on uhci->complete_list", urb);
725
726 head = &urbp->td_list;
727 tmp = head->next;
728 while (tmp != head) {
729 struct uhci_td *td = list_entry(tmp, struct uhci_td, list);
730
731 tmp = tmp->next;
732
733 uhci_remove_td_from_urb(td);
734 uhci_remove_td(uhci, td);
735 uhci_free_td(uhci, td);
736 }
737
738 urb->hcpriv = NULL;
739 kmem_cache_free(uhci_up_cachep, urbp);
740 }
741
742 static void uhci_inc_fsbr(struct uhci_hcd *uhci, struct urb *urb)
743 {
744 unsigned long flags;
745 struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
746
747 spin_lock_irqsave(&uhci->frame_list_lock, flags);
748
749 if ((!(urb->transfer_flags & URB_NO_FSBR)) && !urbp->fsbr) {
750 urbp->fsbr = 1;
751 if (!uhci->fsbr++ && !uhci->fsbrtimeout)
752 uhci->skel_term_qh->link = cpu_to_le32(uhci->skel_hs_control_qh->dma_handle) | UHCI_PTR_QH;
753 }
754
755 spin_unlock_irqrestore(&uhci->frame_list_lock, flags);
756 }
757
758 static void uhci_dec_fsbr(struct uhci_hcd *uhci, struct urb *urb)
759 {
760 unsigned long flags;
761 struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
762
763 spin_lock_irqsave(&uhci->frame_list_lock, flags);
764
765 if ((!(urb->transfer_flags & URB_NO_FSBR)) && urbp->fsbr) {
766 urbp->fsbr = 0;
767 if (!--uhci->fsbr)
768 uhci->fsbrtimeout = jiffies + FSBR_DELAY;
769 }
770
771 spin_unlock_irqrestore(&uhci->frame_list_lock, flags);
772 }
773
774 /*
775 * Map status to standard result codes
776 *
777 * <status> is (td->status & 0xFE0000) [a.k.a. uhci_status_bits(td->status)]
778 * <dir_out> is True for output TDs and False for input TDs.
779 */
780 static int uhci_map_status(int status, int dir_out)
781 {
782 if (!status)
783 return 0;
784 if (status & TD_CTRL_BITSTUFF) /* Bitstuff error */
785 return -EPROTO;
786 if (status & TD_CTRL_CRCTIMEO) { /* CRC/Timeout */
787 if (dir_out)
788 return -ETIMEDOUT;
789 else
790 return -EILSEQ;
791 }
792 if (status & TD_CTRL_NAK) /* NAK */
793 return -ETIMEDOUT;
794 if (status & TD_CTRL_BABBLE) /* Babble */
795 return -EOVERFLOW;
796 if (status & TD_CTRL_DBUFERR) /* Buffer error */
797 return -ENOSR;
798 if (status & TD_CTRL_STALLED) /* Stalled */
799 return -EPIPE;
800 if (status & TD_CTRL_ACTIVE) /* Active */
801 return 0;
802
803 return -EINVAL;
804 }
805
806 /*
807 * Control transfers
808 */
809 static int uhci_submit_control(struct uhci_hcd *uhci, struct urb *urb, struct urb *eurb)
810 {
811 struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
812 struct uhci_td *td;
813 struct uhci_qh *qh, *skelqh;
814 unsigned long destination, status;
815 int maxsze = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
816 int len = urb->transfer_buffer_length;
817 dma_addr_t data = urb->transfer_dma;
818
819 /* The "pipe" thing contains the destination in bits 8--18 */
820 destination = (urb->pipe & PIPE_DEVEP_MASK) | USB_PID_SETUP;
821
822 /* 3 errors */
823 status = TD_CTRL_ACTIVE | uhci_maxerr(3);
824 if (urb->dev->speed == USB_SPEED_LOW)
825 status |= TD_CTRL_LS;
826
827 /*
828 * Build the TD for the control request
829 */
830 td = uhci_alloc_td(uhci, urb->dev);
831 if (!td)
832 return -ENOMEM;
833
834 uhci_add_td_to_urb(urb, td);
835 uhci_fill_td(td, status, destination | uhci_explen(7),
836 urb->setup_dma);
837
838 /*
839 * If direction is "send", change the frame from SETUP (0x2D)
840 * to OUT (0xE1). Else change it from SETUP to IN (0x69).
841 */
842 destination ^= (USB_PID_SETUP ^ usb_packetid(urb->pipe));
843
844 if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
845 status |= TD_CTRL_SPD;
846
847 /*
848 * Build the DATA TD's
849 */
850 while (len > 0) {
851 int pktsze = len;
852
853 if (pktsze > maxsze)
854 pktsze = maxsze;
855
856 td = uhci_alloc_td(uhci, urb->dev);
857 if (!td)
858 return -ENOMEM;
859
860 /* Alternate Data0/1 (start with Data1) */
861 destination ^= TD_TOKEN_TOGGLE;
862
863 uhci_add_td_to_urb(urb, td);
864 uhci_fill_td(td, status, destination | uhci_explen(pktsze - 1),
865 data);
866
867 data += pktsze;
868 len -= pktsze;
869 }
870
871 /*
872 * Build the final TD for control status
873 */
874 td = uhci_alloc_td(uhci, urb->dev);
875 if (!td)
876 return -ENOMEM;
877
878 /*
879 * It's IN if the pipe is an output pipe or we're not expecting
880 * data back.
881 */
882 destination &= ~TD_TOKEN_PID_MASK;
883 if (usb_pipeout(urb->pipe) || !urb->transfer_buffer_length)
884 destination |= USB_PID_IN;
885 else
886 destination |= USB_PID_OUT;
887
888 destination |= TD_TOKEN_TOGGLE; /* End in Data1 */
889
890 status &= ~TD_CTRL_SPD;
891
892 uhci_add_td_to_urb(urb, td);
893 uhci_fill_td(td, status | TD_CTRL_IOC,
894 destination | uhci_explen(UHCI_NULL_DATA_SIZE), 0);
895
896 qh = uhci_alloc_qh(uhci, urb->dev);
897 if (!qh)
898 return -ENOMEM;
899
900 urbp->qh = qh;
901 qh->urbp = urbp;
902
903 uhci_insert_tds_in_qh(qh, urb, UHCI_PTR_BREADTH);
904
905 /* Low speed transfers get a different queue, and won't hog the bus */
906 if (urb->dev->speed == USB_SPEED_LOW)
907 skelqh = uhci->skel_ls_control_qh;
908 else {
909 skelqh = uhci->skel_hs_control_qh;
910 uhci_inc_fsbr(uhci, urb);
911 }
912
913 if (eurb)
914 uhci_append_queued_urb(uhci, eurb, urb);
915 else
916 uhci_insert_qh(uhci, skelqh, urb);
917
918 return -EINPROGRESS;
919 }
920
921 /*
922 * If control was short, then end status packet wasn't sent, so this
923 * reorganize s so it's sent to finish the transfer. The original QH is
924 * removed from the skel and discarded; all TDs except the last (status)
925 * are deleted; the last (status) TD is put on a new QH which is reinserted
926 * into the skel. Since the last TD and urb_priv are reused, the TD->link
927 * and urb_priv maintain any queued QHs.
928 */
929 static int usb_control_retrigger_status(struct uhci_hcd *uhci, struct urb *urb)
930 {
931 struct list_head *tmp, *head;
932 struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
933
934 urbp->short_control_packet = 1;
935
936 /* Create a new QH to avoid pointer overwriting problems */
937 uhci_remove_qh(uhci, urbp->qh);
938
939 /* Delete all of the TD's except for the status TD at the end */
940 head = &urbp->td_list;
941 tmp = head->next;
942 while (tmp != head && tmp->next != head) {
943 struct uhci_td *td = list_entry(tmp, struct uhci_td, list);
944
945 tmp = tmp->next;
946
947 uhci_remove_td_from_urb(td);
948 uhci_remove_td(uhci, td);
949 uhci_free_td(uhci, td);
950 }
951
952 urbp->qh = uhci_alloc_qh(uhci, urb->dev);
953 if (!urbp->qh) {
954 err("unable to allocate new QH for control retrigger");
955 return -ENOMEM;
956 }
957
958 urbp->qh->urbp = urbp;
959
960 /* One TD, who cares about Breadth first? */
961 uhci_insert_tds_in_qh(urbp->qh, urb, UHCI_PTR_DEPTH);
962
963 /* Low speed transfers get a different queue */
964 if (urb->dev->speed == USB_SPEED_LOW)
965 uhci_insert_qh(uhci, uhci->skel_ls_control_qh, urb);
966 else
967 uhci_insert_qh(uhci, uhci->skel_hs_control_qh, urb);
968
969 return -EINPROGRESS;
970 }
971
972
973 static int uhci_result_control(struct uhci_hcd *uhci, struct urb *urb)
974 {
975 struct list_head *tmp, *head;
976 struct urb_priv *urbp = urb->hcpriv;
977 struct uhci_td *td;
978 unsigned int status;
979 int ret = 0;
980
981 if (list_empty(&urbp->td_list))
982 return -EINVAL;
983
984 head = &urbp->td_list;
985
986 if (urbp->short_control_packet) {
987 tmp = head->prev;
988 goto status_phase;
989 }
990
991 tmp = head->next;
992 td = list_entry(tmp, struct uhci_td, list);
993
994 /* The first TD is the SETUP phase, check the status, but skip */
995 /* the count */
996 status = uhci_status_bits(td_status(td));
997 if (status & TD_CTRL_ACTIVE)
998 return -EINPROGRESS;
999
1000 if (status)
1001 goto td_error;
1002
1003 urb->actual_length = 0;
1004
1005 /* The rest of the TD's (but the last) are data */
1006 tmp = tmp->next;
1007 while (tmp != head && tmp->next != head) {
1008 td = list_entry(tmp, struct uhci_td, list);
1009
1010 tmp = tmp->next;
1011
1012 status = uhci_status_bits(td_status(td));
1013 if (status & TD_CTRL_ACTIVE)
1014 return -EINPROGRESS;
1015
1016 urb->actual_length += uhci_actual_length(td_status(td));
1017
1018 if (status)
1019 goto td_error;
1020
1021 /* Check to see if we received a short packet */
1022 if (uhci_actual_length(td_status(td)) < uhci_expected_length(td_token(td))) {
1023 if (urb->transfer_flags & URB_SHORT_NOT_OK) {
1024 ret = -EREMOTEIO;
1025 goto err;
1026 }
1027
1028 if (uhci_packetid(td_token(td)) == USB_PID_IN)
1029 return usb_control_retrigger_status(uhci, urb);
1030 else
1031 return 0;
1032 }
1033 }
1034
1035 status_phase:
1036 td = list_entry(tmp, struct uhci_td, list);
1037
1038 /* Control status phase */
1039 status = td_status(td);
1040
1041 #ifdef I_HAVE_BUGGY_APC_BACKUPS
1042 /* APC BackUPS Pro kludge */
1043 /* It tries to send all of the descriptor instead of the amount */
1044 /* we requested */
1045 if (status & TD_CTRL_IOC && /* IOC is masked out by uhci_status_bits */
1046 status & TD_CTRL_ACTIVE &&
1047 status & TD_CTRL_NAK)
1048 return 0;
1049 #endif
1050
1051 if (status & TD_CTRL_ACTIVE)
1052 return -EINPROGRESS;
1053
1054 if (uhci_status_bits(status))
1055 goto td_error;
1056
1057 return 0;
1058
1059 td_error:
1060 ret = uhci_map_status(status, uhci_packetout(td_token(td)));
1061
1062 err:
1063 if ((debug == 1 && ret != -EPIPE) || debug > 1) {
1064 /* Some debugging code */
1065 dbg("uhci_result_control() failed with status %x", status);
1066
1067 if (errbuf) {
1068 /* Print the chain for debugging purposes */
1069 uhci_show_qh(urbp->qh, errbuf, ERRBUF_LEN, 0);
1070
1071 lprintk(errbuf);
1072 }
1073 }
1074
1075 return ret;
1076 }
1077
1078 /*
1079 * Common submit for bulk and interrupt
1080 */
1081 static int uhci_submit_common(struct uhci_hcd *uhci, struct urb *urb, struct urb *eurb, struct uhci_qh *skelqh)
1082 {
1083 struct uhci_td *td;
1084 struct uhci_qh *qh;
1085 unsigned long destination, status;
1086 int maxsze = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
1087 int len = urb->transfer_buffer_length;
1088 struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
1089 dma_addr_t data = urb->transfer_dma;
1090
1091 if (len < 0)
1092 return -EINVAL;
1093
1094 /* The "pipe" thing contains the destination in bits 8--18 */
1095 destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);
1096
1097 status = uhci_maxerr(3) | TD_CTRL_ACTIVE;
1098 if (urb->dev->speed == USB_SPEED_LOW)
1099 status |= TD_CTRL_LS;
1100 if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
1101 status |= TD_CTRL_SPD;
1102
1103 /*
1104 * Build the DATA TD's
1105 */
1106 do { /* Allow zero length packets */
1107 int pktsze = len;
1108
1109 if (pktsze > maxsze)
1110 pktsze = maxsze;
1111
1112 td = uhci_alloc_td(uhci, urb->dev);
1113 if (!td)
1114 return -ENOMEM;
1115
1116 uhci_add_td_to_urb(urb, td);
1117 uhci_fill_td(td, status, destination | uhci_explen(pktsze - 1) |
1118 (usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe),
1119 usb_pipeout(urb->pipe)) << TD_TOKEN_TOGGLE_SHIFT),
1120 data);
1121
1122 data += pktsze;
1123 len -= maxsze;
1124
1125 usb_dotoggle(urb->dev, usb_pipeendpoint(urb->pipe),
1126 usb_pipeout(urb->pipe));
1127 } while (len > 0);
1128
1129 /*
1130 * URB_ZERO_PACKET means adding a 0-length packet, if direction
1131 * is OUT and the transfer_length was an exact multiple of maxsze,
1132 * hence (len = transfer_length - N * maxsze) == 0
1133 * however, if transfer_length == 0, the zero packet was already
1134 * prepared above.
1135 */
1136 if (usb_pipeout(urb->pipe) && (urb->transfer_flags & URB_ZERO_PACKET) &&
1137 !len && urb->transfer_buffer_length) {
1138 td = uhci_alloc_td(uhci, urb->dev);
1139 if (!td)
1140 return -ENOMEM;
1141
1142 uhci_add_td_to_urb(urb, td);
1143 uhci_fill_td(td, status, destination | uhci_explen(UHCI_NULL_DATA_SIZE) |
1144 (usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe),
1145 usb_pipeout(urb->pipe)) << TD_TOKEN_TOGGLE_SHIFT),
1146 data);
1147
1148 usb_dotoggle(urb->dev, usb_pipeendpoint(urb->pipe),
1149 usb_pipeout(urb->pipe));
1150 }
1151
1152 /* Set the flag on the last packet */
1153 td->status |= cpu_to_le32(TD_CTRL_IOC);
1154
1155 qh = uhci_alloc_qh(uhci, urb->dev);
1156 if (!qh)
1157 return -ENOMEM;
1158
1159 urbp->qh = qh;
1160 qh->urbp = urbp;
1161
1162 /* Always breadth first */
1163 uhci_insert_tds_in_qh(qh, urb, UHCI_PTR_BREADTH);
1164
1165 if (eurb)
1166 uhci_append_queued_urb(uhci, eurb, urb);
1167 else
1168 uhci_insert_qh(uhci, skelqh, urb);
1169
1170 return -EINPROGRESS;
1171 }
1172
1173 /*
1174 * Common result for bulk and interrupt
1175 */
1176 static int uhci_result_common(struct uhci_hcd *uhci, struct urb *urb)
1177 {
1178 struct list_head *tmp, *head;
1179 struct urb_priv *urbp = urb->hcpriv;
1180 struct uhci_td *td;
1181 unsigned int status = 0;
1182 int ret = 0;
1183
1184 urb->actual_length = 0;
1185
1186 head = &urbp->td_list;
1187 tmp = head->next;
1188 while (tmp != head) {
1189 td = list_entry(tmp, struct uhci_td, list);
1190
1191 tmp = tmp->next;
1192
1193 status = uhci_status_bits(td_status(td));
1194 if (status & TD_CTRL_ACTIVE)
1195 return -EINPROGRESS;
1196
1197 urb->actual_length += uhci_actual_length(td_status(td));
1198
1199 if (status)
1200 goto td_error;
1201
1202 if (uhci_actual_length(td_status(td)) < uhci_expected_length(td_token(td))) {
1203 if (urb->transfer_flags & URB_SHORT_NOT_OK) {
1204 ret = -EREMOTEIO;
1205 goto err;
1206 } else
1207 return 0;
1208 }
1209 }
1210
1211 return 0;
1212
1213 td_error:
1214 ret = uhci_map_status(status, uhci_packetout(td_token(td)));
1215 if (ret == -EPIPE)
1216 /* endpoint has stalled - mark it halted */
1217 usb_endpoint_halt(urb->dev, uhci_endpoint(td_token(td)),
1218 uhci_packetout(td_token(td)));
1219
1220 err:
1221 /*
1222 * Enable this chunk of code if you want to see some more debugging.
1223 * But be careful, it has the tendancy to starve out khubd and prevent
1224 * disconnects from happening successfully if you have a slow debug
1225 * log interface (like a serial console.
1226 */
1227 #if 0
1228 if ((debug == 1 && ret != -EPIPE) || debug > 1) {
1229 /* Some debugging code */
1230 dbg("uhci_result_common() failed with status %x", status);
1231
1232 if (errbuf) {
1233 /* Print the chain for debugging purposes */
1234 uhci_show_qh(urbp->qh, errbuf, ERRBUF_LEN, 0);
1235
1236 lprintk(errbuf);
1237 }
1238 }
1239 #endif
1240 return ret;
1241 }
1242
1243 static inline int uhci_submit_bulk(struct uhci_hcd *uhci, struct urb *urb, struct urb *eurb)
1244 {
1245 int ret;
1246
1247 /* Can't have low speed bulk transfers */
1248 if (urb->dev->speed == USB_SPEED_LOW)
1249 return -EINVAL;
1250
1251 ret = uhci_submit_common(uhci, urb, eurb, uhci->skel_bulk_qh);
1252 if (ret == -EINPROGRESS)
1253 uhci_inc_fsbr(uhci, urb);
1254
1255 return ret;
1256 }
1257
1258 static inline int uhci_submit_interrupt(struct uhci_hcd *uhci, struct urb *urb, struct urb *eurb)
1259 {
1260 /* USB 1.1 interrupt transfers only involve one packet per interval;
1261 * that's the uhci_submit_common() "breadth first" policy. Drivers
1262 * can submit urbs of any length, but longer ones might need many
1263 * intervals to complete.
1264 */
1265 return uhci_submit_common(uhci, urb, eurb, uhci->skelqh[__interval_to_skel(urb->interval)]);
1266 }
1267
1268 /*
1269 * Bulk and interrupt use common result
1270 */
1271 #define uhci_result_bulk uhci_result_common
1272 #define uhci_result_interrupt uhci_result_common
1273
1274 /*
1275 * Isochronous transfers
1276 */
1277 static int isochronous_find_limits(struct uhci_hcd *uhci, struct urb *urb, unsigned int *start, unsigned int *end)
1278 {
1279 struct urb *last_urb = NULL;
1280 struct list_head *tmp, *head;
1281 int ret = 0;
1282
1283 head = &uhci->urb_list;
1284 tmp = head->next;
1285 while (tmp != head) {
1286 struct urb_priv *up = list_entry(tmp, struct urb_priv, urb_list);
1287 struct urb *u = up->urb;
1288
1289 tmp = tmp->next;
1290
1291 /* look for pending URB's with identical pipe handle */
1292 if ((urb->pipe == u->pipe) && (urb->dev == u->dev) &&
1293 (u->status == -EINPROGRESS) && (u != urb)) {
1294 if (!last_urb)
1295 *start = u->start_frame;
1296 last_urb = u;
1297 }
1298 }
1299
1300 if (last_urb) {
1301 *end = (last_urb->start_frame + last_urb->number_of_packets *
1302 last_urb->interval) & (UHCI_NUMFRAMES-1);
1303 ret = 0;
1304 } else
1305 ret = -1; /* no previous urb found */
1306
1307 return ret;
1308 }
1309
1310 static int isochronous_find_start(struct uhci_hcd *uhci, struct urb *urb)
1311 {
1312 int limits;
1313 unsigned int start = 0, end = 0;
1314
1315 if (urb->number_of_packets > 900) /* 900? Why? */
1316 return -EFBIG;
1317
1318 limits = isochronous_find_limits(uhci, urb, &start, &end);
1319
1320 if (urb->transfer_flags & URB_ISO_ASAP) {
1321 if (limits) {
1322 int curframe;
1323
1324 curframe = uhci_get_current_frame_number(uhci) % UHCI_NUMFRAMES;
1325 urb->start_frame = (curframe + 10) % UHCI_NUMFRAMES;
1326 } else
1327 urb->start_frame = end;
1328 } else {
1329 urb->start_frame %= UHCI_NUMFRAMES;
1330 /* FIXME: Sanity check */
1331 }
1332
1333 return 0;
1334 }
1335
1336 /*
1337 * Isochronous transfers
1338 */
1339 static int uhci_submit_isochronous(struct uhci_hcd *uhci, struct urb *urb)
1340 {
1341 struct uhci_td *td;
1342 int i, ret, frame;
1343 int status, destination;
1344
1345 status = TD_CTRL_ACTIVE | TD_CTRL_IOS;
1346 destination = (urb->pipe & PIPE_DEVEP_MASK) | usb_packetid(urb->pipe);
1347
1348 ret = isochronous_find_start(uhci, urb);
1349 if (ret)
1350 return ret;
1351
1352 frame = urb->start_frame;
1353 for (i = 0; i < urb->number_of_packets; i++, frame += urb->interval) {
1354 if (!urb->iso_frame_desc[i].length)
1355 continue;
1356
1357 td = uhci_alloc_td(uhci, urb->dev);
1358 if (!td)
1359 return -ENOMEM;
1360
1361 uhci_add_td_to_urb(urb, td);
1362 uhci_fill_td(td, status, destination | uhci_explen(urb->iso_frame_desc[i].length - 1),
1363 urb->transfer_dma + urb->iso_frame_desc[i].offset);
1364
1365 if (i + 1 >= urb->number_of_packets)
1366 td->status |= cpu_to_le32(TD_CTRL_IOC);
1367
1368 uhci_insert_td_frame_list(uhci, td, frame);
1369 }
1370
1371 return -EINPROGRESS;
1372 }
1373
1374 static int uhci_result_isochronous(struct uhci_hcd *uhci, struct urb *urb)
1375 {
1376 struct list_head *tmp, *head;
1377 struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
1378 int status;
1379 int i, ret = 0;
1380
1381 urb->actual_length = 0;
1382
1383 i = 0;
1384 head = &urbp->td_list;
1385 tmp = head->next;
1386 while (tmp != head) {
1387 struct uhci_td *td = list_entry(tmp, struct uhci_td, list);
1388 int actlength;
1389
1390 tmp = tmp->next;
1391
1392 if (td_status(td) & TD_CTRL_ACTIVE)
1393 return -EINPROGRESS;
1394
1395 actlength = uhci_actual_length(td_status(td));
1396 urb->iso_frame_desc[i].actual_length = actlength;
1397 urb->actual_length += actlength;
1398
1399 status = uhci_map_status(uhci_status_bits(td_status(td)), usb_pipeout(urb->pipe));
1400 urb->iso_frame_desc[i].status = status;
1401 if (status) {
1402 urb->error_count++;
1403 ret = status;
1404 }
1405
1406 i++;
1407 }
1408
1409 return ret;
1410 }
1411
1412 /*
1413 * MUST be called with uhci->urb_list_lock acquired
1414 */
1415 static struct urb *uhci_find_urb_ep(struct uhci_hcd *uhci, struct urb *urb)
1416 {
1417 struct list_head *tmp, *head;
1418
1419 /* We don't match Isoc transfers since they are special */
1420 if (usb_pipeisoc(urb->pipe))
1421 return NULL;
1422
1423 head = &uhci->urb_list;
1424 tmp = head->next;
1425 while (tmp != head) {
1426 struct urb_priv *up = list_entry(tmp, struct urb_priv, urb_list);
1427 struct urb *u = up->urb;
1428
1429 tmp = tmp->next;
1430
1431 if (u->dev == urb->dev && u->status == -EINPROGRESS) {
1432 /* For control, ignore the direction */
1433 if (usb_pipecontrol(urb->pipe) &&
1434 (u->pipe & ~USB_DIR_IN) == (urb->pipe & ~USB_DIR_IN))
1435 return u;
1436 else if (u->pipe == urb->pipe)
1437 return u;
1438 }
1439 }
1440
1441 return NULL;
1442 }
1443
1444 static int uhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, int mem_flags)
1445 {
1446 int ret = -EINVAL;
1447 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
1448 unsigned long flags;
1449 struct urb *eurb;
1450 int bustime;
1451
1452 spin_lock_irqsave(&uhci->urb_list_lock, flags);
1453
1454 eurb = uhci_find_urb_ep(uhci, urb);
1455
1456 if (!uhci_alloc_urb_priv(uhci, urb)) {
1457 spin_unlock_irqrestore(&uhci->urb_list_lock, flags);
1458 return -ENOMEM;
1459 }
1460
1461 switch (usb_pipetype(urb->pipe)) {
1462 case PIPE_CONTROL:
1463 ret = uhci_submit_control(uhci, urb, eurb);
1464 break;
1465 case PIPE_INTERRUPT:
1466 if (!eurb) {
1467 bustime = usb_check_bandwidth(urb->dev, urb);
1468 if (bustime < 0)
1469 ret = bustime;
1470 else {
1471 ret = uhci_submit_interrupt(uhci, urb, eurb);
1472 if (ret == -EINPROGRESS)
1473 usb_claim_bandwidth(urb->dev, urb, bustime, 0);
1474 }
1475 } else { /* inherit from parent */
1476 urb->bandwidth = eurb->bandwidth;
1477 ret = uhci_submit_interrupt(uhci, urb, eurb);
1478 }
1479 break;
1480 case PIPE_BULK:
1481 ret = uhci_submit_bulk(uhci, urb, eurb);
1482 break;
1483 case PIPE_ISOCHRONOUS:
1484 bustime = usb_check_bandwidth(urb->dev, urb);
1485 if (bustime < 0) {
1486 ret = bustime;
1487 break;
1488 }
1489
1490 ret = uhci_submit_isochronous(uhci, urb);
1491 if (ret == -EINPROGRESS)
1492 usb_claim_bandwidth(urb->dev, urb, bustime, 1);
1493 break;
1494 }
1495
1496 if (ret != -EINPROGRESS) {
1497 /* Submit failed, so delete it from the urb_list */
1498 struct urb_priv *urbp = urb->hcpriv;
1499
1500 list_del_init(&urbp->urb_list);
1501 spin_unlock_irqrestore(&uhci->urb_list_lock, flags);
1502 uhci_destroy_urb_priv (uhci, urb);
1503
1504 return ret;
1505 }
1506
1507 spin_unlock_irqrestore(&uhci->urb_list_lock, flags);
1508
1509 return 0;
1510 }
1511
1512 /*
1513 * Return the result of a transfer
1514 *
1515 * MUST be called with urb_list_lock acquired
1516 */
1517 static void uhci_transfer_result(struct uhci_hcd *uhci, struct urb *urb)
1518 {
1519 int ret = -EINVAL;
1520 unsigned long flags;
1521 struct urb_priv *urbp;
1522
1523 spin_lock_irqsave(&urb->lock, flags);
1524
1525 urbp = (struct urb_priv *)urb->hcpriv;
1526
1527 if (urb->status != -EINPROGRESS) {
1528 info("uhci_transfer_result: called for URB %p not in flight?", urb);
1529 goto out;
1530 }
1531
1532 switch (usb_pipetype(urb->pipe)) {
1533 case PIPE_CONTROL:
1534 ret = uhci_result_control(uhci, urb);
1535 break;
1536 case PIPE_INTERRUPT:
1537 ret = uhci_result_interrupt(uhci, urb);
1538 break;
1539 case PIPE_BULK:
1540 ret = uhci_result_bulk(uhci, urb);
1541 break;
1542 case PIPE_ISOCHRONOUS:
1543 ret = uhci_result_isochronous(uhci, urb);
1544 break;
1545 }
1546
1547 urbp->status = ret;
1548
1549 if (ret == -EINPROGRESS)
1550 goto out;
1551
1552 switch (usb_pipetype(urb->pipe)) {
1553 case PIPE_CONTROL:
1554 case PIPE_BULK:
1555 case PIPE_ISOCHRONOUS:
1556 /* Release bandwidth for Interrupt or Isoc. transfers */
1557 /* Spinlock needed ? */
1558 if (urb->bandwidth)
1559 usb_release_bandwidth(urb->dev, urb, 1);
1560 uhci_unlink_generic(uhci, urb);
1561 break;
1562 case PIPE_INTERRUPT:
1563 /* Release bandwidth for Interrupt or Isoc. transfers */
1564 /* Make sure we don't release if we have a queued URB */
1565 spin_lock(&uhci->frame_list_lock);
1566 /* Spinlock needed ? */
1567 if (list_empty(&urbp->queue_list) && urb->bandwidth)
1568 usb_release_bandwidth(urb->dev, urb, 0);
1569 else
1570 /* bandwidth was passed on to queued URB, */
1571 /* so don't let usb_unlink_urb() release it */
1572 urb->bandwidth = 0;
1573 spin_unlock(&uhci->frame_list_lock);
1574 uhci_unlink_generic(uhci, urb);
1575 break;
1576 default:
1577 info("uhci_transfer_result: unknown pipe type %d for urb %p\n",
1578 usb_pipetype(urb->pipe), urb);
1579 }
1580
1581 /* Remove it from uhci->urb_list */
1582 list_del_init(&urbp->urb_list);
1583
1584 uhci_add_complete(uhci, urb);
1585
1586 out:
1587 spin_unlock_irqrestore(&urb->lock, flags);
1588 }
1589
1590 /*
1591 * MUST be called with urb->lock acquired
1592 */
1593 static void uhci_unlink_generic(struct uhci_hcd *uhci, struct urb *urb)
1594 {
1595 struct list_head *head, *tmp;
1596 struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
1597 int prevactive = 1;
1598
1599 /* We can get called when urbp allocation fails, so check */
1600 if (!urbp)
1601 return;
1602
1603 uhci_dec_fsbr(uhci, urb); /* Safe since it checks */
1604
1605 /*
1606 * Now we need to find out what the last successful toggle was
1607 * so we can update the local data toggle for the next transfer
1608 *
1609 * There's 3 way's the last successful completed TD is found:
1610 *
1611 * 1) The TD is NOT active and the actual length < expected length
1612 * 2) The TD is NOT active and it's the last TD in the chain
1613 * 3) The TD is active and the previous TD is NOT active
1614 *
1615 * Control and Isochronous ignore the toggle, so this is safe
1616 * for all types
1617 */
1618 head = &urbp->td_list;
1619 tmp = head->next;
1620 while (tmp != head) {
1621 struct uhci_td *td = list_entry(tmp, struct uhci_td, list);
1622
1623 tmp = tmp->next;
1624
1625 if (!(td_status(td) & TD_CTRL_ACTIVE) &&
1626 (uhci_actual_length(td_status(td)) < uhci_expected_length(td_token(td)) ||
1627 tmp == head))
1628 usb_settoggle(urb->dev, uhci_endpoint(td_token(td)),
1629 uhci_packetout(td_token(td)),
1630 uhci_toggle(td_token(td)) ^ 1);
1631 else if ((td_status(td) & TD_CTRL_ACTIVE) && !prevactive)
1632 usb_settoggle(urb->dev, uhci_endpoint(td_token(td)),
1633 uhci_packetout(td_token(td)),
1634 uhci_toggle(td_token(td)));
1635
1636 prevactive = td_status(td) & TD_CTRL_ACTIVE;
1637 }
1638
1639 uhci_delete_queued_urb(uhci, urb);
1640
1641 /* The interrupt loop will reclaim the QH's */
1642 uhci_remove_qh(uhci, urbp->qh);
1643 urbp->qh = NULL;
1644 }
1645
1646 static int uhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
1647 {
1648 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
1649 unsigned long flags;
1650 struct urb_priv *urbp = urb->hcpriv;
1651
1652 /* If this is an interrupt URB that is being killed in urb->complete, */
1653 /* then just set its status and return */
1654 if (!urbp) {
1655 urb->status = -ECONNRESET;
1656 return 0;
1657 }
1658
1659 spin_lock_irqsave(&uhci->urb_list_lock, flags);
1660
1661 list_del_init(&urbp->urb_list);
1662
1663 uhci_unlink_generic(uhci, urb);
1664
1665 spin_lock(&uhci->urb_remove_list_lock);
1666
1667 /* If we're the first, set the next interrupt bit */
1668 if (list_empty(&uhci->urb_remove_list))
1669 uhci_set_next_interrupt(uhci);
1670 list_add(&urbp->urb_list, &uhci->urb_remove_list);
1671
1672 spin_unlock(&uhci->urb_remove_list_lock);
1673 spin_unlock_irqrestore(&uhci->urb_list_lock, flags);
1674 return 0;
1675 }
1676
1677 static int uhci_fsbr_timeout(struct uhci_hcd *uhci, struct urb *urb)
1678 {
1679 struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
1680 struct list_head *head, *tmp;
1681 int count = 0;
1682
1683 uhci_dec_fsbr(uhci, urb);
1684
1685 urbp->fsbr_timeout = 1;
1686
1687 /*
1688 * Ideally we would want to fix qh->element as well, but it's
1689 * read/write by the HC, so that can introduce a race. It's not
1690 * really worth the hassle
1691 */
1692
1693 head = &urbp->td_list;
1694 tmp = head->next;
1695 while (tmp != head) {
1696 struct uhci_td *td = list_entry(tmp, struct uhci_td, list);
1697
1698 tmp = tmp->next;
1699
1700 /*
1701 * Make sure we don't do the last one (since it'll have the
1702 * TERM bit set) as well as we skip every so many TD's to
1703 * make sure it doesn't hog the bandwidth
1704 */
1705 if (tmp != head && (count % DEPTH_INTERVAL) == (DEPTH_INTERVAL - 1))
1706 td->link |= UHCI_PTR_DEPTH;
1707
1708 count++;
1709 }
1710
1711 return 0;
1712 }
1713
1714 /*
1715 * uhci_get_current_frame_number()
1716 *
1717 * returns the current frame number for a USB bus/controller.
1718 */
1719 static int uhci_get_current_frame_number(struct uhci_hcd *uhci)
1720 {
1721 return inw(uhci->io_addr + USBFRNUM);
1722 }
1723
1724 static int init_stall_timer(struct usb_hcd *hcd);
1725
1726 static void stall_callback(unsigned long ptr)
1727 {
1728 struct usb_hcd *hcd = (struct usb_hcd *)ptr;
1729 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
1730 struct list_head list, *tmp, *head;
1731 unsigned long flags;
1732
1733 INIT_LIST_HEAD(&list);
1734
1735 spin_lock_irqsave(&uhci->urb_list_lock, flags);
1736 head = &uhci->urb_list;
1737 tmp = head->next;
1738 while (tmp != head) {
1739 struct urb_priv *up = list_entry(tmp, struct urb_priv, urb_list);
1740 struct urb *u = up->urb;
1741
1742 tmp = tmp->next;
1743
1744 spin_lock(&u->lock);
1745
1746 /* Check if the FSBR timed out */
1747 if (up->fsbr && !up->fsbr_timeout && time_after_eq(jiffies, up->fsbrtime + IDLE_TIMEOUT))
1748 uhci_fsbr_timeout(uhci, u);
1749
1750 /* Check if the URB timed out */
1751 if (u->timeout && time_after_eq(jiffies, up->inserttime + u->timeout))
1752 list_move_tail(&up->urb_list, &list);
1753
1754 spin_unlock(&u->lock);
1755 }
1756 spin_unlock_irqrestore(&uhci->urb_list_lock, flags);
1757
1758 head = &list;
1759 tmp = head->next;
1760 while (tmp != head) {
1761 struct urb_priv *up = list_entry(tmp, struct urb_priv, urb_list);
1762 struct urb *u = up->urb;
1763
1764 tmp = tmp->next;
1765
1766 uhci_urb_dequeue(hcd, u);
1767 }
1768
1769 /* Really disable FSBR */
1770 if (!uhci->fsbr && uhci->fsbrtimeout && time_after_eq(jiffies, uhci->fsbrtimeout)) {
1771 uhci->fsbrtimeout = 0;
1772 uhci->skel_term_qh->link = UHCI_PTR_TERM;
1773 }
1774
1775 /* Poll for and perform state transitions */
1776 hc_state_transitions(uhci);
1777
1778 init_stall_timer(hcd);
1779 }
1780
1781 static int init_stall_timer(struct usb_hcd *hcd)
1782 {
1783 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
1784
1785 init_timer(&uhci->stall_timer);
1786 uhci->stall_timer.function = stall_callback;
1787 uhci->stall_timer.data = (unsigned long)hcd;
1788 uhci->stall_timer.expires = jiffies + (HZ / 10);
1789 add_timer(&uhci->stall_timer);
1790
1791 return 0;
1792 }
1793
1794 static void uhci_free_pending_qhs(struct uhci_hcd *uhci)
1795 {
1796 struct list_head *tmp, *head;
1797 unsigned long flags;
1798
1799 spin_lock_irqsave(&uhci->qh_remove_list_lock, flags);
1800 head = &uhci->qh_remove_list;
1801 tmp = head->next;
1802 while (tmp != head) {
1803 struct uhci_qh *qh = list_entry(tmp, struct uhci_qh, remove_list);
1804
1805 tmp = tmp->next;
1806
1807 list_del_init(&qh->remove_list);
1808
1809 uhci_free_qh(uhci, qh);
1810 }
1811 spin_unlock_irqrestore(&uhci->qh_remove_list_lock, flags);
1812 }
1813
1814 static void uhci_finish_urb(struct usb_hcd *hcd, struct urb *urb, struct pt_regs *regs)
1815 {
1816 struct urb_priv *urbp = (struct urb_priv *)urb->hcpriv;
1817 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
1818 int status;
1819 unsigned long flags;
1820
1821 spin_lock_irqsave(&urb->lock, flags);
1822 status = urbp->status;
1823 uhci_destroy_urb_priv(uhci, urb);
1824
1825 if (urb->status != -ENOENT && urb->status != -ECONNRESET)
1826 urb->status = status;
1827 spin_unlock_irqrestore(&urb->lock, flags);
1828
1829 usb_hcd_giveback_urb(hcd, urb, regs);
1830 }
1831
1832 static void uhci_finish_completion(struct usb_hcd *hcd, struct pt_regs *regs)
1833 {
1834 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
1835 struct list_head *tmp, *head;
1836 unsigned long flags;
1837
1838 spin_lock_irqsave(&uhci->complete_list_lock, flags);
1839 head = &uhci->complete_list;
1840 tmp = head->next;
1841 while (tmp != head) {
1842 struct urb_priv *urbp = list_entry(tmp, struct urb_priv, complete_list);
1843 struct urb *urb = urbp->urb;
1844
1845 list_del_init(&urbp->complete_list);
1846 spin_unlock_irqrestore(&uhci->complete_list_lock, flags);
1847
1848 uhci_finish_urb(hcd, urb, regs);
1849
1850 spin_lock_irqsave(&uhci->complete_list_lock, flags);
1851 head = &uhci->complete_list;
1852 tmp = head->next;
1853 }
1854 spin_unlock_irqrestore(&uhci->complete_list_lock, flags);
1855 }
1856
1857 static void uhci_remove_pending_qhs(struct uhci_hcd *uhci)
1858 {
1859 struct list_head *tmp, *head;
1860 unsigned long flags;
1861
1862 spin_lock_irqsave(&uhci->urb_remove_list_lock, flags);
1863 head = &uhci->urb_remove_list;
1864 tmp = head->next;
1865 while (tmp != head) {
1866 struct urb_priv *urbp = list_entry(tmp, struct urb_priv, urb_list);
1867 struct urb *urb = urbp->urb;
1868
1869 tmp = tmp->next;
1870
1871 list_del_init(&urbp->urb_list);
1872
1873 urbp->status = urb->status = -ECONNRESET;
1874
1875 uhci_add_complete(uhci, urb);
1876 }
1877 spin_unlock_irqrestore(&uhci->urb_remove_list_lock, flags);
1878 }
1879
1880 static int uhci_irq(struct usb_hcd *hcd, struct pt_regs *regs)
1881 {
1882 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
1883 unsigned int io_addr = uhci->io_addr;
1884 unsigned short status;
1885 struct list_head *tmp, *head;
1886
1887 /*
1888 * Read the interrupt status, and write it back to clear the
1889 * interrupt cause
1890 */
1891 status = inw(io_addr + USBSTS);
1892 if (!status) /* shared interrupt, not mine */
1893 return 0;
1894 outw(status, io_addr + USBSTS); /* Clear it */
1895
1896 if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) {
1897 if (status & USBSTS_HSE)
1898 err("%x: host system error, PCI problems?", io_addr);
1899 if (status & USBSTS_HCPE)
1900 err("%x: host controller process error. something bad happened", io_addr);
1901 if ((status & USBSTS_HCH) && uhci->state > 0) {
1902 err("%x: host controller halted. very bad", io_addr);
1903 /* FIXME: Reset the controller, fix the offending TD */
1904 }
1905 }
1906
1907 if (status & USBSTS_RD)
1908 uhci->resume_detect = 1;
1909
1910 uhci_free_pending_qhs(uhci);
1911
1912 uhci_remove_pending_qhs(uhci);
1913
1914 uhci_clear_next_interrupt(uhci);
1915
1916 /* Walk the list of pending URB's to see which ones completed */
1917 spin_lock(&uhci->urb_list_lock);
1918 head = &uhci->urb_list;
1919 tmp = head->next;
1920 while (tmp != head) {
1921 struct urb_priv *urbp = list_entry(tmp, struct urb_priv, urb_list);
1922 struct urb *urb = urbp->urb;
1923
1924 tmp = tmp->next;
1925
1926 /* Checks the status and does all of the magic necessary */
1927 uhci_transfer_result(uhci, urb);
1928 }
1929 spin_unlock(&uhci->urb_list_lock);
1930
1931 uhci_finish_completion(hcd, regs);
1932
1933 return 0;
1934 }
1935
1936 static void reset_hc(struct uhci_hcd *uhci)
1937 {
1938 unsigned int io_addr = uhci->io_addr;
1939
1940 /* Global reset for 50ms */
1941 uhci->state = UHCI_RESET;
1942 outw(USBCMD_GRESET, io_addr + USBCMD);
1943 set_current_state(TASK_UNINTERRUPTIBLE);
1944 schedule_timeout((HZ*50+999) / 1000);
1945 set_current_state(TASK_RUNNING);
1946 outw(0, io_addr + USBCMD);
1947
1948 /* Another 10ms delay */
1949 set_current_state(TASK_UNINTERRUPTIBLE);
1950 schedule_timeout((HZ*10+999) / 1000);
1951 set_current_state(TASK_RUNNING);
1952 uhci->resume_detect = 0;
1953 }
1954
1955 static void suspend_hc(struct uhci_hcd *uhci)
1956 {
1957 unsigned int io_addr = uhci->io_addr;
1958
1959 dbg("%x: suspend_hc", io_addr);
1960 uhci->state = UHCI_SUSPENDED;
1961 uhci->resume_detect = 0;
1962 outw(USBCMD_EGSM, io_addr + USBCMD);
1963 }
1964
1965 static void wakeup_hc(struct uhci_hcd *uhci)
1966 {
1967 unsigned int io_addr = uhci->io_addr;
1968
1969 switch (uhci->state) {
1970 case UHCI_SUSPENDED: /* Start the resume */
1971 dbg("%x: wakeup_hc", io_addr);
1972
1973 /* Global resume for >= 20ms */
1974 outw(USBCMD_FGR | USBCMD_EGSM, io_addr + USBCMD);
1975 uhci->state = UHCI_RESUMING_1;
1976 uhci->state_end = jiffies + (20*HZ+999) / 1000;
1977 break;
1978
1979 case UHCI_RESUMING_1: /* End global resume */
1980 uhci->state = UHCI_RESUMING_2;
1981 outw(0, io_addr + USBCMD);
1982 /* Falls through */
1983
1984 case UHCI_RESUMING_2: /* Wait for EOP to be sent */
1985 if (inw(io_addr + USBCMD) & USBCMD_FGR)
1986 break;
1987
1988 /* Run for at least 1 second, and
1989 * mark it configured with a 64-byte max packet */
1990 uhci->state = UHCI_RUNNING_GRACE;
1991 uhci->state_end = jiffies + HZ;
1992 outw(USBCMD_RS | USBCMD_CF | USBCMD_MAXP,
1993 io_addr + USBCMD);
1994 break;
1995
1996 case UHCI_RUNNING_GRACE: /* Now allowed to suspend */
1997 uhci->state = UHCI_RUNNING;
1998 break;
1999
2000 default:
2001 break;
2002 }
2003 }
2004
2005 static int ports_active(struct uhci_hcd *uhci)
2006 {
2007 unsigned int io_addr = uhci->io_addr;
2008 int connection = 0;
2009 int i;
2010
2011 for (i = 0; i < uhci->rh_numports; i++)
2012 connection |= (inw(io_addr + USBPORTSC1 + i * 2) & USBPORTSC_CCS);
2013
2014 return connection;
2015 }
2016
2017 static int suspend_allowed(struct uhci_hcd *uhci)
2018 {
2019 unsigned int io_addr = uhci->io_addr;
2020 int i;
2021
2022 if (!uhci->hcd.pdev ||
2023 uhci->hcd.pdev->vendor != PCI_VENDOR_ID_INTEL ||
2024 uhci->hcd.pdev->device != PCI_DEVICE_ID_INTEL_82371AB_2)
2025 return 1;
2026
2027 /* This is a 82371AB/EB/MB USB controller which has a bug that
2028 * causes false resume indications if any port has an
2029 * over current condition. To prevent problems, we will not
2030 * allow a global suspend if any ports are OC.
2031 *
2032 * Some motherboards using the 82371AB/EB/MB (but not the USB portion)
2033 * appear to hardwire the over current inputs active to disable
2034 * the USB ports.
2035 */
2036
2037 /* check for over current condition on any port */
2038 for (i = 0; i < uhci->rh_numports; i++) {
2039 if (inw(io_addr + USBPORTSC1 + i * 2) & USBPORTSC_OC)
2040 return 0;
2041 }
2042
2043 return 1;
2044 }
2045
2046 static void hc_state_transitions(struct uhci_hcd *uhci)
2047 {
2048 switch (uhci->state) {
2049 case UHCI_RUNNING:
2050
2051 /* global suspend if nothing connected for 1 second */
2052 if (!ports_active(uhci) && suspend_allowed(uhci)) {
2053 uhci->state = UHCI_SUSPENDING_GRACE;
2054 uhci->state_end = jiffies + HZ;
2055 }
2056 break;
2057
2058 case UHCI_SUSPENDING_GRACE:
2059 if (ports_active(uhci))
2060 uhci->state = UHCI_RUNNING;
2061 else if (time_after_eq(jiffies, uhci->state_end))
2062 suspend_hc(uhci);
2063 break;
2064
2065 case UHCI_SUSPENDED:
2066
2067 /* wakeup if requested by a device */
2068 if (uhci->resume_detect)
2069 wakeup_hc(uhci);
2070 break;
2071
2072 case UHCI_RESUMING_1:
2073 case UHCI_RESUMING_2:
2074 case UHCI_RUNNING_GRACE:
2075 if (time_after_eq(jiffies, uhci->state_end))
2076 wakeup_hc(uhci);
2077 break;
2078
2079 default:
2080 break;
2081 }
2082 }
2083
2084 static void start_hc(struct uhci_hcd *uhci)
2085 {
2086 unsigned int io_addr = uhci->io_addr;
2087 int timeout = 1000;
2088
2089 /*
2090 * Reset the HC - this will force us to get a
2091 * new notification of any already connected
2092 * ports due to the virtual disconnect that it
2093 * implies.
2094 */
2095 outw(USBCMD_HCRESET, io_addr + USBCMD);
2096 while (inw(io_addr + USBCMD) & USBCMD_HCRESET) {
2097 if (!--timeout) {
2098 printk(KERN_ERR "uhci: USBCMD_HCRESET timed out!\n");
2099 break;
2100 }
2101 }
2102
2103 /* Turn on all interrupts */
2104 outw(USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP,
2105 io_addr + USBINTR);
2106
2107 /* Start at frame 0 */
2108 outw(0, io_addr + USBFRNUM);
2109 outl(uhci->fl->dma_handle, io_addr + USBFLBASEADD);
2110
2111 /* Run and mark it configured with a 64-byte max packet */
2112 uhci->state = UHCI_RUNNING_GRACE;
2113 uhci->state_end = jiffies + HZ;
2114 outw(USBCMD_RS | USBCMD_CF | USBCMD_MAXP, io_addr + USBCMD);
2115
2116 uhci->hcd.state = USB_STATE_READY;
2117 }
2118
2119 /*
2120 * De-allocate all resources..
2121 */
2122 static void release_uhci(struct uhci_hcd *uhci)
2123 {
2124 int i;
2125
2126 for (i = 0; i < UHCI_NUM_SKELQH; i++)
2127 if (uhci->skelqh[i]) {
2128 uhci_free_qh(uhci, uhci->skelqh[i]);
2129 uhci->skelqh[i] = NULL;
2130 }
2131
2132 if (uhci->term_td) {
2133 uhci_free_td(uhci, uhci->term_td);
2134 uhci->term_td = NULL;
2135 }
2136
2137 if (uhci->qh_pool) {
2138 pci_pool_destroy(uhci->qh_pool);
2139 uhci->qh_pool = NULL;
2140 }
2141
2142 if (uhci->td_pool) {
2143 pci_pool_destroy(uhci->td_pool);
2144 uhci->td_pool = NULL;
2145 }
2146
2147 if (uhci->fl) {
2148 pci_free_consistent(uhci->hcd.pdev, sizeof(*uhci->fl), uhci->fl, uhci->fl->dma_handle);
2149 uhci->fl = NULL;
2150 }
2151
2152 #ifdef CONFIG_PROC_FS
2153 if (uhci->proc_entry) {
2154 remove_proc_entry(uhci->hcd.self.bus_name, uhci_proc_root);
2155 uhci->proc_entry = NULL;
2156 }
2157 #endif
2158 }
2159
2160 /*
2161 * Allocate a frame list, and then setup the skeleton
2162 *
2163 * The hardware doesn't really know any difference
2164 * in the queues, but the order does matter for the
2165 * protocols higher up. The order is:
2166 *
2167 * - any isochronous events handled before any
2168 * of the queues. We don't do that here, because
2169 * we'll create the actual TD entries on demand.
2170 * - The first queue is the interrupt queue.
2171 * - The second queue is the control queue, split into low and high speed
2172 * - The third queue is bulk queue.
2173 * - The fourth queue is the bandwidth reclamation queue, which loops back
2174 * to the high speed control queue.
2175 */
2176 static int __devinit uhci_start(struct usb_hcd *hcd)
2177 {
2178 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
2179 int retval = -EBUSY;
2180 int i, port;
2181 unsigned io_size;
2182 dma_addr_t dma_handle;
2183 struct usb_device *udev;
2184 #ifdef CONFIG_PROC_FS
2185 struct proc_dir_entry *ent;
2186 #endif
2187
2188 uhci->io_addr = (unsigned long) hcd->regs;
2189 io_size = pci_resource_len(hcd->pdev, hcd->region);
2190
2191 #ifdef CONFIG_PROC_FS
2192 ent = create_proc_entry(hcd->self.bus_name, S_IFREG|S_IRUGO|S_IWUSR, uhci_proc_root);
2193 if (!ent) {
2194 err("couldn't create uhci proc entry");
2195 retval = -ENOMEM;
2196 goto err_create_proc_entry;
2197 }
2198
2199 ent->data = uhci;
2200 ent->proc_fops = &uhci_proc_operations;
2201 ent->size = 0;
2202 uhci->proc_entry = ent;
2203 #endif
2204
2205 /* Reset here so we don't get any interrupts from an old setup */
2206 /* or broken setup */
2207 reset_hc(uhci);
2208
2209 uhci->fsbr = 0;
2210 uhci->fsbrtimeout = 0;
2211
2212 spin_lock_init(&uhci->qh_remove_list_lock);
2213 INIT_LIST_HEAD(&uhci->qh_remove_list);
2214
2215 spin_lock_init(&uhci->urb_remove_list_lock);
2216 INIT_LIST_HEAD(&uhci->urb_remove_list);
2217
2218 spin_lock_init(&uhci->urb_list_lock);
2219 INIT_LIST_HEAD(&uhci->urb_list);
2220
2221 spin_lock_init(&uhci->complete_list_lock);
2222 INIT_LIST_HEAD(&uhci->complete_list);
2223
2224 spin_lock_init(&uhci->frame_list_lock);
2225
2226 uhci->fl = pci_alloc_consistent(hcd->pdev, sizeof(*uhci->fl), &dma_handle);
2227 if (!uhci->fl) {
2228 err("unable to allocate consistent memory for frame list");
2229 goto err_alloc_fl;
2230 }
2231
2232 memset((void *)uhci->fl, 0, sizeof(*uhci->fl));
2233
2234 uhci->fl->dma_handle = dma_handle;
2235
2236 uhci->td_pool = pci_pool_create("uhci_td", hcd->pdev,
2237 sizeof(struct uhci_td), 16, 0);
2238 if (!uhci->td_pool) {
2239 err("unable to create td pci_pool");
2240 goto err_create_td_pool;
2241 }
2242
2243 uhci->qh_pool = pci_pool_create("uhci_qh", hcd->pdev,
2244 sizeof(struct uhci_qh), 16, 0);
2245 if (!uhci->qh_pool) {
2246 err("unable to create qh pci_pool");
2247 goto err_create_qh_pool;
2248 }
2249
2250 /* Initialize the root hub */
2251
2252 /* UHCI specs says devices must have 2 ports, but goes on to say */
2253 /* they may have more but give no way to determine how many they */
2254 /* have. However, according to the UHCI spec, Bit 7 is always set */
2255 /* to 1. So we try to use this to our advantage */
2256 for (port = 0; port < (io_size - 0x10) / 2; port++) {
2257 unsigned int portstatus;
2258
2259 portstatus = inw(uhci->io_addr + 0x10 + (port * 2));
2260 if (!(portstatus & 0x0080))
2261 break;
2262 }
2263 if (debug)
2264 info("detected %d ports", port);
2265
2266 /* This is experimental so anything less than 2 or greater than 8 is */
2267 /* something weird and we'll ignore it */
2268 if (port < 2 || port > 8) {
2269 info("port count misdetected? forcing to 2 ports");
2270 port = 2;
2271 }
2272
2273 uhci->rh_numports = port;
2274
2275 hcd->self.root_hub = udev = usb_alloc_dev(NULL, &hcd->self);
2276 if (!udev) {
2277 err("unable to allocate root hub");
2278 goto err_alloc_root_hub;
2279 }
2280 hcd->pdev->bus = (struct pci_bus *)udev; /* Fix bus pointer for initial device */
2281
2282 uhci->term_td = uhci_alloc_td(uhci, udev);
2283 if (!uhci->term_td) {
2284 err("unable to allocate terminating TD");
2285 goto err_alloc_term_td;
2286 }
2287
2288 for (i = 0; i < UHCI_NUM_SKELQH; i++) {
2289 uhci->skelqh[i] = uhci_alloc_qh(uhci, udev);
2290 if (!uhci->skelqh[i]) {
2291 err("unable to allocate QH %d", i);
2292 goto err_alloc_skelqh;
2293 }
2294 }
2295
2296 /*
2297 * 8 Interrupt queues; link int2 to int1, int4 to int2, etc
2298 * then link int1 to control and control to bulk
2299 */
2300 uhci->skel_int128_qh->link = cpu_to_le32(uhci->skel_int64_qh->dma_handle) | UHCI_PTR_QH;
2301 uhci->skel_int64_qh->link = cpu_to_le32(uhci->skel_int32_qh->dma_handle) | UHCI_PTR_QH;
2302 uhci->skel_int32_qh->link = cpu_to_le32(uhci->skel_int16_qh->dma_handle) | UHCI_PTR_QH;
2303 uhci->skel_int16_qh->link = cpu_to_le32(uhci->skel_int8_qh->dma_handle) | UHCI_PTR_QH;
2304 uhci->skel_int8_qh->link = cpu_to_le32(uhci->skel_int4_qh->dma_handle) | UHCI_PTR_QH;
2305 uhci->skel_int4_qh->link = cpu_to_le32(uhci->skel_int2_qh->dma_handle) | UHCI_PTR_QH;
2306 uhci->skel_int2_qh->link = cpu_to_le32(uhci->skel_int1_qh->dma_handle) | UHCI_PTR_QH;
2307 uhci->skel_int1_qh->link = cpu_to_le32(uhci->skel_ls_control_qh->dma_handle) | UHCI_PTR_QH;
2308
2309 uhci->skel_ls_control_qh->link = cpu_to_le32(uhci->skel_hs_control_qh->dma_handle) | UHCI_PTR_QH;
2310 uhci->skel_hs_control_qh->link = cpu_to_le32(uhci->skel_bulk_qh->dma_handle) | UHCI_PTR_QH;
2311 uhci->skel_bulk_qh->link = cpu_to_le32(uhci->skel_term_qh->dma_handle) | UHCI_PTR_QH;
2312
2313 /* This dummy TD is to work around a bug in Intel PIIX controllers */
2314 uhci_fill_td(uhci->term_td, 0, (UHCI_NULL_DATA_SIZE << 21) |
2315 (0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0);
2316 uhci->term_td->link = cpu_to_le32(uhci->term_td->dma_handle);
2317
2318 uhci->skel_term_qh->link = UHCI_PTR_TERM;
2319 uhci->skel_term_qh->element = cpu_to_le32(uhci->term_td->dma_handle);
2320
2321 /*
2322 * Fill the frame list: make all entries point to
2323 * the proper interrupt queue.
2324 *
2325 * This is probably silly, but it's a simple way to
2326 * scatter the interrupt queues in a way that gives
2327 * us a reasonable dynamic range for irq latencies.
2328 */
2329 for (i = 0; i < UHCI_NUMFRAMES; i++) {
2330 int irq = 0;
2331
2332 if (i & 1) {
2333 irq++;
2334 if (i & 2) {
2335 irq++;
2336 if (i & 4) {
2337 irq++;
2338 if (i & 8) {
2339 irq++;
2340 if (i & 16) {
2341 irq++;
2342 if (i & 32) {
2343 irq++;
2344 if (i & 64)
2345 irq++;
2346 }
2347 }
2348 }
2349 }
2350 }
2351 }
2352
2353 /* Only place we don't use the frame list routines */
2354 uhci->fl->frame[i] = cpu_to_le32(uhci->skelqh[7 - irq]->dma_handle);
2355 }
2356
2357 start_hc(uhci);
2358
2359 init_stall_timer(hcd);
2360
2361 /* disable legacy emulation */
2362 pci_write_config_word(hcd->pdev, USBLEGSUP, USBLEGSUP_DEFAULT);
2363
2364 usb_connect(udev);
2365 udev->speed = USB_SPEED_FULL;
2366
2367 if (usb_register_root_hub(udev, &hcd->pdev->dev) != 0) {
2368 err("unable to start root hub");
2369 retval = -ENOMEM;
2370 goto err_start_root_hub;
2371 }
2372
2373 return 0;
2374
2375 /*
2376 * error exits:
2377 */
2378 err_start_root_hub:
2379 reset_hc(uhci);
2380
2381 del_timer_sync(&uhci->stall_timer);
2382
2383 err_alloc_skelqh:
2384 for (i = 0; i < UHCI_NUM_SKELQH; i++)
2385 if (uhci->skelqh[i]) {
2386 uhci_free_qh(uhci, uhci->skelqh[i]);
2387 uhci->skelqh[i] = NULL;
2388 }
2389
2390 uhci_free_td(uhci, uhci->term_td);
2391 uhci->term_td = NULL;
2392
2393 err_alloc_term_td:
2394 usb_put_dev(udev);
2395 hcd->self.root_hub = NULL;
2396
2397 err_alloc_root_hub:
2398 pci_pool_destroy(uhci->qh_pool);
2399 uhci->qh_pool = NULL;
2400
2401 err_create_qh_pool:
2402 pci_pool_destroy(uhci->td_pool);
2403 uhci->td_pool = NULL;
2404
2405 err_create_td_pool:
2406 pci_free_consistent(hcd->pdev, sizeof(*uhci->fl), uhci->fl, uhci->fl->dma_handle);
2407 uhci->fl = NULL;
2408
2409 err_alloc_fl:
2410 #ifdef CONFIG_PROC_FS
2411 remove_proc_entry(hcd->self.bus_name, uhci_proc_root);
2412 uhci->proc_entry = NULL;
2413
2414 err_create_proc_entry:
2415 #endif
2416
2417 return retval;
2418 }
2419
2420 static void uhci_stop(struct usb_hcd *hcd)
2421 {
2422 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
2423
2424 del_timer_sync(&uhci->stall_timer);
2425
2426 /*
2427 * At this point, we're guaranteed that no new connects can be made
2428 * to this bus since there are no more parents
2429 */
2430 uhci_free_pending_qhs(uhci);
2431 uhci_remove_pending_qhs(uhci);
2432
2433 reset_hc(uhci);
2434
2435 uhci_free_pending_qhs(uhci);
2436
2437 release_uhci(uhci);
2438 }
2439
2440 #ifdef CONFIG_PM
2441 static int uhci_suspend(struct usb_hcd *hcd, u32 state)
2442 {
2443 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
2444
2445 /* Don't try to suspend broken motherboards, reset instead */
2446 if (suspend_allowed(uhci))
2447 suspend_hc(uhci);
2448 else
2449 reset_hc(uhci);
2450 return 0;
2451 }
2452
2453 static int uhci_resume(struct usb_hcd *hcd)
2454 {
2455 struct uhci_hcd *uhci = hcd_to_uhci(hcd);
2456
2457 pci_set_master(uhci->hcd.pdev);
2458
2459 if (uhci->state == UHCI_SUSPENDED)
2460 uhci->resume_detect = 1;
2461 else {
2462 reset_hc(uhci);
2463 start_hc(uhci);
2464 }
2465 uhci->hcd.state = USB_STATE_READY;
2466 return 0;
2467 }
2468 #endif
2469
2470 static struct usb_hcd *uhci_hcd_alloc(void)
2471 {
2472 struct uhci_hcd *uhci;
2473
2474 uhci = (struct uhci_hcd *)kmalloc(sizeof(*uhci), GFP_KERNEL);
2475 if (!uhci)
2476 return NULL;
2477
2478 memset(uhci, 0, sizeof(*uhci));
2479 return &uhci->hcd;
2480 }
2481
2482 static void uhci_hcd_free(struct usb_hcd *hcd)
2483 {
2484 kfree(hcd_to_uhci(hcd));
2485 }
2486
2487 static int uhci_hcd_get_frame_number(struct usb_hcd *hcd)
2488 {
2489 return uhci_get_current_frame_number(hcd_to_uhci(hcd));
2490 }
2491
2492 static const char hcd_name[] = "uhci-hcd";
2493
2494 static struct hc_driver uhci_driver = {
2495 .description = hcd_name,
2496
2497 /* Generic hardware linkage */
2498 .irq = uhci_irq,
2499 .flags = HCD_USB11,
2500
2501 /* Basic lifecycle operations */
2502 .start = uhci_start,
2503 #ifdef CONFIG_PM
2504 .suspend = uhci_suspend,
2505 .resume = uhci_resume,
2506 #endif
2507 .stop = uhci_stop,
2508
2509 .hcd_alloc = uhci_hcd_alloc,
2510 .hcd_free = uhci_hcd_free,
2511
2512 .urb_enqueue = uhci_urb_enqueue,
2513 .urb_dequeue = uhci_urb_dequeue,
2514
2515 .get_frame_number = uhci_hcd_get_frame_number,
2516
2517 .hub_status_data = uhci_hub_status_data,
2518 .hub_control = uhci_hub_control,
2519 };
2520
2521 const struct pci_device_id __devinitdata uhci_pci_ids[] = { {
2522
2523 /* handle any USB UHCI controller */
2524 .class = ((PCI_CLASS_SERIAL_USB << 8) | 0x00),
2525 .class_mask = ~0,
2526 .driver_data = (unsigned long) &uhci_driver,
2527
2528 /* no matter who makes it */
2529 .vendor = PCI_ANY_ID,
2530 .device = PCI_ANY_ID,
2531 .subvendor = PCI_ANY_ID,
2532 .subdevice = PCI_ANY_ID,
2533
2534 }, { /* end: all zeroes */ }
2535 };
2536
2537 MODULE_DEVICE_TABLE(pci, uhci_pci_ids);
2538
2539 struct pci_driver uhci_pci_driver = {
2540 .name = (char *)hcd_name,
2541 .id_table = uhci_pci_ids,
2542
2543 .probe = usb_hcd_pci_probe,
2544 .remove = usb_hcd_pci_remove,
2545
2546 #ifdef CONFIG_PM
2547 .suspend = usb_hcd_pci_suspend,
2548 .resume = usb_hcd_pci_resume,
2549 #endif /* PM */
2550 };
2551
2552 int __init uhci_hcd_init(void)
2553 {
2554 int retval = -ENOMEM;
2555
2556 info(DRIVER_DESC " " DRIVER_VERSION);
2557
2558 if (usb_disabled())
2559 return -ENODEV;
2560
2561 if (debug) {
2562 errbuf = kmalloc(ERRBUF_LEN, GFP_KERNEL);
2563 if (!errbuf)
2564 goto errbuf_failed;
2565 }
2566
2567 #ifdef CONFIG_PROC_FS
2568 uhci_proc_root = create_proc_entry("driver/uhci", S_IFDIR, 0);
2569 if (!uhci_proc_root)
2570 goto proc_failed;
2571 #endif
2572
2573 uhci_up_cachep = kmem_cache_create("uhci_urb_priv",
2574 sizeof(struct urb_priv), 0, 0, NULL, NULL);
2575 if (!uhci_up_cachep)
2576 goto up_failed;
2577
2578 retval = pci_module_init(&uhci_pci_driver);
2579 if (retval)
2580 goto init_failed;
2581
2582 return 0;
2583
2584 init_failed:
2585 if (kmem_cache_destroy(uhci_up_cachep))
2586 printk(KERN_INFO "uhci: not all urb_priv's were freed\n");
2587
2588 up_failed:
2589
2590 #ifdef CONFIG_PROC_FS
2591 remove_proc_entry("driver/uhci", 0);
2592
2593 proc_failed:
2594 #endif
2595 if (errbuf)
2596 kfree(errbuf);
2597
2598 errbuf_failed:
2599
2600 return retval;
2601 }
2602
2603 void __exit uhci_hcd_cleanup(void)
2604 {
2605 pci_unregister_driver(&uhci_pci_driver);
2606
2607 if (kmem_cache_destroy(uhci_up_cachep))
2608 printk(KERN_INFO "uhci: not all urb_priv's were freed\n");
2609
2610 #ifdef CONFIG_PROC_FS
2611 remove_proc_entry("driver/uhci", 0);
2612 #endif
2613
2614 if (errbuf)
2615 kfree(errbuf);
2616 }
2617
2618 /*module_init(uhci_hcd_init);*/
2619 module_exit(uhci_hcd_cleanup);
2620
2621 MODULE_AUTHOR(DRIVER_AUTHOR);
2622 MODULE_DESCRIPTION(DRIVER_DESC);
2623 MODULE_LICENSE("GPL");
2624