reactos/hal/halppc/include/bus.h

   1 #pragma once
   2
   3 //
   4 // Helper Macros
   5 //
   6 #define PASTE2(x,y)                                                     x ## y
   7 #define POINTER_TO_(x)                                                  PASTE2(P,x)
   8 #define READ_FROM(x)                                                    PASTE2(READ_PORT_, x)
   9 #define WRITE_TO(x)                                                     PASTE2(WRITE_PORT_, x)
  10
  11 //
  12 // Declares a PCI Register Read/Write Routine
  13 //
  14 #define TYPE_DEFINE(x, y)                                               \
  15     ULONG                                                               \
  16     NTAPI                                                               \
  17     x(                                                                  \
  18         IN PPCIPBUSDATA BusData,                                        \
  19         IN y PciCfg,                                                    \
  20         IN PUCHAR Buffer,                                               \
  21         IN ULONG Offset                                                 \
  22     )
  23 #define TYPE1_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS);
  24 #define TYPE2_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS);
  25
  26 //
  27 // Defines a PCI Register Read/Write Type 1 Routine Prologue and Epilogue
  28 //
  29 #define TYPE1_START(x, y)                                               \
  30     TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS)                                 \
  31 {                                                                       \
  32     ULONG i = Offset % sizeof(ULONG);                                   \
  33     PciCfg->u.bits.RegisterNumber = Offset / sizeof(ULONG);             \
  34     WRITE_PORT_ULONG(BusData->Config.Type1.Address, PciCfg->u.AsULONG);
  35 #define TYPE1_END(y)                                                    \
  36     return sizeof(y); }
  37 #define TYPE2_END       TYPE1_END
  38
  39 //
  40 // PCI Register Read Type 1 Routine
  41 //
  42 #define TYPE1_READ(x, y)                                                \
  43     TYPE1_START(x, y)                                                   \
  44     *((POINTER_TO_(y))Buffer) =                                         \
  45     READ_FROM(y)((POINTER_TO_(y))(BusData->Config.Type1.Data + i));     \
  46     TYPE1_END(y)
  47
  48 //
  49 // PCI Register Write Type 1 Routine
  50 //
  51 #define TYPE1_WRITE(x, y)                                               \
  52     TYPE1_START(x, y)                                                   \
  53     WRITE_TO(y)((POINTER_TO_(y))(BusData->Config.Type1.Data + i),       \
  54                 *((POINTER_TO_(y))Buffer));                             \
  55     TYPE1_END(y)
  56
  57 //
  58 // Defines a PCI Register Read/Write Type 2 Routine Prologue and Epilogue
  59 //
  60 #define TYPE2_START(x, y)                                               \
  61     TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS)                             \
  62 {                                                                       \
  63     PciCfg->u.bits.RegisterNumber = (USHORT)Offset;
  64
  65 //
  66 // PCI Register Read Type 2 Routine
  67 //
  68 #define TYPE2_READ(x, y)                                                \
  69     TYPE2_START(x, y)                                                   \
  70     *((POINTER_TO_(y))Buffer) =                                         \
  71         READ_FROM(y)((POINTER_TO_(y))(ULONG)PciCfg->u.AsUSHORT);        \
  72     TYPE2_END(y)
  73
  74 //
  75 // PCI Register Write Type 2 Routine
  76 //
  77 #define TYPE2_WRITE(x, y)                                               \
  78     TYPE2_START(x, y)                                                   \
  79     WRITE_TO(y)((POINTER_TO_(y))(ULONG)PciCfg->u.AsUSHORT,              \
  80                 *((POINTER_TO_(y))Buffer));                             \
  81     TYPE2_END(y)
  82
  83 typedef struct _PCIPBUSDATA
  84 {
  85     PCIBUSDATA CommonData;
  86     union
  87     {
  88         struct
  89         {
  90             PULONG Address;
  91             ULONG Data;
  92         } Type1;
  93         struct
  94         {
  95             PUCHAR CSE;
  96             PUCHAR Forward;
  97             ULONG Base;
  98         } Type2;
  99     } Config;
 100     ULONG MaxDevice;
 101 } PCIPBUSDATA, *PPCIPBUSDATA;
 102
 103 typedef ULONG
 104 (NTAPI *FncConfigIO)(
 105     IN PPCIPBUSDATA BusData,
 106     IN PVOID State,
 107     IN PUCHAR Buffer,
 108     IN ULONG Offset
 109 );
 110
 111 typedef VOID
 112 (NTAPI *FncSync)(
 113     IN PBUS_HANDLER BusHandler,
 114     IN PCI_SLOT_NUMBER Slot,
 115     IN PKIRQL Irql,
 116     IN PVOID State
 117 );
 118
 119 typedef VOID
 120 (NTAPI *FncReleaseSync)(
 121     IN PBUS_HANDLER BusHandler,
 122     IN KIRQL Irql
 123 );
 124
 125 typedef struct _PCI_CONFIG_HANDLER
 126 {
 127     FncSync Synchronize;
 128     FncReleaseSync ReleaseSynchronzation;
 129     FncConfigIO ConfigRead[3];
 130     FncConfigIO ConfigWrite[3];
 131 } PCI_CONFIG_HANDLER, *PPCI_CONFIG_HANDLER;
 132
 133 typedef struct _PCI_REGISTRY_INFO_INTERNAL
 134 {
 135     UCHAR MajorRevision;
 136     UCHAR MinorRevision;
 137     UCHAR NoBuses;
 138     UCHAR HardwareMechanism;
 139     ULONG ElementCount;
 140     PCI_CARD_DESCRIPTOR CardList[ANYSIZE_ARRAY];
 141 } PCI_REGISTRY_INFO_INTERNAL, *PPCI_REGISTRY_INFO_INTERNAL;
 142
 143 /* FUNCTIONS *****************************************************************/
 144
 145 VOID
 146 NTAPI
 147 HalpPCISynchronizeType1(
 148     IN PBUS_HANDLER BusHandler,
 149     IN PCI_SLOT_NUMBER Slot,
 150     IN PKIRQL Irql,
 151     IN PPCI_TYPE1_CFG_BITS PciCfg
 152 );
 153
 154 VOID
 155 NTAPI
 156 HalpPCIReleaseSynchronzationType1(
 157     IN PBUS_HANDLER BusHandler,
 158     IN KIRQL Irql
 159 );
 160
 161 VOID
 162 NTAPI
 163 HalpPCISynchronizeType2(
 164     IN PBUS_HANDLER BusHandler,
 165     IN PCI_SLOT_NUMBER Slot,
 166     IN PKIRQL Irql,
 167     IN PPCI_TYPE2_ADDRESS_BITS PciCfg
 168 );
 169
 170 VOID
 171 NTAPI
 172 HalpPCIReleaseSynchronzationType2(
 173     IN PBUS_HANDLER BusHandler,
 174     IN KIRQL Irql
 175 );
 176
 177 TYPE1_DEFINE(HalpPCIReadUcharType1);
 178 TYPE1_DEFINE(HalpPCIReadUshortType1);
 179 TYPE1_DEFINE(HalpPCIReadUlongType1);
 180 TYPE2_DEFINE(HalpPCIReadUcharType2);
 181 TYPE2_DEFINE(HalpPCIReadUshortType2);
 182 TYPE2_DEFINE(HalpPCIReadUlongType2);
 183 TYPE1_DEFINE(HalpPCIWriteUcharType1);
 184 TYPE1_DEFINE(HalpPCIWriteUshortType1);
 185 TYPE1_DEFINE(HalpPCIWriteUlongType1);
 186 TYPE2_DEFINE(HalpPCIWriteUcharType2);
 187 TYPE2_DEFINE(HalpPCIWriteUshortType2);
 188 TYPE2_DEFINE(HalpPCIWriteUlongType2);
 189
 190 BOOLEAN
 191 NTAPI
 192 HalpValidPCISlot(
 193     IN PBUS_HANDLER BusHandler,
 194     IN PCI_SLOT_NUMBER Slot
 195 );
 196
 197 VOID
 198 NTAPI
 199 HalpReadPCIConfig(
 200     IN PBUS_HANDLER BusHandler,
 201     IN PCI_SLOT_NUMBER Slot,
 202     IN PVOID Buffer,
 203     IN ULONG Offset,
 204     IN ULONG Length
 205 );
 206
 207 VOID
 208 NTAPI
 209 HalpWritePCIConfig(
 210     IN PBUS_HANDLER BusHandler,
 211     IN PCI_SLOT_NUMBER Slot,
 212     IN PVOID Buffer,
 213     IN ULONG Offset,
 214     IN ULONG Length
 215 );
 216
 217 ULONG
 218 NTAPI
 219 HalpGetSystemInterruptVector(
 220     ULONG BusNumber,
 221     ULONG BusInterruptLevel,
 222     ULONG BusInterruptVector,
 223     PKIRQL Irql,
 224     PKAFFINITY Affinity
 225 );
 226
 227 ULONG
 228 NTAPI
 229 HalpGetCmosData(
 230     IN ULONG BusNumber,
 231     IN ULONG SlotNumber,
 232     IN PVOID Buffer,
 233     IN ULONG Length
 234 );
 235
 236 ULONG
 237 NTAPI
 238 HalpSetCmosData(
 239     IN ULONG BusNumber,
 240     IN ULONG SlotNumber,
 241     IN PVOID Buffer,
 242     IN ULONG Length
 243 );
 244
 245 ULONG
 246 NTAPI
 247 HalpGetPCIData(
 248     IN PBUS_HANDLER BusHandler,
 249     IN PBUS_HANDLER RootBusHandler,
 250     IN PCI_SLOT_NUMBER SlotNumber,
 251     IN PUCHAR Buffer,
 252     IN ULONG Offset,
 253     IN ULONG Length
 254 );
 255
 256 ULONG
 257 NTAPI
 258 HalpSetPCIData(
 259     IN PBUS_HANDLER BusHandler,
 260     IN PBUS_HANDLER RootBusHandler,
 261     IN PCI_SLOT_NUMBER SlotNumber,
 262     IN PUCHAR Buffer,
 263     IN ULONG Offset,
 264     IN ULONG Length
 265 );
 266
 267 NTSTATUS
 268 NTAPI
 269 HalpAssignPCISlotResources(
 270     IN PBUS_HANDLER BusHandler,
 271     IN PBUS_HANDLER RootHandler,
 272     IN PUNICODE_STRING RegistryPath,
 273     IN PUNICODE_STRING DriverClassName OPTIONAL,
 274     IN PDRIVER_OBJECT DriverObject,
 275     IN PDEVICE_OBJECT DeviceObject OPTIONAL,
 276     IN ULONG Slot,
 277     IN OUT PCM_RESOURCE_LIST *pAllocatedResources
 278 );
 279
 280 VOID
 281 NTAPI
 282 HalpInitializePciBus(
 283     VOID
 284 );
 285
 286 extern ULONG HalpBusType;
 287 extern BOOLEAN HalpPCIConfigInitialized;
 288 extern BUS_HANDLER HalpFakePciBusHandler;
 289 extern ULONG HalpMinPciBus, HalpMaxPciBus;
 290
 291 /* EOF */