reactos/hal/halppc/include/haldma.h

   1 #pragma once
   2
   3 /*
   4  * DMA Page Register Structure
   5  * 080     DMA        RESERVED
   6  * 081     DMA        Page Register (channel 2)
   7  * 082     DMA        Page Register (channel 3)
   8  * 083     DMA        Page Register (channel 1)
   9  * 084     DMA        RESERVED
  10  * 085     DMA        RESERVED
  11  * 086     DMA        RESERVED
  12  * 087     DMA        Page Register (channel 0)
  13  * 088     DMA        RESERVED
  14  * 089     PS/2-DMA   Page Register (channel 6)
  15  * 08A     PS/2-DMA   Page Register (channel 7)
  16  * 08B     PS/2-DMA   Page Register (channel 5)
  17  * 08C     PS/2-DMA   RESERVED
  18  * 08D     PS/2-DMA   RESERVED
  19  * 08E     PS/2-DMA   RESERVED
  20  * 08F     PS/2-DMA   Page Register (channel 4)
  21  */
  22
  23 typedef struct _DMA_PAGE
  24 {
  25    UCHAR Reserved1;
  26    UCHAR Channel2;
  27    UCHAR Channel3;
  28    UCHAR Channel1;
  29    UCHAR Reserved2[3];
  30    UCHAR Channel0;
  31    UCHAR Reserved3;
  32    UCHAR Channel6;
  33    UCHAR Channel7;
  34    UCHAR Channel5;
  35    UCHAR Reserved4[3];
  36    UCHAR Channel4;
  37 } DMA_PAGE, *PDMA_PAGE;
  38
  39 /*
  40  * DMA Channel Mask Register Structure
  41  *
  42  * MSB                             LSB
  43  *       x   x   x   x     x   x   x   x
  44  *       -------------------   -   -----
  45  *                |            |     |     00 - Select channel 0 mask bit
  46  *                |            |     \---- 01 - Select channel 1 mask bit
  47  *                |            |           10 - Select channel 2 mask bit
  48  *                |            |           11 - Select channel 3 mask bit
  49  *                |            |
  50  *                |            \----------  0 - Clear mask bit
  51  *                |                         1 - Set mask bit
  52  *                |
  53  *                \----------------------- xx - Reserved
  54  */
  55
  56 typedef struct _DMA_CHANNEL_MASK
  57 {
  58    UCHAR Channel: 2;
  59    UCHAR SetMask: 1;
  60    UCHAR Reserved: 5;
  61 } DMA_CHANNEL_MASK, *PDMA_CHANNEL_MASK;
  62
  63 /*
  64  * DMA Mask Register Structure
  65  *
  66  * MSB                             LSB
  67  *    x   x   x   x     x   x   x   x
  68  *    \---/   -   -     -----   -----
  69  *      |     |   |       |       |     00 - Channel 0 select
  70  *      |     |   |       |       \---- 01 - Channel 1 select
  71  *      |     |   |       |             10 - Channel 2 select
  72  *      |     |   |       |             11 - Channel 3 select
  73  *      |     |   |       |
  74  *      |     |   |       |             00 - Verify transfer
  75  *      |     |   |       \------------ 01 - Write transfer
  76  *      |     |   |                     10 - Read transfer
  77  *      |     |   |
  78  *      |     |   \--------------------  0 - Autoinitialized
  79  *      |     |                          1 - Non-autoinitialized
  80  *      |     |
  81  *      |     \------------------------  0 - Address increment select
  82  *      |
  83  *      |                               00 - Demand mode
  84  *      \------------------------------ 01 - Single mode
  85  *                                      10 - Block mode
  86  *                                      11 - Cascade mode
  87  */
  88
  89 typedef union _DMA_MODE
  90 {
  91    struct
  92    {
  93       UCHAR Channel: 2;
  94       UCHAR TransferType: 2;
  95       UCHAR AutoInitialize: 1;
  96       UCHAR AddressDecrement: 1;
  97       UCHAR RequestMode: 2;
  98    };
  99    UCHAR Byte;
 100 } DMA_MODE, *PDMA_MODE;
 101
 102 /*
 103  * DMA Extended Mode Register Structure
 104  *
 105  * MSB                             LSB
 106  *    x   x   x   x     x   x   x   x
 107  *    -   -   -----     -----   -----
 108  *    |   |     |         |       |     00 - Channel 0 select
 109  *    |   |     |         |       \---- 01 - Channel 1 select
 110  *    |   |     |         |             10 - Channel 2 select
 111  *    |   |     |         |             11 - Channel 3 select
 112  *    |   |     |         |
 113  *    |   |     |         |             00 - 8-bit I/O, by bytes
 114  *    |   |     |         \------------ 01 - 16-bit I/O, by words, address shifted
 115  *    |   |     |                       10 - 32-bit I/O, by bytes
 116  *    |   |     |                       11 - 16-bit I/O, by bytes
 117  *    |   |     |
 118  *    |   |     \---------------------- 00 - Compatible
 119  *    |   |                             01 - Type A
 120  *    |   |                             10 - Type B
 121  *    |   |                             11 - Burst
 122  *    |   |
 123  *    |   \---------------------------- 0 - Terminal Count is Output
 124  *    |
 125  *    \---------------------------------0 - Disable Stop Register
 126  *                                      1 - Enable Stop Register
 127  */
 128
 129 typedef union _DMA_EXTENDED_MODE
 130 {
 131    struct
 132    {
 133       UCHAR ChannelNumber: 2;
 134       UCHAR TransferSize: 2;
 135       UCHAR TimingMode: 2;
 136       UCHAR TerminalCountIsOutput: 1;
 137       UCHAR EnableStopRegister: 1;
 138    };
 139    UCHAR Byte;
 140 } DMA_EXTENDED_MODE, *PDMA_EXTENDED_MODE;
 141
 142 /* DMA Extended Mode Register Transfer Sizes */
 143 #define B_8BITS 0
 144 #define W_16BITS 1
 145 #define B_32BITS 2
 146 #define B_16BITS 3
 147
 148 /* DMA Extended Mode Register Timing */
 149 #define COMPATIBLE_TIMING 0
 150 #define TYPE_A_TIMING 1
 151 #define TYPE_B_TIMING 2
 152 #define BURST_TIMING 3
 153
 154 /* Channel Stop Registers for each Channel */
 155 typedef struct _DMA_CHANNEL_STOP
 156 {
 157    UCHAR ChannelLow;
 158    UCHAR ChannelMid;
 159    UCHAR ChannelHigh;
 160    UCHAR Reserved;
 161 } DMA_CHANNEL_STOP, *PDMA_CHANNEL_STOP;
 162
 163 /* Transfer Types */
 164 #define VERIFY_TRANSFER 0x00
 165 #define READ_TRANSFER 0x01
 166 #define WRITE_TRANSFER 0x02
 167
 168 /* Request Modes */
 169 #define DEMAND_REQUEST_MODE 0x00
 170 #define SINGLE_REQUEST_MODE 0x01
 171 #define BLOCK_REQUEST_MODE 0x02
 172 #define CASCADE_REQUEST_MODE 0x03
 173
 174 #define DMA_SETMASK 4
 175 #define DMA_CLEARMASK 0
 176 #define DMA_READ 4
 177 #define DMA_WRITE 8
 178 #define DMA_SINGLE_TRANSFER 0x40
 179 #define DMA_AUTO_INIT 0x10
 180
 181 typedef struct _DMA1_ADDRESS_COUNT
 182 {
 183    UCHAR DmaBaseAddress;
 184    UCHAR DmaBaseCount;
 185 } DMA1_ADDRESS_COUNT, *PDMA1_ADDRESS_COUNT;
 186
 187 typedef struct _DMA2_ADDRESS_COUNT
 188 {
 189    UCHAR DmaBaseAddress;
 190    UCHAR Reserved1;
 191    UCHAR DmaBaseCount;
 192    UCHAR Reserved2;
 193 } DMA2_ADDRESS_COUNT, *PDMA2_ADDRESS_COUNT;
 194
 195 typedef struct _DMA1_CONTROL
 196 {
 197    DMA1_ADDRESS_COUNT DmaAddressCount[4];
 198    UCHAR DmaStatus;
 199    UCHAR DmaRequest;
 200    UCHAR SingleMask;
 201    UCHAR Mode;
 202    UCHAR ClearBytePointer;
 203    UCHAR MasterClear;
 204    UCHAR ClearMask;
 205    UCHAR AllMask;
 206 } DMA1_CONTROL, *PDMA1_CONTROL;
 207
 208 typedef struct _DMA2_CONTROL
 209 {
 210    DMA2_ADDRESS_COUNT DmaAddressCount[4];
 211    UCHAR DmaStatus;
 212    UCHAR Reserved1;
 213    UCHAR DmaRequest;
 214    UCHAR Reserved2;
 215    UCHAR SingleMask;
 216    UCHAR Reserved3;
 217    UCHAR Mode;
 218    UCHAR Reserved4;
 219    UCHAR ClearBytePointer;
 220    UCHAR Reserved5;
 221    UCHAR MasterClear;
 222    UCHAR Reserved6;
 223    UCHAR ClearMask;
 224    UCHAR Reserved7;
 225    UCHAR AllMask;
 226    UCHAR Reserved8;
 227 } DMA2_CONTROL, *PDMA2_CONTROL;
 228
 229 /* This structure defines the I/O Map of the 82537 controller. */
 230 typedef struct _EISA_CONTROL
 231 {
 232    /* DMA Controller 1 */
 233    DMA1_CONTROL DmaController1;         /* 00h-0Fh */
 234    UCHAR Reserved1[16];                 /* 0Fh-1Fh */
 235
 236    /* Interrupt Controller 1 (PIC) */
 237    UCHAR Pic1Operation;                 /* 20h     */
 238    UCHAR Pic1Interrupt;                 /* 21h     */
 239    UCHAR Reserved2[30];                 /* 22h-3Fh */
 240
 241    /* Timer */
 242    UCHAR TimerCounter;                  /* 40h     */
 243    UCHAR TimerMemoryRefresh;            /* 41h     */
 244    UCHAR Speaker;                       /* 42h     */
 245    UCHAR TimerOperation;                /* 43h     */
 246    UCHAR TimerMisc;                     /* 44h     */
 247    UCHAR Reserved3[2];                  /* 45-46h  */
 248    UCHAR TimerCounterControl;           /* 47h     */
 249    UCHAR TimerFailSafeCounter;          /* 48h     */
 250    UCHAR Reserved4;                     /* 49h     */
 251    UCHAR TimerCounter2;                 /* 4Ah     */
 252    UCHAR TimerOperation2;               /* 4Bh     */
 253    UCHAR Reserved5[20];                 /* 4Ch-5Fh */
 254
 255    /* NMI / Keyboard / RTC */
 256    UCHAR Keyboard;                      /* 60h     */
 257    UCHAR NmiStatus;                     /* 61h     */
 258    UCHAR Reserved6[14];                 /* 62h-6Fh */
 259    UCHAR NmiEnable;                     /* 70h     */
 260    UCHAR Reserved7[15];                 /* 71h-7Fh */
 261
 262    /* DMA Page Registers Controller 1 */
 263    DMA_PAGE DmaController1Pages;        /* 80h-8Fh */
 264    UCHAR Reserved8[16];                 /* 90h-9Fh */
 265
 266     /* Interrupt Controller 2 (PIC) */
 267    UCHAR Pic2Operation;                 /* 0A0h      */
 268    UCHAR Pic2Interrupt;                 /* 0A1h      */
 269    UCHAR Reserved9[30];                 /* 0A2h-0BFh */
 270
 271    /* DMA Controller 2 */
 272    DMA1_CONTROL DmaController2;         /* 0C0h-0CFh */
 273
 274    /* System Reserved Ports */
 275    UCHAR SystemReserved[816];           /* 0D0h-3FFh */
 276
 277    /* Extended DMA Registers, Controller 1 */
 278    UCHAR DmaHighByteCount1[8];          /* 400h-407h */
 279    UCHAR Reserved10[2];                 /* 408h-409h */
 280    UCHAR DmaChainMode1;                 /* 40Ah      */
 281    UCHAR DmaExtendedMode1;              /* 40Bh      */
 282    UCHAR DmaBufferControl;              /* 40Ch      */
 283    UCHAR Reserved11[84];                /* 40Dh-460h */
 284    UCHAR ExtendedNmiControl;            /* 461h      */
 285    UCHAR NmiCommand;                    /* 462h      */
 286    UCHAR Reserved12;                    /* 463h      */
 287    UCHAR BusMaster;                     /* 464h      */
 288    UCHAR Reserved13[27];                /* 465h-47Fh */
 289
 290    /* DMA Page Registers Controller 2 */
 291    DMA_PAGE DmaController2Pages;        /* 480h-48Fh */
 292    UCHAR Reserved14[48];                /* 490h-4BFh */
 293
 294    /* Extended DMA Registers, Controller 2 */
 295    UCHAR DmaHighByteCount2[16];         /* 4C0h-4CFh */
 296
 297    /* Edge/Level Control Registers */
 298    UCHAR Pic1EdgeLevel;                 /* 4D0h      */
 299    UCHAR Pic2EdgeLevel;                 /* 4D1h      */
 300    UCHAR Reserved15[2];                 /* 4D2h-4D3h */
 301
 302    /* Extended DMA Registers, Controller 2 */
 303    UCHAR DmaChainMode2;                 /* 4D4h      */
 304    UCHAR Reserved16;                    /* 4D5h      */
 305    UCHAR DmaExtendedMode2;              /* 4D6h      */
 306    UCHAR Reserved17[9];                 /* 4D7h-4DFh */
 307
 308    /* DMA Stop Registers */
 309    DMA_CHANNEL_STOP DmaChannelStop[8];  /* 4E0h-4FFh */
 310 } EISA_CONTROL, *PEISA_CONTROL;
 311
 312 typedef struct _ROS_MAP_REGISTER_ENTRY
 313 {
 314    PVOID VirtualAddress;
 315    PHYSICAL_ADDRESS PhysicalAddress;
 316    ULONG Counter;
 317 } ROS_MAP_REGISTER_ENTRY, *PROS_MAP_REGISTER_ENTRY;
 318
 319 typedef struct _ADAPTER_OBJECT {
 320    /*
 321     * New style DMA object definition. The fact that it is at the beginning
 322     * of the ADAPTER_OBJECT structure allows us to easily implement the
 323     * fallback implementation of IoGetDmaAdapter.
 324     */
 325    DMA_ADAPTER DmaHeader;
 326
 327    /*
 328     * For normal adapter objects pointer to master adapter that takes care
 329     * of channel allocation. For master adapter set to NULL.
 330     */
 331    struct _ADAPTER_OBJECT *MasterAdapter;
 332
 333    ULONG MapRegistersPerChannel;
 334    PVOID AdapterBaseVa;
 335    PROS_MAP_REGISTER_ENTRY MapRegisterBase;
 336
 337    ULONG NumberOfMapRegisters;
 338    ULONG CommittedMapRegisters;
 339
 340    PWAIT_CONTEXT_BLOCK CurrentWcb;
 341    KDEVICE_QUEUE ChannelWaitQueue;
 342    PKDEVICE_QUEUE RegisterWaitQueue;
 343    LIST_ENTRY AdapterQueue;
 344    KSPIN_LOCK SpinLock;
 345    PRTL_BITMAP MapRegisters;
 346    PUCHAR PagePort;
 347    UCHAR ChannelNumber;
 348    UCHAR AdapterNumber;
 349    USHORT DmaPortAddress;
 350    DMA_MODE AdapterMode;
 351    BOOLEAN NeedsMapRegisters;
 352    BOOLEAN MasterDevice;
 353    BOOLEAN Width16Bits;
 354    BOOLEAN ScatterGather;
 355    BOOLEAN IgnoreCount;
 356    BOOLEAN Dma32BitAddresses;
 357    BOOLEAN Dma64BitAddresses;
 358    LIST_ENTRY AdapterList;
 359 } ADAPTER_OBJECT;
 360
 361 typedef struct _GROW_WORK_ITEM {
 362    WORK_QUEUE_ITEM WorkQueueItem;
 363    PADAPTER_OBJECT AdapterObject;
 364    ULONG NumberOfMapRegisters;
 365 } GROW_WORK_ITEM, *PGROW_WORK_ITEM;
 366
 367 #define MAP_BASE_SW_SG 1
 368
 369 PADAPTER_OBJECT NTAPI
 370 HalpDmaAllocateMasterAdapter(VOID);
 371
 372 PDMA_ADAPTER NTAPI
 373 HalpGetDmaAdapter(
 374    IN PVOID Context,
 375    IN PDEVICE_DESCRIPTION DeviceDescription,
 376    OUT PULONG NumberOfMapRegisters);
 377
 378 ULONG NTAPI
 379 HalpDmaGetDmaAlignment(
 380    PADAPTER_OBJECT AdapterObject);