reactos/hal/halx86/apic/apic.h

   1
   2 #ifdef _M_AMD64
   3 #define IOAPIC_BASE 0xFFFFFFFFFFFE1000ULL // checkme
   4 #define ZERO_VECTOR          0x00 // IRQL 00
   5 #define APC_VECTOR           0x3D // IRQL 01
   6 #define APIC_SPURIOUS_VECTOR 0x3f
   7 #define DISPATCH_VECTOR      0x41 // IRQL 02
   8 #define APIC_GENERIC_VECTOR  0xC1 // IRQL 27
   9 #define APIC_CLOCK_VECTOR    0xD1 // IRQL 28
  10 #define APIC_SYNCH_VECTOR    0xD1 // IRQL 28
  11 #define APIC_IPI_VECTOR      0xE1 // IRQL 29
  12 #define APIC_ERROR_VECTOR    0xE3
  13 #define POWERFAIL_VECTOR     0xEF // IRQL 30
  14 #define APIC_PROFILE_VECTOR  0xFD // IRQL 31
  15 #define APIC_NMI_VECTOR      0xFF
  16 #define IrqlToTpr(Irql) (Irql << 4)
  17 #define IrqlToSoftVector(Irql) ((Irql << 4)|0xf)
  18 #define TprToIrql(Tpr) ((KIRQL)(Tpr >> 4))
  19 #define CLOCK2_LEVEL CLOCK_LEVEL
  20 #else
  21 #define IOAPIC_BASE 0xFFFE1000 // checkme
  22 #define ZERO_VECTOR          0x00 // IRQL 00
  23 #define APIC_SPURIOUS_VECTOR 0x1f
  24 #define APC_VECTOR           0x3D // IRQL 01
  25 #define DISPATCH_VECTOR      0x41 // IRQL 02
  26 #define APIC_GENERIC_VECTOR  0xC1 // IRQL 27
  27 #define APIC_CLOCK_VECTOR    0xD1 // IRQL 28
  28 #define APIC_SYNCH_VECTOR    0xD1 // IRQL 28
  29 #define APIC_IPI_VECTOR      0xE1 // IRQL 29
  30 #define APIC_ERROR_VECTOR    0xE3
  31 #define POWERFAIL_VECTOR     0xEF // IRQL 30
  32 #define APIC_PROFILE_VECTOR  0xFD // IRQL 31
  33 #define APIC_NMI_VECTOR      0xFF
  34 #define IrqlToTpr(Irql) (HalpIRQLtoTPR[Irql])
  35 #define IrqlToSoftVector(Irql) IrqlToTpr(Irql)
  36 #define TprToIrql(Tpr)  (HalVectorToIRQL[Tpr >> 4])
  37 #endif
  38
  39 #define MSR_APIC_BASE 0x0000001B
  40 #define IOAPIC_PHYS_BASE 0xFEC00000
  41 #define APIC_CLOCK_INDEX 8
  42
  43 #define ApicLogicalId(Cpu) ((UCHAR)(1<< Cpu))
  44
  45 /* APIC Register Address Map */
  46 #define APIC_ID       0x0020 /* Local APIC ID Register (R/W) */
  47 #define APIC_VER      0x0030 /* Local APIC Version Register (R) */
  48 #define APIC_TPR      0x0080 /* Task Priority Register (R/W) */
  49 #define APIC_APR      0x0090 /* Arbitration Priority Register (R) */
  50 #define APIC_PPR      0x00A0 /* Processor Priority Register (R) */
  51 #define APIC_EOI      0x00B0 /* EOI Register (W) */
  52 #define APIC_RRR      0x00C0 /* Remote Read Register () */
  53 #define APIC_LDR      0x00D0 /* Logical Destination Register (R/W) */
  54 #define APIC_DFR      0x00E0 /* Destination Format Register (0-27 R, 28-31 R/W) */
  55 #define APIC_SIVR     0x00F0 /* Spurious Interrupt Vector Register (0-3 R, 4-9 R/W) */
  56 #define APIC_ISR      0x0100 /* Interrupt Service Register 0-255 (R) */
  57 #define APIC_TMR      0x0180 /* Trigger Mode Register 0-255 (R) */
  58 #define APIC_IRR      0x0200 /* Interrupt Request Register 0-255 (r) */
  59 #define APIC_ESR      0x0280 /* Error Status Register (R) */
  60 #define APIC_ICR0     0x0300 /* Interrupt Command Register 0-31 (R/W) */
  61 #define APIC_ICR1     0x0310 /* Interrupt Command Register 32-63 (R/W) */
  62 #define APIC_TMRLVTR  0x0320 /* Timer Local Vector Table (R/W) */
  63 #define APIC_THRMLVTR 0x0330 /* Thermal Local Vector Table */
  64 #define APIC_PCLVTR   0x0340 /* Performance Counter Local Vector Table (R/W) */
  65 #define APIC_LINT0    0x0350 /* LINT0 Local Vector Table (R/W) */
  66 #define APIC_LINT1    0x0360 /* LINT1 Local Vector Table (R/W) */
  67 #define APIC_ERRLVTR  0x0370 /* Error Local Vector Table (R/W) */
  68 #define APIC_TICR     0x0380 /* Initial Count Register for Timer (R/W) */
  69 #define APIC_TCCR     0x0390 /* Current Count Register for Timer (R) */
  70 #define APIC_TDCR     0x03E0 /* Timer Divide Configuration Register (R/W) */
  71 #define APIC_EAFR     0x0400 /* extended APIC Feature register (R/W) */
  72 #define APIC_EACR     0x0410 /* Extended APIC Control Register (R/W) */
  73 #define APIC_SEOI     0x0420 /* Specific End Of Interrupt Register (W) */
  74 #define APIC_EXT0LVTR 0x0500 /* Extended Interrupt 0 Local Vector Table */
  75 #define APIC_EXT1LVTR 0x0510 /* Extended Interrupt 1 Local Vector Table */
  76 #define APIC_EXT2LVTR 0x0520 /* Extended Interrupt 2 Local Vector Table */
  77 #define APIC_EXT3LVTR 0x0530 /* Extended Interrupt 3 Local Vector Table */
  78
  79 enum
  80 {
  81     APIC_MT_Fixed = 0,
  82     APIC_MT_LowestPriority = 1,
  83     APIC_MT_SMI = 2,
  84     APIC_MT_RemoteRead = 3,
  85     APIC_MT_NMI = 4,
  86     APIC_MT_INIT = 5,
  87     APIC_MT_Startup = 6,
  88     APIC_MT_ExtInt = 7,
  89 };
  90
  91 enum
  92 {
  93     APIC_TGM_Edge,
  94     APIC_TGM_Level
  95 };
  96
  97 enum
  98 {
  99     APIC_DM_Physical,
 100     APIC_DM_Logical
 101 };
 102
 103 enum
 104 {
 105     APIC_DSH_Destination,
 106     APIC_DSH_Self,
 107     APIC_DSH_AllIncludingSelf,
 108     APIC_DSH_AllExclusingSelf
 109 };
 110
 111 enum
 112 {
 113     APIC_DF_Flat = 0xFFFFFFFF,
 114     APIC_DF_Cluster = 0x0FFFFFFF
 115 };
 116
 117 enum
 118 {
 119     TIMER_DV_DivideBy2 = 0,
 120     TIMER_DV_DivideBy4 = 1,
 121     TIMER_DV_DivideBy8 = 2,
 122     TIMER_DV_DivideBy16 = 3,
 123     TIMER_DV_DivideBy32 = 8,
 124     TIMER_DV_DivideBy64 = 9,
 125     TIMER_DV_DivideBy128 = 10,
 126     TIMER_DV_DivideBy1 = 11,
 127 };
 128
 129
 130 typedef union _APIC_BASE_ADRESS_REGISTER
 131 {
 132     ULONG64 Long;
 133     struct
 134     {
 135         ULONG64 Reserved1:8;
 136         ULONG64 BootStrapCPUCore:1;
 137         ULONG64 Reserved2:2;
 138         ULONG64 Enable:1;
 139         ULONG64 BaseAddress:40;
 140         ULONG64 ReservedMBZ:12;
 141     };
 142 } APIC_BASE_ADRESS_REGISTER;
 143
 144 typedef union _APIC_SPURIOUS_INERRUPT_REGISTER
 145 {
 146     ULONG Long;
 147     struct
 148     {
 149         ULONG Vector:8;
 150         ULONG SoftwareEnable:1;
 151         ULONG FocusCPUCoreChecking:1;
 152         ULONG ReservedMBZ:22;
 153     };
 154 } APIC_SPURIOUS_INERRUPT_REGISTER;
 155
 156 typedef union
 157 {
 158     ULONG Long;
 159     struct
 160     {
 161         ULONG Version:8;
 162         ULONG ReservedMBZ:8;
 163         ULONG MaxLVT:8;
 164         ULONG ReservedMBZ1:7;
 165         ULONG ExtRegSpacePresent:1;
 166     };
 167 } APIC_VERSION_REGISTER;
 168
 169 typedef union
 170 {
 171     ULONG Long;
 172     struct
 173     {
 174         ULONG Version:1;
 175         ULONG SEOIEnable:1;
 176         ULONG ExtApicIdEnable:1;
 177         ULONG ReservedMBZ:29;
 178     };
 179 } APIC_EXTENDED_CONTROL_REGISTER;
 180
 181 typedef union _APIC_COMMAND_REGISTER
 182 {
 183     ULONGLONG LongLong;
 184     struct
 185     {
 186         ULONG Long0;
 187         ULONG Long1;
 188     };
 189     struct
 190     {
 191         ULONGLONG Vector:8;
 192         ULONGLONG MessageType:3;
 193         ULONGLONG DestinationMode:1;
 194         ULONGLONG DeliveryStatus:1;
 195         ULONGLONG ReservedMBZ:1;
 196         ULONGLONG Level:1;
 197         ULONGLONG TriggerMode:1;
 198         ULONGLONG RemoteReadStatus:2;
 199         ULONGLONG DestinationShortHand:2;
 200         ULONGLONG Reserved2MBZ:36;
 201         ULONGLONG Destination:8;
 202     };
 203 } APIC_COMMAND_REGISTER;
 204
 205 typedef union
 206 {
 207     ULONG Long;
 208     struct
 209     {
 210         ULONG Vector:8;
 211         ULONG MessageType:3;
 212         ULONG ReservedMBZ:1;
 213         ULONG DeliveryStatus:1;
 214         ULONG Reserved1MBZ:1;
 215         ULONG RemoteIRR:1;
 216         ULONG TriggerMode:1;
 217         ULONG Mask:1;
 218         ULONG TimerMode:1;
 219         ULONG Reserved2MBZ:13;
 220     };
 221 } LVT_REGISTER;
 222
 223
 224 enum
 225 {
 226     IOAPIC_IOREGSEL = 0x00,
 227     IOAPIC_IOWIN    = 0x10
 228 };
 229
 230 enum
 231 {
 232     IOAPIC_ID  = 0x00,
 233     IOAPIC_VER = 0x01,
 234     IOAPIC_ARB = 0x02,
 235     IOAPIC_REDTBL = 0x10
 236 };
 237
 238 typedef union _IOAPIC_REDIRECTION_REGISTER
 239 {
 240     ULONGLONG LongLong;
 241     struct
 242     {
 243         ULONG Long0;
 244         ULONG Long1;
 245     };
 246     struct
 247     {
 248         ULONGLONG Vector:8;
 249         ULONGLONG DeliveryMode:3;
 250         ULONGLONG DestinationMode:1;
 251         ULONGLONG DeliveryStatus:1;
 252         ULONGLONG Polarity:1;
 253         ULONGLONG RemoteIRR:1;
 254         ULONGLONG TriggerMode:1;
 255         ULONGLONG Mask:1;
 256         ULONGLONG Reserved:39;
 257         ULONGLONG Destination:8;
 258     };
 259 } IOAPIC_REDIRECTION_REGISTER;
 260
 261 FORCEINLINE
 262 ULONG
 263 ApicRead(ULONG Offset)
 264 {
 265     return *(volatile ULONG *)(APIC_BASE + Offset);
 266 }
 267
 268 FORCEINLINE
 269 VOID
 270 ApicWrite(ULONG Offset, ULONG Value)
 271 {
 272     *(volatile ULONG *)(APIC_BASE + Offset) = Value;
 273 }
 274
 275 VOID
 276 NTAPI
 277 ApicInitializeTimer(ULONG Cpu);
 278
 279 VOID __cdecl ApicSpuriousService(VOID);
 280