reactos/hal/halx86/generic/legacy/bus/pcibus.c

   1 /*
   2  * PROJECT:         ReactOS HAL
   3  * LICENSE:         GPL - See COPYING in the top level directory
   4  * FILE:            hal/halx86/generic/bus/pcibus.c
   5  * PURPOSE:         PCI Bus Support (Configuration Space, Resource Allocation)
   6  * PROGRAMMERS:     Alex Ionescu (alex.ionescu@reactos.org)
   7  */
   8
   9 /* INCLUDES ******************************************************************/
  10
  11 #include <hal.h>
  12 #define NDEBUG
  13 #include <debug.h>
  14
  15 /* GLOBALS *******************************************************************/
  16
  17 ULONG HalpBusType;
  18
  19 PCI_TYPE1_CFG_CYCLE_BITS HalpPciDebuggingDevice[2] = {{{{0}}}};
  20
  21 BOOLEAN HalpPCIConfigInitialized;
  22 ULONG HalpMinPciBus, HalpMaxPciBus;
  23 KSPIN_LOCK HalpPCIConfigLock;
  24 PCI_CONFIG_HANDLER PCIConfigHandler;
  25
  26 /* PCI Operation Matrix */
  27 UCHAR PCIDeref[4][4] =
  28 {
  29     {0, 1, 2, 2},   // ULONG-aligned offset
  30     {1, 1, 1, 1},   // UCHAR-aligned offset
  31     {2, 1, 2, 2},   // USHORT-aligned offset
  32     {1, 1, 1, 1}    // UCHAR-aligned offset
  33 };
  34
  35 /* Type 1 PCI Bus */
  36 PCI_CONFIG_HANDLER PCIConfigHandlerType1 =
  37 {
  38     /* Synchronization */
  39     (FncSync)HalpPCISynchronizeType1,
  40     (FncReleaseSync)HalpPCIReleaseSynchronzationType1,
  41
  42     /* Read */
  43     {
  44         (FncConfigIO)HalpPCIReadUlongType1,
  45         (FncConfigIO)HalpPCIReadUcharType1,
  46         (FncConfigIO)HalpPCIReadUshortType1
  47     },
  48
  49     /* Write */
  50     {
  51         (FncConfigIO)HalpPCIWriteUlongType1,
  52         (FncConfigIO)HalpPCIWriteUcharType1,
  53         (FncConfigIO)HalpPCIWriteUshortType1
  54     }
  55 };
  56
  57 /* Type 2 PCI Bus */
  58 PCI_CONFIG_HANDLER PCIConfigHandlerType2 =
  59 {
  60     /* Synchronization */
  61     (FncSync)HalpPCISynchronizeType2,
  62     (FncReleaseSync)HalpPCIReleaseSynchronizationType2,
  63
  64     /* Read */
  65     {
  66         (FncConfigIO)HalpPCIReadUlongType2,
  67         (FncConfigIO)HalpPCIReadUcharType2,
  68         (FncConfigIO)HalpPCIReadUshortType2
  69     },
  70
  71     /* Write */
  72     {
  73         (FncConfigIO)HalpPCIWriteUlongType2,
  74         (FncConfigIO)HalpPCIWriteUcharType2,
  75         (FncConfigIO)HalpPCIWriteUshortType2
  76     }
  77 };
  78
  79 PCIPBUSDATA HalpFakePciBusData =
  80 {
  81     {
  82         PCI_DATA_TAG,
  83         PCI_DATA_VERSION,
  84         HalpReadPCIConfig,
  85         HalpWritePCIConfig,
  86         NULL,
  87         NULL,
  88         {{{0, 0, 0}}},
  89         {0, 0, 0, 0}
  90     },
  91     {{0, 0}},
  92     32,
  93 };
  94
  95 BUS_HANDLER HalpFakePciBusHandler =
  96 {
  97     1,
  98     PCIBus,
  99     PCIConfiguration,
 100     0,
 101     NULL,
 102     NULL,
 103     &HalpFakePciBusData,
 104     0,
 105     NULL,
 106     {0, 0, 0, 0},
 107     (PGETSETBUSDATA)HalpGetPCIData,
 108     (PGETSETBUSDATA)HalpSetPCIData,
 109     NULL,
 110     HalpAssignPCISlotResources,
 111     NULL,
 112     NULL
 113 };
 114
 115 /* TYPE 1 FUNCTIONS **********************************************************/
 116
 117 VOID
 118 NTAPI
 119 HalpPCISynchronizeType1(IN PBUS_HANDLER BusHandler,
 120                         IN PCI_SLOT_NUMBER Slot,
 121                         IN PKIRQL Irql,
 122                         IN PPCI_TYPE1_CFG_BITS PciCfg1)
 123 {
 124     /* Setup the PCI Configuration Register */
 125     PciCfg1->u.AsULONG = 0;
 126     PciCfg1->u.bits.BusNumber = BusHandler->BusNumber;
 127     PciCfg1->u.bits.DeviceNumber = Slot.u.bits.DeviceNumber;
 128     PciCfg1->u.bits.FunctionNumber = Slot.u.bits.FunctionNumber;
 129     PciCfg1->u.bits.Enable = TRUE;
 130
 131     /* Acquire the lock */
 132     KeRaiseIrql(HIGH_LEVEL, Irql);
 133     KiAcquireSpinLock(&HalpPCIConfigLock);
 134 }
 135
 136 VOID
 137 NTAPI
 138 HalpPCIReleaseSynchronzationType1(IN PBUS_HANDLER BusHandler,
 139                                   IN KIRQL Irql)
 140 {
 141     PCI_TYPE1_CFG_BITS PciCfg1;
 142
 143     /* Clear the PCI Configuration Register */
 144     PciCfg1.u.AsULONG = 0;
 145     WRITE_PORT_ULONG(((PPCIPBUSDATA)BusHandler->BusData)->Config.Type1.Address,
 146                      PciCfg1.u.AsULONG);
 147
 148     /* Release the lock */
 149     KiReleaseSpinLock(&HalpPCIConfigLock);
 150     KeLowerIrql(Irql);
 151 }
 152
 153 TYPE1_READ(HalpPCIReadUcharType1, UCHAR)
 154 TYPE1_READ(HalpPCIReadUshortType1, USHORT)
 155 TYPE1_READ(HalpPCIReadUlongType1, ULONG)
 156 TYPE1_WRITE(HalpPCIWriteUcharType1, UCHAR)
 157 TYPE1_WRITE(HalpPCIWriteUshortType1, USHORT)
 158 TYPE1_WRITE(HalpPCIWriteUlongType1, ULONG)
 159
 160 /* TYPE 2 FUNCTIONS **********************************************************/
 161
 162 VOID
 163 NTAPI
 164 HalpPCISynchronizeType2(IN PBUS_HANDLER BusHandler,
 165                         IN PCI_SLOT_NUMBER Slot,
 166                         IN PKIRQL Irql,
 167                         IN PPCI_TYPE2_ADDRESS_BITS PciCfg)
 168 {
 169     PCI_TYPE2_CSE_BITS PciCfg2Cse;
 170     PPCIPBUSDATA BusData = (PPCIPBUSDATA)BusHandler->BusData;
 171
 172     /* Setup the configuration register */
 173     PciCfg->u.AsUSHORT = 0;
 174     PciCfg->u.bits.Agent = (USHORT)Slot.u.bits.DeviceNumber;
 175     PciCfg->u.bits.AddressBase = (USHORT)BusData->Config.Type2.Base;
 176
 177     /* Acquire the lock */
 178     KeRaiseIrql(HIGH_LEVEL, Irql);
 179     KiAcquireSpinLock(&HalpPCIConfigLock);
 180
 181     /* Setup the CSE Register */
 182     PciCfg2Cse.u.AsUCHAR = 0;
 183     PciCfg2Cse.u.bits.Enable = TRUE;
 184     PciCfg2Cse.u.bits.FunctionNumber = (UCHAR)Slot.u.bits.FunctionNumber;
 185     PciCfg2Cse.u.bits.Key = -1;
 186
 187     /* Write the bus number and CSE */
 188     WRITE_PORT_UCHAR(BusData->Config.Type2.Forward,
 189                      (UCHAR)BusHandler->BusNumber);
 190     WRITE_PORT_UCHAR(BusData->Config.Type2.CSE, PciCfg2Cse.u.AsUCHAR);
 191 }
 192
 193 VOID
 194 NTAPI
 195 HalpPCIReleaseSynchronizationType2(IN PBUS_HANDLER BusHandler,
 196                                    IN KIRQL Irql)
 197 {
 198     PCI_TYPE2_CSE_BITS PciCfg2Cse;
 199     PPCIPBUSDATA BusData = (PPCIPBUSDATA)BusHandler->BusData;
 200
 201     /* Clear CSE and bus number */
 202     PciCfg2Cse.u.AsUCHAR = 0;
 203     WRITE_PORT_UCHAR(BusData->Config.Type2.CSE, PciCfg2Cse.u.AsUCHAR);
 204     WRITE_PORT_UCHAR(BusData->Config.Type2.Forward, 0);
 205
 206     /* Release the lock */
 207     KiReleaseSpinLock(&HalpPCIConfigLock);
 208     KeLowerIrql(Irql);
 209 }
 210
 211 TYPE2_READ(HalpPCIReadUcharType2, UCHAR)
 212 TYPE2_READ(HalpPCIReadUshortType2, USHORT)
 213 TYPE2_READ(HalpPCIReadUlongType2, ULONG)
 214 TYPE2_WRITE(HalpPCIWriteUcharType2, UCHAR)
 215 TYPE2_WRITE(HalpPCIWriteUshortType2, USHORT)
 216 TYPE2_WRITE(HalpPCIWriteUlongType2, ULONG)
 217
 218 /* PCI CONFIGURATION SPACE ***************************************************/
 219
 220 VOID
 221 NTAPI
 222 HalpPCIConfig(IN PBUS_HANDLER BusHandler,
 223               IN PCI_SLOT_NUMBER Slot,
 224               IN PUCHAR Buffer,
 225               IN ULONG Offset,
 226               IN ULONG Length,
 227               IN FncConfigIO *ConfigIO)
 228 {
 229     KIRQL OldIrql;
 230     ULONG i;
 231     UCHAR State[20];
 232
 233     /* Synchronize the operation */
 234     PCIConfigHandler.Synchronize(BusHandler, Slot, &OldIrql, State);
 235
 236     /* Loop every increment */
 237     while (Length)
 238     {
 239         /* Find out the type of read/write we need to do */
 240         i = PCIDeref[Offset % sizeof(ULONG)][Length % sizeof(ULONG)];
 241
 242         /* Do the read/write and return the number of bytes */
 243         i = ConfigIO[i]((PPCIPBUSDATA)BusHandler->BusData,
 244                         State,
 245                         Buffer,
 246                         Offset);
 247
 248         /* Increment the buffer position and offset, and decrease the length */
 249         Offset += i;
 250         Buffer += i;
 251         Length -= i;
 252     }
 253
 254     /* Release the lock and PCI bus */
 255     PCIConfigHandler.ReleaseSynchronzation(BusHandler, OldIrql);
 256 }
 257
 258 VOID
 259 NTAPI
 260 HalpReadPCIConfig(IN PBUS_HANDLER BusHandler,
 261                   IN PCI_SLOT_NUMBER Slot,
 262                   IN PVOID Buffer,
 263                   IN ULONG Offset,
 264                   IN ULONG Length)
 265 {
 266     /* Validate the PCI Slot */
 267     if (!HalpValidPCISlot(BusHandler, Slot))
 268     {
 269         /* Fill the buffer with invalid data */
 270         RtlFillMemory(Buffer, Length, -1);
 271     }
 272     else
 273     {
 274         /* Send the request */
 275         HalpPCIConfig(BusHandler,
 276                       Slot,
 277                       Buffer,
 278                       Offset,
 279                       Length,
 280                       PCIConfigHandler.ConfigRead);
 281     }
 282 }
 283
 284 VOID
 285 NTAPI
 286 HalpWritePCIConfig(IN PBUS_HANDLER BusHandler,
 287                    IN PCI_SLOT_NUMBER Slot,
 288                    IN PVOID Buffer,
 289                    IN ULONG Offset,
 290                    IN ULONG Length)
 291 {
 292     /* Validate the PCI Slot */
 293     if (HalpValidPCISlot(BusHandler, Slot))
 294     {
 295         /* Send the request */
 296         HalpPCIConfig(BusHandler,
 297                       Slot,
 298                       Buffer,
 299                       Offset,
 300                       Length,
 301                       PCIConfigHandler.ConfigWrite);
 302     }
 303 }
 304
 305 BOOLEAN
 306 NTAPI
 307 HalpValidPCISlot(IN PBUS_HANDLER BusHandler,
 308                  IN PCI_SLOT_NUMBER Slot)
 309 {
 310     PCI_SLOT_NUMBER MultiSlot;
 311     PPCIPBUSDATA BusData = (PPCIPBUSDATA)BusHandler->BusData;
 312     UCHAR HeaderType;
 313     ULONG Device;
 314
 315     /* Simple validation */
 316     if (Slot.u.bits.Reserved) return FALSE;
 317     if (Slot.u.bits.DeviceNumber >= BusData->MaxDevice) return FALSE;
 318
 319     /* Function 0 doesn't need checking */
 320     if (!Slot.u.bits.FunctionNumber) return TRUE;
 321
 322     /* Functions 0+ need Multi-Function support, so check the slot */
 323     Device = Slot.u.bits.DeviceNumber;
 324     MultiSlot = Slot;
 325     MultiSlot.u.bits.FunctionNumber = 0;
 326
 327     /* Send function 0 request to get the header back */
 328     HalpReadPCIConfig(BusHandler,
 329                       MultiSlot,
 330                       &HeaderType,
 331                       FIELD_OFFSET(PCI_COMMON_CONFIG, HeaderType),
 332                       sizeof(UCHAR));
 333
 334     /* Now make sure the header is multi-function */
 335     if (!(HeaderType & PCI_MULTIFUNCTION) || (HeaderType == 0xFF)) return FALSE;
 336     return TRUE;
 337 }
 338
 339 /* HAL PCI CALLBACKS *********************************************************/
 340
 341 ULONG
 342 NTAPI
 343 HalpGetPCIData(IN PBUS_HANDLER BusHandler,
 344                IN PBUS_HANDLER RootHandler,
 345                IN PCI_SLOT_NUMBER Slot,
 346                IN PVOID Buffer,
 347                IN ULONG Offset,
 348                IN ULONG Length)
 349 {
 350     UCHAR PciBuffer[PCI_COMMON_HDR_LENGTH];
 351     PPCI_COMMON_CONFIG PciConfig = (PPCI_COMMON_CONFIG)PciBuffer;
 352     ULONG Len = 0;
 353
 354 #ifdef SARCH_XBOX
 355     /* Trying to get PCI config data from devices 0:0:1 and 0:0:2 will completely
 356      * hang the Xbox. Also, the device number doesn't seem to be decoded for the
 357      * video card, so it appears to be present on 1:0:0 - 1:31:0.
 358      * We hack around these problems by indicating "device not present" for devices
 359      * 0:0:1, 0:0:2, 1:1:0, 1:2:0, 1:3:0, ...., 1:31:0 */
 360     if ((0 == BusHandler->BusNumber && 0 == Slot.u.bits.DeviceNumber &&
 361          (1 == Slot.u.bits.FunctionNumber || 2 == Slot.u.bits.FunctionNumber)) ||
 362         (1 == BusHandler->BusNumber && 0 != Slot.u.bits.DeviceNumber))
 363     {
 364         DPRINT("Blacklisted PCI slot\n");
 365         if (0 == Offset && sizeof(USHORT) <= Length)
 366         {
 367             *(PUSHORT)Buffer = PCI_INVALID_VENDORID;
 368             return sizeof(USHORT);
 369         }
 370         return 0;
 371     }
 372 #endif
 373
 374     /* Normalize the length */
 375     if (Length > sizeof(PCI_COMMON_CONFIG)) Length = sizeof(PCI_COMMON_CONFIG);
 376
 377     /* Check if this is a vendor-specific read */
 378     if (Offset >= PCI_COMMON_HDR_LENGTH)
 379     {
 380         /* Read the header */
 381         HalpReadPCIConfig(BusHandler, Slot, PciConfig, 0, sizeof(ULONG));
 382
 383         /* Make sure the vendor is valid */
 384         if (PciConfig->VendorID == PCI_INVALID_VENDORID) return 0;
 385     }
 386     else
 387     {
 388         /* Read the entire header */
 389         Len = PCI_COMMON_HDR_LENGTH;
 390         HalpReadPCIConfig(BusHandler, Slot, PciConfig, 0, Len);
 391
 392         /* Validate the vendor ID */
 393         if (PciConfig->VendorID == PCI_INVALID_VENDORID)
 394         {
 395             /* It's invalid, but we want to return this much */
 396             Len = sizeof(USHORT);
 397         }
 398
 399         /* Now check if there's space left */
 400         if (Len < Offset) return 0;
 401
 402         /* There is, so return what's after the offset and normalize */
 403         Len -= Offset;
 404         if (Len > Length) Len = Length;
 405
 406         /* Copy the data into the caller's buffer */
 407         RtlMoveMemory(Buffer, PciBuffer + Offset, Len);
 408
 409         /* Update buffer and offset, decrement total length */
 410         Offset += Len;
 411         Buffer = (PVOID)((ULONG_PTR)Buffer + Len);
 412         Length -= Len;
 413     }
 414
 415     /* Now we still have something to copy */
 416     if (Length)
 417     {
 418         /* Check if it's vendor-specific data */
 419         if (Offset >= PCI_COMMON_HDR_LENGTH)
 420         {
 421             /* Read it now */
 422             HalpReadPCIConfig(BusHandler, Slot, Buffer, Offset, Length);
 423             Len += Length;
 424         }
 425     }
 426
 427     /* Update the total length read */
 428     return Len;
 429 }
 430
 431 ULONG
 432 NTAPI
 433 HalpSetPCIData(IN PBUS_HANDLER BusHandler,
 434                IN PBUS_HANDLER RootHandler,
 435                IN PCI_SLOT_NUMBER Slot,
 436                IN PVOID Buffer,
 437                IN ULONG Offset,
 438                IN ULONG Length)
 439 {
 440     UCHAR PciBuffer[PCI_COMMON_HDR_LENGTH];
 441     PPCI_COMMON_CONFIG PciConfig = (PPCI_COMMON_CONFIG)PciBuffer;
 442     ULONG Len = 0;
 443
 444 #ifdef SARCH_XBOX
 445     /* Trying to get PCI config data from devices 0:0:1 and 0:0:2 will completely
 446      * hang the Xbox. Also, the device number doesn't seem to be decoded for the
 447      * video card, so it appears to be present on 1:0:0 - 1:31:0.
 448      * We hack around these problems by indicating "device not present" for devices
 449      * 0:0:1, 0:0:2, 1:1:0, 1:2:0, 1:3:0, ...., 1:31:0 */
 450     if ((0 == BusHandler->BusNumber && 0 == Slot.u.bits.DeviceNumber &&
 451          (1 == Slot.u.bits.FunctionNumber || 2 == Slot.u.bits.FunctionNumber)) ||
 452         (1 == BusHandler->BusNumber && 0 != Slot.u.bits.DeviceNumber))
 453     {
 454         DPRINT1("Trying to set data on blacklisted PCI slot\n");
 455         return 0;
 456     }
 457 #endif
 458
 459     /* Normalize the length */
 460     if (Length > sizeof(PCI_COMMON_CONFIG)) Length = sizeof(PCI_COMMON_CONFIG);
 461
 462     /* Check if this is a vendor-specific read */
 463     if (Offset >= PCI_COMMON_HDR_LENGTH)
 464     {
 465         /* Read the header */
 466         HalpReadPCIConfig(BusHandler, Slot, PciConfig, 0, sizeof(ULONG));
 467
 468         /* Make sure the vendor is valid */
 469         if (PciConfig->VendorID == PCI_INVALID_VENDORID) return 0;
 470     }
 471     else
 472     {
 473         /* Read the entire header and validate the vendor ID */
 474         Len = PCI_COMMON_HDR_LENGTH;
 475         HalpReadPCIConfig(BusHandler, Slot, PciConfig, 0, Len);
 476         if (PciConfig->VendorID == PCI_INVALID_VENDORID) return 0;
 477
 478         /* Return what's after the offset and normalize */
 479         Len -= Offset;
 480         if (Len > Length) Len = Length;
 481
 482         /* Copy the specific caller data */
 483         RtlMoveMemory(PciBuffer + Offset, Buffer, Len);
 484
 485         /* Write the actual configuration data */
 486         HalpWritePCIConfig(BusHandler, Slot, PciBuffer + Offset, Offset, Len);
 487
 488         /* Update buffer and offset, decrement total length */
 489         Offset += Len;
 490         Buffer = (PVOID)((ULONG_PTR)Buffer + Len);
 491         Length -= Len;
 492     }
 493
 494     /* Now we still have something to copy */
 495     if (Length)
 496     {
 497         /* Check if it's vendor-specific data */
 498         if (Offset >= PCI_COMMON_HDR_LENGTH)
 499         {
 500             /* Read it now */
 501             HalpWritePCIConfig(BusHandler, Slot, Buffer, Offset, Length);
 502             Len += Length;
 503         }
 504     }
 505
 506     /* Update the total length read */
 507     return Len;
 508 }
 509
 510 NTSTATUS
 511 NTAPI
 512 HalpSetupPciDeviceForDebugging(IN PVOID LoaderBlock,
 513                                IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice)
 514 {
 515     DPRINT1("Unimplemented!\n");
 516     return STATUS_NOT_IMPLEMENTED;
 517 }
 518
 519 NTSTATUS
 520 NTAPI
 521 HalpReleasePciDeviceForDebugging(IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice)
 522 {
 523     DPRINT1("Unimplemented!\n");
 524     return STATUS_NOT_IMPLEMENTED;
 525 }
 526
 527 VOID
 528 NTAPI
 529 HalpRegisterPciDebuggingDeviceInfo(VOID)
 530 {
 531     BOOLEAN Found = FALSE;
 532     ULONG i;
 533     PAGED_CODE();
 534
 535     /* Loop PCI debugging devices */
 536     for (i = 0; i < 2; i++)
 537     {
 538         /* Reserved bit is set if we found one */
 539         if (HalpPciDebuggingDevice[i].u.bits.Reserved1)
 540         {
 541             Found = TRUE;
 542             break;
 543         }
 544     }
 545
 546     /* Bail out if there aren't any */
 547     if (!Found) return;
 548
 549     /* FIXME: TODO */
 550     DPRINT1("You have implemented the KD routines for searching PCI debugger"
 551             "devices, but you have forgotten to implement this routine\n");
 552     while (TRUE);
 553 }
 554
 555 static ULONG NTAPI
 556 PciSize(ULONG Base, ULONG Mask)
 557 {
 558     ULONG Size = Mask & Base; /* Find the significant bits */
 559     Size = Size & ~(Size - 1); /* Get the lowest of them to find the decode size */
 560     return Size;
 561 }
 562
 563 NTSTATUS
 564 NTAPI
 565 HalpAssignPCISlotResources(IN PBUS_HANDLER BusHandler,
 566                            IN PBUS_HANDLER RootHandler,
 567                            IN PUNICODE_STRING RegistryPath,
 568                            IN PUNICODE_STRING DriverClassName OPTIONAL,
 569                            IN PDRIVER_OBJECT DriverObject,
 570                            IN PDEVICE_OBJECT DeviceObject OPTIONAL,
 571                            IN ULONG Slot,
 572                            IN OUT PCM_RESOURCE_LIST *AllocatedResources)
 573 {
 574     PCI_COMMON_CONFIG PciConfig;
 575     SIZE_T Address;
 576     SIZE_T ResourceCount;
 577     ULONG Size[PCI_TYPE0_ADDRESSES];
 578     NTSTATUS Status = STATUS_SUCCESS;
 579     UCHAR Offset;
 580     PCM_PARTIAL_RESOURCE_DESCRIPTOR Descriptor;
 581     PCI_SLOT_NUMBER SlotNumber;
 582     ULONG WriteBuffer;
 583
 584     /* FIXME: Should handle 64-bit addresses */
 585
 586     /* Read configuration data */
 587     SlotNumber.u.AsULONG = Slot;
 588     HalpReadPCIConfig(BusHandler, SlotNumber, &PciConfig, 0, PCI_COMMON_HDR_LENGTH);
 589
 590     /* Check if we read it correctly */
 591     if (PciConfig.VendorID == PCI_INVALID_VENDORID)
 592         return STATUS_NO_SUCH_DEVICE;
 593
 594     /* Read the PCI configuration space for the device and store base address and
 595     size information in temporary storage. Count the number of valid base addresses */
 596     ResourceCount = 0;
 597     for (Address = 0; Address < PCI_TYPE0_ADDRESSES; Address++)
 598     {
 599         if (0xffffffff == PciConfig.u.type0.BaseAddresses[Address])
 600             PciConfig.u.type0.BaseAddresses[Address] = 0;
 601
 602         /* Memory resource */
 603         if (0 != PciConfig.u.type0.BaseAddresses[Address])
 604         {
 605             ResourceCount++;
 606
 607             Offset = (UCHAR)FIELD_OFFSET(PCI_COMMON_CONFIG, u.type0.BaseAddresses[Address]);
 608
 609             /* Write 0xFFFFFFFF there */
 610             WriteBuffer = 0xffffffff;
 611             HalpWritePCIConfig(BusHandler, SlotNumber, &WriteBuffer, Offset, sizeof(ULONG));
 612
 613             /* Read that figure back from the config space */
 614             HalpReadPCIConfig(BusHandler, SlotNumber, &Size[Address], Offset, sizeof(ULONG));
 615
 616             /* Write back initial value */
 617             HalpWritePCIConfig(BusHandler, SlotNumber, &PciConfig.u.type0.BaseAddresses[Address], Offset, sizeof(ULONG));
 618         }
 619     }
 620
 621     /* Interrupt resource */
 622     if (0 != PciConfig.u.type0.InterruptLine)
 623         ResourceCount++;
 624
 625     /* Allocate output buffer and initialize */
 626     *AllocatedResources = ExAllocatePoolWithTag(
 627         PagedPool,
 628         sizeof(CM_RESOURCE_LIST) +
 629         (ResourceCount - 1) * sizeof(CM_PARTIAL_RESOURCE_DESCRIPTOR),
 630         ' laH');
 631
 632     if (NULL == *AllocatedResources)
 633         return STATUS_NO_MEMORY;
 634
 635     (*AllocatedResources)->Count = 1;
 636     (*AllocatedResources)->List[0].InterfaceType = PCIBus;
 637     (*AllocatedResources)->List[0].BusNumber = BusHandler->BusNumber;
 638     (*AllocatedResources)->List[0].PartialResourceList.Version = 1;
 639     (*AllocatedResources)->List[0].PartialResourceList.Revision = 1;
 640     (*AllocatedResources)->List[0].PartialResourceList.Count = ResourceCount;
 641     Descriptor = (*AllocatedResources)->List[0].PartialResourceList.PartialDescriptors;
 642
 643     /* Store configuration information */
 644     for (Address = 0; Address < PCI_TYPE0_ADDRESSES; Address++)
 645     {
 646         if (0 != PciConfig.u.type0.BaseAddresses[Address])
 647         {
 648             if (PCI_ADDRESS_MEMORY_SPACE ==
 649                 (PciConfig.u.type0.BaseAddresses[Address] & 0x1))
 650             {
 651                 Descriptor->Type = CmResourceTypeMemory;
 652                 Descriptor->ShareDisposition = CmResourceShareDeviceExclusive; /* FIXME I have no idea... */
 653                 Descriptor->Flags = CM_RESOURCE_MEMORY_READ_WRITE;             /* FIXME Just a guess */
 654                 Descriptor->u.Memory.Start.QuadPart = (PciConfig.u.type0.BaseAddresses[Address] & PCI_ADDRESS_MEMORY_ADDRESS_MASK);
 655                 Descriptor->u.Memory.Length = PciSize(Size[Address], PCI_ADDRESS_MEMORY_ADDRESS_MASK);
 656             }
 657             else if (PCI_ADDRESS_IO_SPACE ==
 658                 (PciConfig.u.type0.BaseAddresses[Address] & 0x1))
 659             {
 660                 Descriptor->Type = CmResourceTypePort;
 661                 Descriptor->ShareDisposition = CmResourceShareDeviceExclusive; /* FIXME I have no idea... */
 662                 Descriptor->Flags = CM_RESOURCE_PORT_IO;                       /* FIXME Just a guess */
 663                 Descriptor->u.Port.Start.QuadPart = PciConfig.u.type0.BaseAddresses[Address] &= PCI_ADDRESS_IO_ADDRESS_MASK;
 664                 Descriptor->u.Port.Length = PciSize(Size[Address], PCI_ADDRESS_IO_ADDRESS_MASK & 0xffff);
 665             }
 666             else
 667             {
 668                 ASSERT(FALSE);
 669                 return STATUS_UNSUCCESSFUL;
 670             }
 671             Descriptor++;
 672         }
 673     }
 674
 675     if (0 != PciConfig.u.type0.InterruptLine)
 676     {
 677         Descriptor->Type = CmResourceTypeInterrupt;
 678         Descriptor->ShareDisposition = CmResourceShareShared;          /* FIXME Just a guess */
 679         Descriptor->Flags = CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE;     /* FIXME Just a guess */
 680         Descriptor->u.Interrupt.Level = PciConfig.u.type0.InterruptLine;
 681         Descriptor->u.Interrupt.Vector = PciConfig.u.type0.InterruptLine;
 682         Descriptor->u.Interrupt.Affinity = 0xFFFFFFFF;
 683
 684         Descriptor++;
 685     }
 686
 687     ASSERT(Descriptor == (*AllocatedResources)->List[0].PartialResourceList.PartialDescriptors + ResourceCount);
 688
 689     /* FIXME: Should store the resources in the registry resource map */
 690
 691     return Status;
 692 }
 693
 694 ULONG
 695 NTAPI
 696 HaliPciInterfaceReadConfig(IN PBUS_HANDLER RootBusHandler,
 697                            IN ULONG BusNumber,
 698                            IN PCI_SLOT_NUMBER SlotNumber,
 699                            IN PVOID Buffer,
 700                            IN ULONG Offset,
 701                            IN ULONG Length)
 702 {
 703     BUS_HANDLER BusHandler;
 704
 705     /* Setup fake PCI Bus handler */
 706     RtlCopyMemory(&BusHandler, &HalpFakePciBusHandler, sizeof(BUS_HANDLER));
 707     BusHandler.BusNumber = BusNumber;
 708
 709     /* Read configuration data */
 710     HalpReadPCIConfig(&BusHandler, SlotNumber, Buffer, Offset, Length);
 711
 712     /* Return length */
 713     return Length;
 714 }
 715
 716 PPCI_REGISTRY_INFO_INTERNAL
 717 NTAPI
 718 HalpQueryPciRegistryInfo(VOID)
 719 {
 720 #ifndef _MINIHAL_
 721     WCHAR NameBuffer[8];
 722     OBJECT_ATTRIBUTES  ObjectAttributes;
 723     UNICODE_STRING KeyName, ConfigName, IdentName;
 724     HANDLE KeyHandle, BusKeyHandle, CardListHandle;
 725     NTSTATUS Status;
 726     UCHAR KeyBuffer[sizeof(CM_FULL_RESOURCE_DESCRIPTOR) + 100];
 727     PKEY_VALUE_FULL_INFORMATION ValueInfo = (PVOID)KeyBuffer;
 728     UCHAR PartialKeyBuffer[sizeof(KEY_VALUE_PARTIAL_INFORMATION) +
 729                            sizeof(PCI_CARD_DESCRIPTOR)];
 730     PKEY_VALUE_PARTIAL_INFORMATION PartialValueInfo = (PVOID)PartialKeyBuffer;
 731     KEY_FULL_INFORMATION KeyInformation;
 732     ULONG ResultLength;
 733     PWSTR Tag;
 734     ULONG i, ElementCount;
 735     PCM_FULL_RESOURCE_DESCRIPTOR FullDescriptor;
 736     PCM_PARTIAL_RESOURCE_DESCRIPTOR PartialDescriptor;
 737     PPCI_REGISTRY_INFO PciRegInfo;
 738     PPCI_REGISTRY_INFO_INTERNAL PciRegistryInfo;
 739     PPCI_CARD_DESCRIPTOR CardDescriptor;
 740
 741     /* Setup the object attributes for the key */
 742     RtlInitUnicodeString(&KeyName,
 743                          L"\\Registry\\Machine\\Hardware\\Description\\"
 744                          L"System\\MultiFunctionAdapter");
 745     InitializeObjectAttributes(&ObjectAttributes,
 746                                &KeyName,
 747                                OBJ_CASE_INSENSITIVE,
 748                                NULL,
 749                                NULL);
 750
 751     /* Open the key */
 752     Status = ZwOpenKey(&KeyHandle, KEY_READ, &ObjectAttributes);
 753     if (!NT_SUCCESS(Status)) return NULL;
 754
 755     /* Setup the receiving string */
 756     KeyName.Buffer = NameBuffer;
 757     KeyName.MaximumLength = sizeof(NameBuffer);
 758
 759     /* Setup the configuration and identifier key names */
 760     RtlInitUnicodeString(&ConfigName, L"Configuration Data");
 761     RtlInitUnicodeString(&IdentName, L"Identifier");
 762
 763     /* Keep looping for each ID */
 764     for (i = 0; TRUE; i++)
 765     {
 766         /* Setup the key name */
 767         RtlIntegerToUnicodeString(i, 10, &KeyName);
 768         InitializeObjectAttributes(&ObjectAttributes,
 769                                    &KeyName,
 770                                    OBJ_CASE_INSENSITIVE,
 771                                    KeyHandle,
 772                                    NULL);
 773
 774         /* Open it */
 775         Status = ZwOpenKey(&BusKeyHandle, KEY_READ, &ObjectAttributes);
 776         if (!NT_SUCCESS(Status))
 777         {
 778             /* None left, fail */
 779             ZwClose(KeyHandle);
 780             return NULL;
 781         }
 782
 783         /* Read the registry data */
 784         Status = ZwQueryValueKey(BusKeyHandle,
 785                                  &IdentName,
 786                                  KeyValueFullInformation,
 787                                  ValueInfo,
 788                                  sizeof(KeyBuffer),
 789                                  &ResultLength);
 790         if (!NT_SUCCESS(Status))
 791         {
 792             /* Failed, try the next one */
 793             ZwClose(BusKeyHandle);
 794             continue;
 795         }
 796
 797         /* Get the PCI Tag and validate it */
 798         Tag = (PWSTR)((ULONG_PTR)ValueInfo + ValueInfo->DataOffset);
 799         if ((Tag[0] != L'P') ||
 800             (Tag[1] != L'C') ||
 801             (Tag[2] != L'I') ||
 802             (Tag[3]))
 803         {
 804             /* Not a valid PCI entry, skip it */
 805             ZwClose(BusKeyHandle);
 806             continue;
 807         }
 808
 809         /* Now read our PCI structure */
 810         Status = ZwQueryValueKey(BusKeyHandle,
 811                                  &ConfigName,
 812                                  KeyValueFullInformation,
 813                                  ValueInfo,
 814                                  sizeof(KeyBuffer),
 815                                  &ResultLength);
 816         ZwClose(BusKeyHandle);
 817         if (!NT_SUCCESS(Status)) continue;
 818
 819         /* We read it OK! Get the actual resource descriptors */
 820         FullDescriptor  = (PCM_FULL_RESOURCE_DESCRIPTOR)
 821                           ((ULONG_PTR)ValueInfo + ValueInfo->DataOffset);
 822         PartialDescriptor = (PCM_PARTIAL_RESOURCE_DESCRIPTOR)
 823                             ((ULONG_PTR)FullDescriptor->
 824                                         PartialResourceList.PartialDescriptors);
 825
 826         /* Check if this is our PCI Registry Information */
 827         if (PartialDescriptor->Type == CmResourceTypeDeviceSpecific)
 828         {
 829             /* It is, stop searching */
 830             break;
 831         }
 832     }
 833
 834     /* Close the key */
 835     ZwClose(KeyHandle);
 836
 837     /* Save the PCI information for later */
 838     PciRegInfo = (PPCI_REGISTRY_INFO)(PartialDescriptor + 1);
 839
 840     /* Assume no Card List entries */
 841     ElementCount = 0;
 842
 843     /* Set up for checking the PCI Card List key */
 844     RtlInitUnicodeString(&KeyName,
 845                          L"\\Registry\\Machine\\System\\CurrentControlSet\\"
 846                          L"Control\\PnP\\PCI\\CardList");
 847     InitializeObjectAttributes(&ObjectAttributes,
 848                                &KeyName,
 849                                OBJ_CASE_INSENSITIVE,
 850                                NULL,
 851                                NULL);
 852
 853     /* Attempt to open it */
 854     Status = ZwOpenKey(&CardListHandle, KEY_READ, &ObjectAttributes);
 855     if (NT_SUCCESS(Status))
 856     {
 857         /* It exists, so let's query it */
 858         Status = ZwQueryKey(CardListHandle,
 859                             KeyFullInformation,
 860                             &KeyInformation,
 861                             sizeof(KEY_FULL_INFORMATION),
 862                             &ResultLength);
 863         if (!NT_SUCCESS(Status))
 864         {
 865             /* Failed to query, so no info */
 866             PciRegistryInfo = NULL;
 867         }
 868         else
 869         {
 870             /* Allocate the full structure */
 871             PciRegistryInfo =
 872                 ExAllocatePoolWithTag(NonPagedPool,
 873                                       sizeof(PCI_REGISTRY_INFO_INTERNAL) +
 874                                       (KeyInformation.Values *
 875                                        sizeof(PCI_CARD_DESCRIPTOR)),
 876                                        ' laH');
 877             if (PciRegistryInfo)
 878             {
 879                 /* Get the first card descriptor entry */
 880                 CardDescriptor = (PPCI_CARD_DESCRIPTOR)(PciRegistryInfo + 1);
 881
 882                 /* Loop all the values */
 883                 for (i = 0; i < KeyInformation.Values; i++)
 884                 {
 885                     /* Attempt to get the value */
 886                     Status = ZwEnumerateValueKey(CardListHandle,
 887                                                  i,
 888                                                  KeyValuePartialInformation,
 889                                                  PartialValueInfo,
 890                                                  sizeof(PartialKeyBuffer),
 891                                                  &ResultLength);
 892                     if (!NT_SUCCESS(Status))
 893                     {
 894                         /* Something went wrong, stop the search */
 895                         break;
 896                     }
 897
 898                     /* Make sure it is correctly sized */
 899                     if (PartialValueInfo->DataLength == sizeof(PCI_CARD_DESCRIPTOR))
 900                     {
 901                         /* Sure is, copy it over */
 902                         *CardDescriptor = *(PPCI_CARD_DESCRIPTOR)
 903                                            PartialValueInfo->Data;
 904
 905                         /* One more Card List entry */
 906                         ElementCount++;
 907
 908                         /* Move to the next descriptor */
 909                         CardDescriptor = (CardDescriptor + 1);
 910                     }
 911                 }
 912             }
 913         }
 914
 915         /* Close the Card List key */
 916         ZwClose(CardListHandle);
 917     }
 918     else
 919     {
 920        /* No key, no Card List */
 921        PciRegistryInfo = NULL;
 922     }
 923
 924     /* Check if we failed to get the full structure */
 925     if (!PciRegistryInfo)
 926     {
 927         /* Just allocate the basic structure then */
 928         PciRegistryInfo = ExAllocatePoolWithTag(NonPagedPool,
 929                                                 sizeof(PCI_REGISTRY_INFO_INTERNAL),
 930                                                 ' laH');
 931         if (!PciRegistryInfo) return NULL;
 932     }
 933
 934     /* Save the info we got */
 935     PciRegistryInfo->MajorRevision = PciRegInfo->MajorRevision;
 936     PciRegistryInfo->MinorRevision = PciRegInfo->MinorRevision;
 937     PciRegistryInfo->NoBuses = PciRegInfo->NoBuses;
 938     PciRegistryInfo->HardwareMechanism = PciRegInfo->HardwareMechanism;
 939     PciRegistryInfo->ElementCount = ElementCount;
 940
 941     /* Return it */
 942     return PciRegistryInfo;
 943 #else
 944     return NULL;
 945 #endif
 946 }
 947
 948 VOID
 949 NTAPI
 950 HalpInitializePciStubs(VOID)
 951 {
 952     PPCI_REGISTRY_INFO_INTERNAL PciRegistryInfo;
 953     UCHAR PciType;
 954     PPCIPBUSDATA BusData = (PPCIPBUSDATA)HalpFakePciBusHandler.BusData;
 955     ULONG i;
 956     PCI_SLOT_NUMBER j;
 957     ULONG VendorId = 0;
 958     ULONG MaxPciBusNumber;
 959
 960     /* Query registry information */
 961     PciRegistryInfo = HalpQueryPciRegistryInfo();
 962     if (!PciRegistryInfo)
 963     {
 964         /* Assume type 1 */
 965         PciType = 1;
 966
 967         /* Force a manual bus scan later */
 968         MaxPciBusNumber = MAXULONG;
 969     }
 970     else
 971     {
 972         /* Get the PCI type */
 973         PciType = PciRegistryInfo->HardwareMechanism & 0xF;
 974
 975         /* Get MaxPciBusNumber and make it 0-based */
 976         MaxPciBusNumber = PciRegistryInfo->NoBuses - 1;
 977
 978         /* Free the info structure */
 979         ExFreePool(PciRegistryInfo);
 980     }
 981
 982     /* Initialize the PCI lock */
 983     KeInitializeSpinLock(&HalpPCIConfigLock);
 984
 985     /* Check the type of PCI bus */
 986     switch (PciType)
 987     {
 988         /* Type 1 PCI Bus */
 989         case 1:
 990
 991             /* Copy the Type 1 handler data */
 992             RtlCopyMemory(&PCIConfigHandler,
 993                           &PCIConfigHandlerType1,
 994                           sizeof(PCIConfigHandler));
 995
 996             /* Set correct I/O Ports */
 997             BusData->Config.Type1.Address = PCI_TYPE1_ADDRESS_PORT;
 998             BusData->Config.Type1.Data = PCI_TYPE1_DATA_PORT;
 999             break;
1000
1001         /* Type 2 PCI Bus */
1002         case 2:
1003
1004             /* Copy the Type 2 handler data */
1005             RtlCopyMemory(&PCIConfigHandler,
1006                           &PCIConfigHandlerType2,
1007                           sizeof (PCIConfigHandler));
1008
1009             /* Set correct I/O Ports */
1010             BusData->Config.Type2.CSE = PCI_TYPE2_CSE_PORT;
1011             BusData->Config.Type2.Forward = PCI_TYPE2_FORWARD_PORT;
1012             BusData->Config.Type2.Base = PCI_TYPE2_ADDRESS_BASE;
1013
1014             /* Only 16 devices supported, not 32 */
1015             BusData->MaxDevice = 16;
1016             break;
1017
1018         default:
1019
1020             /* Invalid type */
1021             DbgPrint("HAL: Unknown PCI type\n");
1022     }
1023
1024     /* Run a forced bus scan if needed */
1025     if (MaxPciBusNumber == MAXULONG)
1026     {
1027         /* Initialize the max bus number to 0xFF */
1028         HalpMaxPciBus = 0xFF;
1029
1030         /* Initialize the counter */
1031         MaxPciBusNumber = 0;
1032
1033         /* Loop all possible buses */
1034         for (i = 0; i < HalpMaxPciBus; i++)
1035         {
1036             /* Loop all devices */
1037             for (j.u.AsULONG = 0; j.u.AsULONG < BusData->MaxDevice; j.u.AsULONG++)
1038             {
1039                 /* Query the interface */
1040                 if (HaliPciInterfaceReadConfig(NULL,
1041                                                i,
1042                                                j,
1043                                                &VendorId,
1044                                                0,
1045                                                sizeof(ULONG)))
1046                 {
1047                     /* Validate the vendor ID */
1048                     if ((USHORT)VendorId != PCI_INVALID_VENDORID)
1049                     {
1050                         /* Set this as the maximum ID */
1051                         MaxPciBusNumber = i;
1052                         break;
1053                     }
1054                 }
1055             }
1056         }
1057     }
1058
1059     /* Set the real max bus number */
1060     HalpMaxPciBus = MaxPciBusNumber;
1061
1062     /* We're done */
1063     HalpPCIConfigInitialized = TRUE;
1064 }
1065