3 * COPYRIGHT: See COPYING in the top level directory
4 * PROJECT: ReactOS kernel
5 * FILE: ntoskrnl/hal/x86/pci.c
6 * PURPOSE: Interfaces to the PCI bus
7 * PROGRAMMER: David Welch (welch@mcmail.com)
8 * Eric Kohl (ekohl@rz-online.de)
11 * 17/08/2000: Added preliminary pci bus scanner
12 * 13/06/2001: Implemented access to pci configuration space
16 * NOTES: Sections copied from the Linux pci support
19 /* INCLUDES *****************************************************************/
26 /* MACROS ******************************************************************/
28 /* FIXME These are also defined in drivers/bus/pci/pcidef.h.
29 Maybe put PCI definitions in a central include file??? */
31 /* access type 1 macros */
32 #define CONFIG_CMD(bus, dev_fn, where) \
33 (0x80000000 | (((ULONG)(bus)) << 16) | (((dev_fn) & 0x1F) << 11) | (((dev_fn) & 0xE0) << 3) | ((where) & ~3))
35 /* access type 2 macros */
36 #define IOADDR(dev_fn, where) \
37 (0xC000 | (((dev_fn) & 0x1F) << 8) | (where))
38 #define FUNC(dev_fn) \
39 ((((dev_fn) & 0xE0) >> 4) | 0xf0)
41 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
42 #define PCI_BASE_ADDRESS_SPACE_IO 0x01
43 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
44 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
45 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
46 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
47 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
48 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
49 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
50 #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
51 /* bit 1 is reserved if address_space = 1 */
54 /* GLOBALS ******************************************************************/
56 #define TAG_PCI TAG('P', 'C', 'I', 'H')
58 static ULONG BusConfigType
= 0; /* undetermined config type */
59 static KSPIN_LOCK PciLock
;
61 /* FUNCTIONS ****************************************************************/
64 ReadPciConfigUchar(UCHAR Bus
,
71 switch (BusConfigType
)
74 KeAcquireSpinLock(&PciLock
, &oldIrql
);
75 WRITE_PORT_ULONG((PULONG
)0xCF8, CONFIG_CMD(Bus
, Slot
, Offset
));
76 *Value
= READ_PORT_UCHAR((PUCHAR
)0xCFC + (Offset
& 3));
77 KeReleaseSpinLock(&PciLock
, oldIrql
);
78 return STATUS_SUCCESS
;
81 KeAcquireSpinLock(&PciLock
, &oldIrql
);
82 WRITE_PORT_UCHAR((PUCHAR
)0xCF8, (UCHAR
)FUNC(Slot
));
83 WRITE_PORT_UCHAR((PUCHAR
)0xCFA, Bus
);
84 *Value
= READ_PORT_UCHAR((PUCHAR
)(IOADDR(Slot
, Offset
)));
85 WRITE_PORT_UCHAR((PUCHAR
)0xCF8, 0);
86 KeReleaseSpinLock(&PciLock
, oldIrql
);
87 return STATUS_SUCCESS
;
89 return STATUS_UNSUCCESSFUL
;
94 ReadPciConfigUshort(UCHAR Bus
,
101 if ((Offset
& 1) != 0)
103 return STATUS_INVALID_PARAMETER
;
106 switch (BusConfigType
)
109 KeAcquireSpinLock(&PciLock
, &oldIrql
);
110 WRITE_PORT_ULONG((PULONG
)0xCF8, CONFIG_CMD(Bus
, Slot
, Offset
));
111 *Value
= READ_PORT_USHORT((PUSHORT
)0xCFC + (Offset
& 2));
112 KeReleaseSpinLock(&PciLock
, oldIrql
);
113 return STATUS_SUCCESS
;
116 KeAcquireSpinLock(&PciLock
, &oldIrql
);
117 WRITE_PORT_UCHAR((PUCHAR
)0xCF8, (UCHAR
)FUNC(Slot
));
118 WRITE_PORT_UCHAR((PUCHAR
)0xCFA, Bus
);
119 *Value
= READ_PORT_USHORT((PUSHORT
)(IOADDR(Slot
, Offset
)));
120 WRITE_PORT_UCHAR((PUCHAR
)0xCF8, 0);
121 KeReleaseSpinLock(&PciLock
, oldIrql
);
122 return STATUS_SUCCESS
;
124 return STATUS_UNSUCCESSFUL
;
129 ReadPciConfigUlong(UCHAR Bus
,
136 if ((Offset
& 3) != 0)
138 return STATUS_INVALID_PARAMETER
;
141 switch (BusConfigType
)
144 KeAcquireSpinLock(&PciLock
, &oldIrql
);
145 WRITE_PORT_ULONG((PULONG
)0xCF8, CONFIG_CMD(Bus
, Slot
, Offset
));
146 *Value
= READ_PORT_ULONG((PULONG
)0xCFC);
147 KeReleaseSpinLock(&PciLock
, oldIrql
);
148 return STATUS_SUCCESS
;
151 KeAcquireSpinLock(&PciLock
, &oldIrql
);
152 WRITE_PORT_UCHAR((PUCHAR
)0xCF8, (UCHAR
)FUNC(Slot
));
153 WRITE_PORT_UCHAR((PUCHAR
)0xCFA, Bus
);
154 *Value
= READ_PORT_ULONG((PULONG
)(IOADDR(Slot
, Offset
)));
155 WRITE_PORT_UCHAR((PUCHAR
)0xCF8, 0);
156 KeReleaseSpinLock(&PciLock
, oldIrql
);
157 return STATUS_SUCCESS
;
159 return STATUS_UNSUCCESSFUL
;
164 WritePciConfigUchar(UCHAR Bus
,
171 switch (BusConfigType
)
174 KeAcquireSpinLock(&PciLock
, &oldIrql
);
175 WRITE_PORT_ULONG((PULONG
)0xCF8, CONFIG_CMD(Bus
, Slot
, Offset
));
176 WRITE_PORT_UCHAR((PUCHAR
)0xCFC + (Offset
&3), Value
);
177 KeReleaseSpinLock(&PciLock
, oldIrql
);
178 return STATUS_SUCCESS
;
181 KeAcquireSpinLock(&PciLock
, &oldIrql
);
182 WRITE_PORT_UCHAR((PUCHAR
)0xCF8, (UCHAR
)FUNC(Slot
));
183 WRITE_PORT_UCHAR((PUCHAR
)0xCFA, Bus
);
184 WRITE_PORT_UCHAR((PUCHAR
)(IOADDR(Slot
,Offset
)), Value
);
185 WRITE_PORT_UCHAR((PUCHAR
)0xCF8, 0);
186 KeReleaseSpinLock(&PciLock
, oldIrql
);
187 return STATUS_SUCCESS
;
189 return STATUS_UNSUCCESSFUL
;
194 WritePciConfigUshort(UCHAR Bus
,
201 if ((Offset
& 1) != 0)
203 return STATUS_INVALID_PARAMETER
;
206 switch (BusConfigType
)
209 KeAcquireSpinLock(&PciLock
, &oldIrql
);
210 WRITE_PORT_ULONG((PULONG
)0xCF8, CONFIG_CMD(Bus
, Slot
, Offset
));
211 WRITE_PORT_USHORT((PUSHORT
)0xCFC + (Offset
& 2), Value
);
212 KeReleaseSpinLock(&PciLock
, oldIrql
);
213 return STATUS_SUCCESS
;
216 KeAcquireSpinLock(&PciLock
, &oldIrql
);
217 WRITE_PORT_UCHAR((PUCHAR
)0xCF8, (UCHAR
)FUNC(Slot
));
218 WRITE_PORT_UCHAR((PUCHAR
)0xCFA, Bus
);
219 WRITE_PORT_USHORT((PUSHORT
)(IOADDR(Slot
, Offset
)), Value
);
220 WRITE_PORT_UCHAR((PUCHAR
)0xCF8, 0);
221 KeReleaseSpinLock(&PciLock
, oldIrql
);
222 return STATUS_SUCCESS
;
224 return STATUS_UNSUCCESSFUL
;
229 WritePciConfigUlong(UCHAR Bus
,
236 if ((Offset
& 3) != 0)
238 return STATUS_INVALID_PARAMETER
;
241 switch (BusConfigType
)
244 KeAcquireSpinLock(&PciLock
, &oldIrql
);
245 WRITE_PORT_ULONG((PULONG
)0xCF8, CONFIG_CMD(Bus
, Slot
, Offset
));
246 WRITE_PORT_ULONG((PULONG
)0xCFC, Value
);
247 KeReleaseSpinLock(&PciLock
, oldIrql
);
248 return STATUS_SUCCESS
;
251 KeAcquireSpinLock(&PciLock
, &oldIrql
);
252 WRITE_PORT_UCHAR((PUCHAR
)0xCF8, (UCHAR
)FUNC(Slot
));
253 WRITE_PORT_UCHAR((PUCHAR
)0xCFA, Bus
);
254 WRITE_PORT_ULONG((PULONG
)(IOADDR(Slot
, Offset
)), Value
);
255 WRITE_PORT_UCHAR((PUCHAR
)0xCF8, 0);
256 KeReleaseSpinLock(&PciLock
, oldIrql
);
257 return STATUS_SUCCESS
;
259 return STATUS_UNSUCCESSFUL
;
264 HalpGetPciData(PBUS_HANDLER BusHandler
,
272 ULONG Address
= Offset
;
277 DPRINT("HalpGetPciData() called.\n");
278 DPRINT(" BusNumber %lu\n", BusNumber
);
279 DPRINT(" SlotNumber %lu\n", SlotNumber
);
280 DPRINT(" Offset 0x%lx\n", Offset
);
281 DPRINT(" Length 0x%lx\n", Length
);
283 if ((Length
== 0) || (BusConfigType
== 0))
286 ReadPciConfigUlong((UCHAR
)BusNumber
,
287 (UCHAR
)(SlotNumber
& 0x1F),
290 /* some broken boards return 0 if a slot is empty: */
291 if (Vendor
== 0xFFFFFFFF || Vendor
== 0)
293 if (BusNumber
== 0 && Offset
== 0 && Length
>= 2)
295 *(PUSHORT
)Buffer
= PCI_INVALID_VENDORID
;
301 /* 0E=PCI_HEADER_TYPE */
302 ReadPciConfigUchar((UCHAR
)BusNumber
,
303 (UCHAR
)(SlotNumber
& 0x1F),
306 if (((HeaderType
& PCI_MULTIFUNCTION
) == 0) && ((SlotNumber
& 0xE0) != 0))
308 if (Offset
== 0 && Length
>= 2)
310 *(PUSHORT
)Buffer
= PCI_INVALID_VENDORID
;
315 ReadPciConfigUlong((UCHAR
)BusNumber
,
319 /* some broken boards return 0 if a slot is empty: */
320 if (Vendor
== 0xFFFFFFFF || Vendor
== 0)
322 if (BusNumber
== 0 && Offset
== 0 && Length
>= 2)
324 *(PUSHORT
)Buffer
= PCI_INVALID_VENDORID
;
330 if ((Address
& 1) && (Len
>= 1))
332 ReadPciConfigUchar((UCHAR
)BusNumber
,
336 Ptr
= (char*)Ptr
+ 1;
341 if ((Address
& 2) && (Len
>= 2))
343 ReadPciConfigUshort((UCHAR
)BusNumber
,
347 Ptr
= (char*)Ptr
+ 2;
354 ReadPciConfigUlong((UCHAR
)BusNumber
,
358 Ptr
= (char*)Ptr
+ 4;
365 ReadPciConfigUshort((UCHAR
)BusNumber
,
369 Ptr
= (char*)Ptr
+ 2;
376 ReadPciConfigUchar((UCHAR
)BusNumber
,
380 Ptr
= (char*)Ptr
+ 1;
390 HalpSetPciData(PBUS_HANDLER BusHandler
,
398 ULONG Address
= Offset
;
403 DPRINT("HalpSetPciData() called.\n");
404 DPRINT(" BusNumber %lu\n", BusNumber
);
405 DPRINT(" SlotNumber %lu\n", SlotNumber
);
406 DPRINT(" Offset 0x%lx\n", Offset
);
407 DPRINT(" Length 0x%lx\n", Length
);
409 if ((Length
== 0) || (BusConfigType
== 0))
412 ReadPciConfigUlong((UCHAR
)BusNumber
,
413 (UCHAR
)(SlotNumber
& 0x1F),
416 /* some broken boards return 0 if a slot is empty: */
417 if (Vendor
== 0xFFFFFFFF || Vendor
== 0)
421 /* 0E=PCI_HEADER_TYPE */
422 ReadPciConfigUchar((UCHAR
)BusNumber
,
423 (UCHAR
)(SlotNumber
& 0x1F),
426 if (((HeaderType
& PCI_MULTIFUNCTION
) == 0) && ((SlotNumber
& 0xE0) != 0))
429 ReadPciConfigUlong((UCHAR
)BusNumber
,
433 /* some broken boards return 0 if a slot is empty: */
434 if (Vendor
== 0xFFFFFFFF || Vendor
== 0)
437 if ((Address
& 1) && (Len
>= 1))
439 WritePciConfigUchar((UCHAR
)BusNumber
,
443 Ptr
= (char*)Ptr
+ 1;
448 if ((Address
& 2) && (Len
>= 2))
450 WritePciConfigUshort((UCHAR
)BusNumber
,
454 Ptr
= (char*)Ptr
+ 2;
461 WritePciConfigUlong((UCHAR
)BusNumber
,
465 Ptr
= (char*)Ptr
+ 4;
472 WritePciConfigUshort((UCHAR
)BusNumber
,
476 Ptr
= (char*)Ptr
+ 2;
483 WritePciConfigUchar((UCHAR
)BusNumber
,
487 Ptr
= (char*)Ptr
+ 1;
497 GetBusConfigType(VOID
)
502 DPRINT("GetBusConfigType() called\n");
504 KeAcquireSpinLock(&PciLock
, &oldIrql
);
506 DPRINT("Checking configuration type 1:");
507 WRITE_PORT_UCHAR((PUCHAR
)0xCFB, 0x01);
508 Value
= READ_PORT_ULONG((PULONG
)0xCF8);
509 WRITE_PORT_ULONG((PULONG
)0xCF8, 0x80000000);
510 if (READ_PORT_ULONG((PULONG
)0xCF8) == 0x80000000)
512 WRITE_PORT_ULONG((PULONG
)0xCF8, Value
);
513 KeReleaseSpinLock(&PciLock
, oldIrql
);
514 DPRINT(" Success!\n");
517 WRITE_PORT_ULONG((PULONG
)0xCF8, Value
);
518 DPRINT(" Unsuccessful!\n");
520 DPRINT("Checking configuration type 2:");
521 WRITE_PORT_UCHAR((PUCHAR
)0xCFB, 0x00);
522 WRITE_PORT_UCHAR((PUCHAR
)0xCF8, 0x00);
523 WRITE_PORT_UCHAR((PUCHAR
)0xCFA, 0x00);
524 if (READ_PORT_UCHAR((PUCHAR
)0xCF8) == 0x00 &&
525 READ_PORT_UCHAR((PUCHAR
)0xCFB) == 0x00)
527 KeReleaseSpinLock(&PciLock
, oldIrql
);
528 DPRINT(" Success!\n");
531 KeReleaseSpinLock(&PciLock
, oldIrql
);
532 DPRINT(" Unsuccessful!\n");
534 DPRINT("No pci bus found!\n");
540 HalpGetPciInterruptVector(PVOID BusHandler
,
542 ULONG BusInterruptLevel
,
543 ULONG BusInterruptVector
,
547 ULONG Vector
= IRQ2VECTOR(BusInterruptVector
);
548 *Irql
= VECTOR2IRQL(Vector
);
549 *Affinity
= 0xFFFFFFFF;
553 static BOOLEAN STDCALL
554 HalpTranslatePciAddress(PBUS_HANDLER BusHandler
,
556 PHYSICAL_ADDRESS BusAddress
,
558 PPHYSICAL_ADDRESS TranslatedAddress
)
560 if (*AddressSpace
== 0)
565 else if (*AddressSpace
== 1)
576 TranslatedAddress
->QuadPart
= BusAddress
.QuadPart
;
582 * Find the extent of a PCI decode..
585 PciSize(ULONG Base
, ULONG Mask
)
587 ULONG Size
= Mask
& Base
; /* Find the significant bits */
588 Size
= Size
& ~(Size
- 1); /* Get the lowest of them to find the decode size */
592 static NTSTATUS STDCALL
593 HalpAssignPciSlotResources(IN PBUS_HANDLER BusHandler
,
595 IN PUNICODE_STRING RegistryPath
,
596 IN PUNICODE_STRING DriverClassName
,
597 IN PDRIVER_OBJECT DriverObject
,
598 IN PDEVICE_OBJECT DeviceObject
,
600 IN OUT PCM_RESOURCE_LIST
*AllocatedResources
)
603 PCI_COMMON_CONFIG PciConfig
;
606 ULONG Size
[PCI_TYPE0_ADDRESSES
];
607 NTSTATUS Status
= STATUS_SUCCESS
;
609 PCM_PARTIAL_RESOURCE_DESCRIPTOR Descriptor
;
611 /* FIXME: Should handle 64-bit addresses */
613 DataSize
= HalpGetPciData(BusHandler
,
618 PCI_COMMON_HDR_LENGTH
);
619 if (PCI_COMMON_HDR_LENGTH
!= DataSize
)
621 return STATUS_UNSUCCESSFUL
;
624 /* Read the PCI configuration space for the device and store base address and
625 size information in temporary storage. Count the number of valid base addresses */
627 for (Address
= 0; Address
< PCI_TYPE0_ADDRESSES
; Address
++)
629 if (0xffffffff == PciConfig
.u
.type0
.BaseAddresses
[Address
])
631 PciConfig
.u
.type0
.BaseAddresses
[Address
] = 0;
633 if (0 != PciConfig
.u
.type0
.BaseAddresses
[Address
])
636 Offset
= FIELD_OFFSET(PCI_COMMON_CONFIG
, u
.type0
.BaseAddresses
[Address
]);
637 Status
= WritePciConfigUlong((UCHAR
)BusNumber
, (UCHAR
)SlotNumber
, Offset
, 0xffffffff);
638 if (! NT_SUCCESS(Status
))
640 WritePciConfigUlong((UCHAR
)BusNumber
, (UCHAR
)SlotNumber
, Offset
,
641 PciConfig
.u
.type0
.BaseAddresses
[Address
]);
644 Status
= ReadPciConfigUlong((UCHAR
)BusNumber
, (UCHAR
)SlotNumber
,
645 Offset
, Size
+ Address
);
646 if (! NT_SUCCESS(Status
))
648 WritePciConfigUlong((UCHAR
)BusNumber
, (UCHAR
)SlotNumber
, Offset
,
649 PciConfig
.u
.type0
.BaseAddresses
[Address
]);
652 Status
= WritePciConfigUlong((UCHAR
)BusNumber
, (UCHAR
)SlotNumber
, Offset
,
653 PciConfig
.u
.type0
.BaseAddresses
[Address
]);
654 if (! NT_SUCCESS(Status
))
661 if (0 != PciConfig
.u
.type0
.InterruptLine
)
666 /* Allocate output buffer and initialize */
667 *AllocatedResources
= ExAllocatePoolWithTag(PagedPool
,
668 sizeof(CM_RESOURCE_LIST
) +
669 (ResourceCount
- 1) * sizeof(CM_PARTIAL_RESOURCE_DESCRIPTOR
),
671 if (NULL
== *AllocatedResources
)
673 return STATUS_NO_MEMORY
;
675 (*AllocatedResources
)->Count
= 1;
676 (*AllocatedResources
)->List
[0].InterfaceType
= PCIBus
;
677 (*AllocatedResources
)->List
[0].BusNumber
= BusNumber
;
678 (*AllocatedResources
)->List
[0].PartialResourceList
.Version
= 1;
679 (*AllocatedResources
)->List
[0].PartialResourceList
.Revision
= 1;
680 (*AllocatedResources
)->List
[0].PartialResourceList
.Count
= ResourceCount
;
681 Descriptor
= (*AllocatedResources
)->List
[0].PartialResourceList
.PartialDescriptors
;
683 /* Store configuration information */
684 for (Address
= 0; Address
< PCI_TYPE0_ADDRESSES
; Address
++)
686 if (0 != PciConfig
.u
.type0
.BaseAddresses
[Address
])
688 if (PCI_BASE_ADDRESS_SPACE_MEMORY
==
689 (PciConfig
.u
.type0
.BaseAddresses
[Address
] & PCI_BASE_ADDRESS_SPACE
))
691 Descriptor
->Type
= CmResourceTypeMemory
;
692 Descriptor
->ShareDisposition
= CmResourceShareDeviceExclusive
; /* FIXME I have no idea... */
693 Descriptor
->Flags
= CM_RESOURCE_MEMORY_READ_WRITE
; /* FIXME Just a guess */
694 Descriptor
->u
.Memory
.Start
.QuadPart
= (PciConfig
.u
.type0
.BaseAddresses
[Address
] & PCI_BASE_ADDRESS_MEM_MASK
);
695 Descriptor
->u
.Memory
.Length
= PciSize(Size
[Address
], PCI_BASE_ADDRESS_MEM_MASK
);
697 else if (PCI_BASE_ADDRESS_SPACE_IO
==
698 (PciConfig
.u
.type0
.BaseAddresses
[Address
] & PCI_BASE_ADDRESS_SPACE
))
700 Descriptor
->Type
= CmResourceTypePort
;
701 Descriptor
->ShareDisposition
= CmResourceShareDeviceExclusive
; /* FIXME I have no idea... */
702 Descriptor
->Flags
= CM_RESOURCE_PORT_IO
; /* FIXME Just a guess */
703 Descriptor
->u
.Port
.Start
.QuadPart
= PciConfig
.u
.type0
.BaseAddresses
[Address
] &= PCI_BASE_ADDRESS_IO_MASK
;
704 Descriptor
->u
.Port
.Length
= PciSize(Size
[Address
], PCI_BASE_ADDRESS_IO_MASK
& 0xffff);
709 return STATUS_UNSUCCESSFUL
;
715 if (0 != PciConfig
.u
.type0
.InterruptLine
)
717 Descriptor
->Type
= CmResourceTypeInterrupt
;
718 Descriptor
->ShareDisposition
= CmResourceShareShared
; /* FIXME Just a guess */
719 Descriptor
->Flags
= CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE
; /* FIXME Just a guess */
720 Descriptor
->u
.Interrupt
.Level
= PciConfig
.u
.type0
.InterruptLine
;
721 Descriptor
->u
.Interrupt
.Vector
= PciConfig
.u
.type0
.InterruptLine
;
722 Descriptor
->u
.Interrupt
.Affinity
= 0xFFFFFFFF;
727 ASSERT(Descriptor
== (*AllocatedResources
)->List
[0].PartialResourceList
.PartialDescriptors
+ ResourceCount
);
729 /* FIXME: Should store the resources in the registry resource map */
738 PBUS_HANDLER BusHandler
;
740 DPRINT("HalpInitPciBus() called.\n");
742 KeInitializeSpinLock (&PciLock
);
744 BusConfigType
= GetBusConfigType();
745 if (BusConfigType
== 0)
748 DPRINT("Bus configuration %lu used\n", BusConfigType
);
750 /* pci bus (bus 0) handler */
751 BusHandler
= HalpAllocateBusHandler(PCIBus
,
754 BusHandler
->GetBusData
= (pGetSetBusData
)HalpGetPciData
;
755 BusHandler
->SetBusData
= (pGetSetBusData
)HalpSetPciData
;
756 BusHandler
->GetInterruptVector
=
757 (pGetInterruptVector
)HalpGetPciInterruptVector
;
758 BusHandler
->TranslateBusAddress
=
759 (pTranslateBusAddress
)HalpTranslatePciAddress
;
760 // BusHandler->AdjustResourceList =
761 // (pGetSetBusData)HalpAdjustPciResourceList;
762 BusHandler
->AssignSlotResources
=
763 (pAssignSlotResources
)HalpAssignPciSlotResources
;
764 if (NULL
!= HalpHooks
.InitPciBus
)
766 HalpHooks
.InitPciBus(0, BusHandler
);
770 /* agp bus (bus 1) handler */
771 BusHandler
= HalpAllocateBusHandler(PCIBus
,
774 BusHandler
->GetBusData
= (pGetSetBusData
)HalpGetPciData
;
775 BusHandler
->SetBusData
= (pGetSetBusData
)HalpSetPciData
;
776 BusHandler
->GetInterruptVector
=
777 (pGetInterruptVector
)HalpGetPciInterruptVector
;
778 BusHandler
->TranslateBusAddress
=
779 (pTranslateBusAddress
)HalpTranslatePciAddress
;
780 // BusHandler->AdjustResourceList =
781 // (pGetSetBusData)HalpAdjustPciResourceList;
782 BusHandler
->AssignSlotResources
=
783 (pAssignSlotResources
)HalpAssignPciSlotResources
;
784 if (NULL
!= HalpHooks
.InitPciBus
)
786 HalpHooks
.InitPciBus(1, BusHandler
);
790 /* PCI bus (bus 2) handler */
791 BusHandler
= HalpAllocateBusHandler(PCIBus
,
794 BusHandler
->GetBusData
= (pGetSetBusData
)HalpGetPciData
;
795 BusHandler
->SetBusData
= (pGetSetBusData
)HalpSetPciData
;
796 BusHandler
->GetInterruptVector
=
797 (pGetInterruptVector
)HalpGetPciInterruptVector
;
798 BusHandler
->TranslateBusAddress
=
799 (pTranslateBusAddress
)HalpTranslatePciAddress
;
800 // BusHandler->AdjustResourceList =
801 // (pGetSetBusData)HalpAdjustPciResourceList;
802 BusHandler
->AssignSlotResources
=
803 (pAssignSlotResources
)HalpAssignPciSlotResources
;
804 if (NULL
!= HalpHooks
.InitPciBus
)
806 HalpHooks
.InitPciBus(2, BusHandler
);
809 DPRINT("HalpInitPciBus() finished.\n");