reactos/hal/halx86/include/bus.h

   1 #pragma once
   2
   3 #define PCI_ADDRESS_MEMORY_SPACE            0x00000000
   4
   5 //
   6 // Helper Macros
   7 //
   8 #define PASTE2(x,y)                                                     x ## y
   9 #define POINTER_TO_(x)                                                  PASTE2(P,x)
  10 #define READ_FROM(x)                                                    PASTE2(READ_PORT_, x)
  11 #define WRITE_TO(x)                                                     PASTE2(WRITE_PORT_, x)
  12
  13 //
  14 // Declares a PCI Register Read/Write Routine
  15 //
  16 #define TYPE_DEFINE(x, y)                                               \
  17     ULONG                                                               \
  18     NTAPI                                                               \
  19     x(                                                                  \
  20         IN PPCIPBUSDATA BusData,                                        \
  21         IN y PciCfg,                                                    \
  22         IN PUCHAR Buffer,                                               \
  23         IN ULONG Offset                                                 \
  24     )
  25 #define TYPE1_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS);
  26 #define TYPE2_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS);
  27
  28 //
  29 // Defines a PCI Register Read/Write Type 1 Routine Prologue and Epilogue
  30 //
  31 #define TYPE1_START(x, y)                                               \
  32     TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS)                                 \
  33 {                                                                       \
  34     ULONG i = Offset % sizeof(ULONG);                                   \
  35     PciCfg->u.bits.RegisterNumber = Offset / sizeof(ULONG);             \
  36     WRITE_PORT_ULONG(BusData->Config.Type1.Address, PciCfg->u.AsULONG);
  37 #define TYPE1_END(y)                                                    \
  38     return sizeof(y); }
  39 #define TYPE2_END       TYPE1_END
  40
  41 //
  42 // PCI Register Read Type 1 Routine
  43 //
  44 #define TYPE1_READ(x, y)                                                \
  45     TYPE1_START(x, y)                                                   \
  46     *((POINTER_TO_(y))Buffer) =                                         \
  47     READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i));     \
  48     TYPE1_END(y)
  49
  50 //
  51 // PCI Register Write Type 1 Routine
  52 //
  53 #define TYPE1_WRITE(x, y)                                               \
  54     TYPE1_START(x, y)                                                   \
  55     WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i),       \
  56                 *((POINTER_TO_(y))Buffer));                             \
  57     TYPE1_END(y)
  58
  59 //
  60 // Defines a PCI Register Read/Write Type 2 Routine Prologue and Epilogue
  61 //
  62 #define TYPE2_START(x, y)                                               \
  63     TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS)                             \
  64 {                                                                       \
  65     PciCfg->u.bits.RegisterNumber = (USHORT)Offset;
  66
  67 //
  68 // PCI Register Read Type 2 Routine
  69 //
  70 #define TYPE2_READ(x, y)                                                \
  71     TYPE2_START(x, y)                                                   \
  72     *((POINTER_TO_(y))Buffer) =                                         \
  73         READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT);        \
  74     TYPE2_END(y)
  75
  76 //
  77 // PCI Register Write Type 2 Routine
  78 //
  79 #define TYPE2_WRITE(x, y)                                               \
  80     TYPE2_START(x, y)                                                   \
  81     WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT,              \
  82                 *((POINTER_TO_(y))Buffer));                             \
  83     TYPE2_END(y)
  84
  85 typedef NTSTATUS
  86 (NTAPI *PciIrqRange)(
  87     IN PBUS_HANDLER BusHandler,
  88     IN PBUS_HANDLER RootHandler,
  89     IN PCI_SLOT_NUMBER PciSlot,
  90     OUT PSUPPORTED_RANGE *Interrupt
  91 );
  92
  93 typedef struct _PCIPBUSDATA
  94 {
  95     PCIBUSDATA CommonData;
  96     union
  97     {
  98         struct
  99         {
 100             PULONG Address;
 101             ULONG Data;
 102         } Type1;
 103         struct
 104         {
 105             PUCHAR CSE;
 106             PUCHAR Forward;
 107             ULONG Base;
 108         } Type2;
 109     } Config;
 110     ULONG MaxDevice;
 111     PciIrqRange GetIrqRange;
 112     BOOLEAN BridgeConfigRead;
 113     UCHAR ParentBus;
 114     UCHAR Subtractive;
 115     UCHAR reserved[1];
 116     UCHAR SwizzleIn[4];
 117     RTL_BITMAP DeviceConfigured;
 118     ULONG ConfiguredBits[PCI_MAX_DEVICES * PCI_MAX_FUNCTION / 32];
 119 } PCIPBUSDATA, *PPCIPBUSDATA;
 120
 121 typedef ULONG
 122 (NTAPI *FncConfigIO)(
 123     IN PPCIPBUSDATA BusData,
 124     IN PVOID State,
 125     IN PUCHAR Buffer,
 126     IN ULONG Offset
 127 );
 128
 129 typedef VOID
 130 (NTAPI *FncSync)(
 131     IN PBUS_HANDLER BusHandler,
 132     IN PCI_SLOT_NUMBER Slot,
 133     IN PKIRQL Irql,
 134     IN PVOID State
 135 );
 136
 137 typedef VOID
 138 (NTAPI *FncReleaseSync)(
 139     IN PBUS_HANDLER BusHandler,
 140     IN KIRQL Irql
 141 );
 142
 143 typedef struct _PCI_CONFIG_HANDLER
 144 {
 145     FncSync Synchronize;
 146     FncReleaseSync ReleaseSynchronzation;
 147     FncConfigIO ConfigRead[3];
 148     FncConfigIO ConfigWrite[3];
 149 } PCI_CONFIG_HANDLER, *PPCI_CONFIG_HANDLER;
 150
 151 typedef struct _PCI_REGISTRY_INFO_INTERNAL
 152 {
 153     UCHAR MajorRevision;
 154     UCHAR MinorRevision;
 155     UCHAR NoBuses; // Number Of Buses
 156     UCHAR HardwareMechanism;
 157     ULONG ElementCount;
 158     PCI_CARD_DESCRIPTOR CardList[ANYSIZE_ARRAY];
 159 } PCI_REGISTRY_INFO_INTERNAL, *PPCI_REGISTRY_INFO_INTERNAL;
 160
 161 typedef struct _PCI_TYPE0_CFG_CYCLE_BITS
 162 {
 163     union
 164     {
 165         struct
 166         {
 167             ULONG Reserved1:2;
 168             ULONG RegisterNumber:6;
 169             ULONG FunctionNumber:3;
 170             ULONG Reserved2:21;
 171         } bits;
 172         ULONG AsULONG;
 173     } u;
 174 } PCI_TYPE0_CFG_CYCLE_BITS, *PPCI_TYPE0_CFG_CYCLE_BITS;
 175
 176 typedef struct _PCI_TYPE1_CFG_CYCLE_BITS
 177 {
 178     union
 179     {
 180         struct
 181         {
 182             ULONG Reserved1:2;
 183             ULONG RegisterNumber:6;
 184             ULONG FunctionNumber:3;
 185             ULONG DeviceNumber:5;
 186             ULONG BusNumber:8;
 187             ULONG Reserved2:8;
 188         } bits;
 189         ULONG AsULONG;
 190     } u;
 191 } PCI_TYPE1_CFG_CYCLE_BITS, *PPCI_TYPE1_CFG_CYCLE_BITS;
 192
 193 typedef struct _ARRAY
 194 {
 195     ULONG ArraySize;
 196     PVOID Element[ANYSIZE_ARRAY];
 197 } ARRAY, *PARRAY;
 198
 199 typedef struct _HAL_BUS_HANDLER
 200 {
 201     LIST_ENTRY AllHandlers;
 202     ULONG ReferenceCount;
 203     BUS_HANDLER Handler;
 204 } HAL_BUS_HANDLER, *PHAL_BUS_HANDLER;
 205
 206 /* FUNCTIONS *****************************************************************/
 207
 208 VOID
 209 NTAPI
 210 HalpPCISynchronizeType1(
 211     IN PBUS_HANDLER BusHandler,
 212     IN PCI_SLOT_NUMBER Slot,
 213     IN PKIRQL Irql,
 214     IN PPCI_TYPE1_CFG_BITS PciCfg
 215 );
 216
 217 VOID
 218 NTAPI
 219 HalpPCIReleaseSynchronzationType1(
 220     IN PBUS_HANDLER BusHandler,
 221     IN KIRQL Irql
 222 );
 223
 224 VOID
 225 NTAPI
 226 HalpPCISynchronizeType2(
 227     IN PBUS_HANDLER BusHandler,
 228     IN PCI_SLOT_NUMBER Slot,
 229     IN PKIRQL Irql,
 230     IN PPCI_TYPE2_ADDRESS_BITS PciCfg
 231 );
 232
 233 VOID
 234 NTAPI
 235 HalpPCIReleaseSynchronizationType2(
 236     IN PBUS_HANDLER BusHandler,
 237     IN KIRQL Irql
 238 );
 239
 240 TYPE1_DEFINE(HalpPCIReadUcharType1);
 241 TYPE1_DEFINE(HalpPCIReadUshortType1);
 242 TYPE1_DEFINE(HalpPCIReadUlongType1);
 243 TYPE2_DEFINE(HalpPCIReadUcharType2);
 244 TYPE2_DEFINE(HalpPCIReadUshortType2);
 245 TYPE2_DEFINE(HalpPCIReadUlongType2);
 246 TYPE1_DEFINE(HalpPCIWriteUcharType1);
 247 TYPE1_DEFINE(HalpPCIWriteUshortType1);
 248 TYPE1_DEFINE(HalpPCIWriteUlongType1);
 249 TYPE2_DEFINE(HalpPCIWriteUcharType2);
 250 TYPE2_DEFINE(HalpPCIWriteUshortType2);
 251 TYPE2_DEFINE(HalpPCIWriteUlongType2);
 252
 253 BOOLEAN
 254 NTAPI
 255 HalpValidPCISlot(
 256     IN PBUS_HANDLER BusHandler,
 257     IN PCI_SLOT_NUMBER Slot
 258 );
 259
 260 VOID
 261 NTAPI
 262 HalpReadPCIConfig(
 263     IN PBUS_HANDLER BusHandler,
 264     IN PCI_SLOT_NUMBER Slot,
 265     IN PVOID Buffer,
 266     IN ULONG Offset,
 267     IN ULONG Length
 268 );
 269
 270 VOID
 271 NTAPI
 272 HalpWritePCIConfig(
 273     IN PBUS_HANDLER BusHandler,
 274     IN PCI_SLOT_NUMBER Slot,
 275     IN PVOID Buffer,
 276     IN ULONG Offset,
 277     IN ULONG Length
 278 );
 279
 280 ULONG
 281 NTAPI
 282 HalpGetSystemInterruptVector(
 283     ULONG BusNumber,
 284     ULONG BusInterruptLevel,
 285     ULONG BusInterruptVector,
 286     PKIRQL Irql,
 287     PKAFFINITY Affinity
 288 );
 289
 290 ULONG
 291 NTAPI
 292 HalpGetCmosData(
 293     IN ULONG BusNumber,
 294     IN ULONG SlotNumber,
 295     IN PVOID Buffer,
 296     IN ULONG Length
 297 );
 298
 299 ULONG
 300 NTAPI
 301 HalpSetCmosData(
 302     IN ULONG BusNumber,
 303     IN ULONG SlotNumber,
 304     IN PVOID Buffer,
 305     IN ULONG Length
 306 );
 307
 308 ULONG
 309 NTAPI
 310 HalpGetPCIData(
 311     IN PBUS_HANDLER BusHandler,
 312     IN PBUS_HANDLER RootBusHandler,
 313     IN PCI_SLOT_NUMBER SlotNumber,
 314     IN PVOID Buffer,
 315     IN ULONG Offset,
 316     IN ULONG Length
 317 );
 318
 319 ULONG
 320 NTAPI
 321 HalpSetPCIData(
 322     IN PBUS_HANDLER BusHandler,
 323     IN PBUS_HANDLER RootBusHandler,
 324     IN PCI_SLOT_NUMBER SlotNumber,
 325     IN PVOID Buffer,
 326     IN ULONG Offset,
 327     IN ULONG Length
 328 );
 329
 330 NTSTATUS
 331 NTAPI
 332 HalpAssignPCISlotResources(
 333     IN PBUS_HANDLER BusHandler,
 334     IN PBUS_HANDLER RootHandler,
 335     IN PUNICODE_STRING RegistryPath,
 336     IN PUNICODE_STRING DriverClassName OPTIONAL,
 337     IN PDRIVER_OBJECT DriverObject,
 338     IN PDEVICE_OBJECT DeviceObject OPTIONAL,
 339     IN ULONG Slot,
 340     IN OUT PCM_RESOURCE_LIST *pAllocatedResources
 341 );
 342
 343 VOID
 344 NTAPI
 345 HalpInitializePciBus(
 346     VOID
 347 );
 348
 349 VOID
 350 NTAPI
 351 HalpInitializePciStubs(
 352     VOID
 353 );
 354
 355 VOID
 356 NTAPI
 357 HalpInitBusHandler(
 358     VOID
 359 );
 360
 361 BOOLEAN
 362 NTAPI
 363 HalpTranslateBusAddress(
 364     IN INTERFACE_TYPE InterfaceType,
 365     IN ULONG BusNumber,
 366     IN PHYSICAL_ADDRESS BusAddress,
 367     IN OUT PULONG AddressSpace,
 368     OUT PPHYSICAL_ADDRESS TranslatedAddress
 369 );
 370
 371 NTSTATUS
 372 NTAPI
 373 HalpAssignSlotResources(
 374     IN PUNICODE_STRING RegistryPath,
 375     IN PUNICODE_STRING DriverClassName,
 376     IN PDRIVER_OBJECT DriverObject,
 377     IN PDEVICE_OBJECT DeviceObject,
 378     IN INTERFACE_TYPE BusType,
 379     IN ULONG BusNumber,
 380     IN ULONG SlotNumber,
 381     IN OUT PCM_RESOURCE_LIST *AllocatedResources
 382 );
 383
 384 BOOLEAN
 385 NTAPI
 386 HalpFindBusAddressTranslation(
 387     IN PHYSICAL_ADDRESS BusAddress,
 388     IN OUT PULONG AddressSpace,
 389     OUT PPHYSICAL_ADDRESS TranslatedAddress,
 390     IN OUT PULONG_PTR Context,
 391     IN BOOLEAN NextBus
 392 );
 393
 394 VOID
 395 NTAPI
 396 HalpRegisterPciDebuggingDeviceInfo(
 397     VOID
 398 );
 399
 400 extern ULONG HalpBusType;
 401 extern BOOLEAN HalpPCIConfigInitialized;
 402 extern BUS_HANDLER HalpFakePciBusHandler;
 403 extern ULONG HalpMinPciBus, HalpMaxPciBus;
 404
 405 /* EOF */