5af43db051b1609b66d7d222df0c8f3a2cca589d
[reactos.git] / reactos / hal / halx86 / include / bus.h
1 #pragma once
2
3 #define PCI_ADDRESS_MEMORY_SPACE 0x00000000
4
5 //
6 // Helper Macros
7 //
8 #define PASTE2(x,y) x ## y
9 #define POINTER_TO_(x) PASTE2(P,x)
10 #define READ_FROM(x) PASTE2(READ_PORT_, x)
11 #define WRITE_TO(x) PASTE2(WRITE_PORT_, x)
12
13 //
14 // Declares a PCI Register Read/Write Routine
15 //
16 #define TYPE_DEFINE(x, y) \
17 ULONG \
18 NTAPI \
19 x( \
20 IN PPCIPBUSDATA BusData, \
21 IN y PciCfg, \
22 IN PUCHAR Buffer, \
23 IN ULONG Offset \
24 )
25 #define TYPE1_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS);
26 #define TYPE2_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS);
27
28 //
29 // Defines a PCI Register Read/Write Type 1 Routine Prologue and Epilogue
30 //
31 #define TYPE1_START(x, y) \
32 TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS) \
33 { \
34 ULONG i = Offset % sizeof(ULONG); \
35 PciCfg->u.bits.RegisterNumber = Offset / sizeof(ULONG); \
36 WRITE_PORT_ULONG(BusData->Config.Type1.Address, PciCfg->u.AsULONG);
37 #define TYPE1_END(y) \
38 return sizeof(y); }
39 #define TYPE2_END TYPE1_END
40
41 //
42 // PCI Register Read Type 1 Routine
43 //
44 #define TYPE1_READ(x, y) \
45 TYPE1_START(x, y) \
46 *((POINTER_TO_(y))Buffer) = \
47 READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i)); \
48 TYPE1_END(y)
49
50 //
51 // PCI Register Write Type 1 Routine
52 //
53 #define TYPE1_WRITE(x, y) \
54 TYPE1_START(x, y) \
55 WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i), \
56 *((POINTER_TO_(y))Buffer)); \
57 TYPE1_END(y)
58
59 //
60 // Defines a PCI Register Read/Write Type 2 Routine Prologue and Epilogue
61 //
62 #define TYPE2_START(x, y) \
63 TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS) \
64 { \
65 PciCfg->u.bits.RegisterNumber = (USHORT)Offset;
66
67 //
68 // PCI Register Read Type 2 Routine
69 //
70 #define TYPE2_READ(x, y) \
71 TYPE2_START(x, y) \
72 *((POINTER_TO_(y))Buffer) = \
73 READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT); \
74 TYPE2_END(y)
75
76 //
77 // PCI Register Write Type 2 Routine
78 //
79 #define TYPE2_WRITE(x, y) \
80 TYPE2_START(x, y) \
81 WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT, \
82 *((POINTER_TO_(y))Buffer)); \
83 TYPE2_END(y)
84
85 typedef NTSTATUS
86 (NTAPI *PciIrqRange)(
87 IN PBUS_HANDLER BusHandler,
88 IN PBUS_HANDLER RootHandler,
89 IN PCI_SLOT_NUMBER PciSlot,
90 OUT PSUPPORTED_RANGE *Interrupt
91 );
92
93 typedef struct _PCIPBUSDATA
94 {
95 PCIBUSDATA CommonData;
96 union
97 {
98 struct
99 {
100 PULONG Address;
101 ULONG Data;
102 } Type1;
103 struct
104 {
105 PUCHAR CSE;
106 PUCHAR Forward;
107 ULONG Base;
108 } Type2;
109 } Config;
110 ULONG MaxDevice;
111 PciIrqRange GetIrqRange;
112 BOOLEAN BridgeConfigRead;
113 UCHAR ParentBus;
114 UCHAR Subtractive;
115 UCHAR reserved[1];
116 UCHAR SwizzleIn[4];
117 RTL_BITMAP DeviceConfigured;
118 ULONG ConfiguredBits[PCI_MAX_DEVICES * PCI_MAX_FUNCTION / 32];
119 } PCIPBUSDATA, *PPCIPBUSDATA;
120
121 typedef ULONG
122 (NTAPI *FncConfigIO)(
123 IN PPCIPBUSDATA BusData,
124 IN PVOID State,
125 IN PUCHAR Buffer,
126 IN ULONG Offset
127 );
128
129 typedef VOID
130 (NTAPI *FncSync)(
131 IN PBUS_HANDLER BusHandler,
132 IN PCI_SLOT_NUMBER Slot,
133 IN PKIRQL Irql,
134 IN PVOID State
135 );
136
137 typedef VOID
138 (NTAPI *FncReleaseSync)(
139 IN PBUS_HANDLER BusHandler,
140 IN KIRQL Irql
141 );
142
143 typedef struct _PCI_CONFIG_HANDLER
144 {
145 FncSync Synchronize;
146 FncReleaseSync ReleaseSynchronzation;
147 FncConfigIO ConfigRead[3];
148 FncConfigIO ConfigWrite[3];
149 } PCI_CONFIG_HANDLER, *PPCI_CONFIG_HANDLER;
150
151 typedef struct _PCI_REGISTRY_INFO_INTERNAL
152 {
153 UCHAR MajorRevision;
154 UCHAR MinorRevision;
155 UCHAR NoBuses; // Number Of Buses
156 UCHAR HardwareMechanism;
157 ULONG ElementCount;
158 PCI_CARD_DESCRIPTOR CardList[ANYSIZE_ARRAY];
159 } PCI_REGISTRY_INFO_INTERNAL, *PPCI_REGISTRY_INFO_INTERNAL;
160
161 typedef struct _PCI_TYPE0_CFG_CYCLE_BITS
162 {
163 union
164 {
165 struct
166 {
167 ULONG Reserved1:2;
168 ULONG RegisterNumber:6;
169 ULONG FunctionNumber:3;
170 ULONG Reserved2:21;
171 } bits;
172 ULONG AsULONG;
173 } u;
174 } PCI_TYPE0_CFG_CYCLE_BITS, *PPCI_TYPE0_CFG_CYCLE_BITS;
175
176 typedef struct _PCI_TYPE1_CFG_CYCLE_BITS
177 {
178 union
179 {
180 struct
181 {
182 ULONG Reserved1:2;
183 ULONG RegisterNumber:6;
184 ULONG FunctionNumber:3;
185 ULONG DeviceNumber:5;
186 ULONG BusNumber:8;
187 ULONG Reserved2:8;
188 } bits;
189 ULONG AsULONG;
190 } u;
191 } PCI_TYPE1_CFG_CYCLE_BITS, *PPCI_TYPE1_CFG_CYCLE_BITS;
192
193 typedef struct _ARRAY
194 {
195 ULONG ArraySize;
196 PVOID Element[ANYSIZE_ARRAY];
197 } ARRAY, *PARRAY;
198
199 typedef struct _HAL_BUS_HANDLER
200 {
201 LIST_ENTRY AllHandlers;
202 ULONG ReferenceCount;
203 BUS_HANDLER Handler;
204 } HAL_BUS_HANDLER, *PHAL_BUS_HANDLER;
205
206 /* FUNCTIONS *****************************************************************/
207
208 /* SHARED (Fake PCI-BUS HANDLER) */
209
210 extern PCI_CONFIG_HANDLER PCIConfigHandler;
211 extern PCI_CONFIG_HANDLER PCIConfigHandlerType1;
212 extern PCI_CONFIG_HANDLER PCIConfigHandlerType2;
213
214 PPCI_REGISTRY_INFO_INTERNAL
215 NTAPI
216 HalpQueryPciRegistryInfo(
217 VOID
218 );
219
220 VOID
221 NTAPI
222 HalpPCISynchronizeType1(
223 IN PBUS_HANDLER BusHandler,
224 IN PCI_SLOT_NUMBER Slot,
225 IN PKIRQL Irql,
226 IN PPCI_TYPE1_CFG_BITS PciCfg
227 );
228
229 VOID
230 NTAPI
231 HalpPCIReleaseSynchronzationType1(
232 IN PBUS_HANDLER BusHandler,
233 IN KIRQL Irql
234 );
235
236 VOID
237 NTAPI
238 HalpPCISynchronizeType2(
239 IN PBUS_HANDLER BusHandler,
240 IN PCI_SLOT_NUMBER Slot,
241 IN PKIRQL Irql,
242 IN PPCI_TYPE2_ADDRESS_BITS PciCfg
243 );
244
245 VOID
246 NTAPI
247 HalpPCIReleaseSynchronizationType2(
248 IN PBUS_HANDLER BusHandler,
249 IN KIRQL Irql
250 );
251
252 TYPE1_DEFINE(HalpPCIReadUcharType1);
253 TYPE1_DEFINE(HalpPCIReadUshortType1);
254 TYPE1_DEFINE(HalpPCIReadUlongType1);
255 TYPE2_DEFINE(HalpPCIReadUcharType2);
256 TYPE2_DEFINE(HalpPCIReadUshortType2);
257 TYPE2_DEFINE(HalpPCIReadUlongType2);
258 TYPE1_DEFINE(HalpPCIWriteUcharType1);
259 TYPE1_DEFINE(HalpPCIWriteUshortType1);
260 TYPE1_DEFINE(HalpPCIWriteUlongType1);
261 TYPE2_DEFINE(HalpPCIWriteUcharType2);
262 TYPE2_DEFINE(HalpPCIWriteUshortType2);
263 TYPE2_DEFINE(HalpPCIWriteUlongType2);
264
265 BOOLEAN
266 NTAPI
267 HalpValidPCISlot(
268 IN PBUS_HANDLER BusHandler,
269 IN PCI_SLOT_NUMBER Slot
270 );
271
272 VOID
273 NTAPI
274 HalpReadPCIConfig(
275 IN PBUS_HANDLER BusHandler,
276 IN PCI_SLOT_NUMBER Slot,
277 IN PVOID Buffer,
278 IN ULONG Offset,
279 IN ULONG Length
280 );
281
282 VOID
283 NTAPI
284 HalpWritePCIConfig(
285 IN PBUS_HANDLER BusHandler,
286 IN PCI_SLOT_NUMBER Slot,
287 IN PVOID Buffer,
288 IN ULONG Offset,
289 IN ULONG Length
290 );
291
292 ULONG
293 NTAPI
294 HalpGetPCIData(
295 IN PBUS_HANDLER BusHandler,
296 IN PBUS_HANDLER RootBusHandler,
297 IN PCI_SLOT_NUMBER SlotNumber,
298 IN PVOID Buffer,
299 IN ULONG Offset,
300 IN ULONG Length
301 );
302
303 ULONG
304 NTAPI
305 HalpSetPCIData(
306 IN PBUS_HANDLER BusHandler,
307 IN PBUS_HANDLER RootBusHandler,
308 IN PCI_SLOT_NUMBER SlotNumber,
309 IN PVOID Buffer,
310 IN ULONG Offset,
311 IN ULONG Length
312 );
313
314 NTSTATUS
315 NTAPI
316 HalpAssignPCISlotResources(
317 IN PBUS_HANDLER BusHandler,
318 IN PBUS_HANDLER RootHandler,
319 IN PUNICODE_STRING RegistryPath,
320 IN PUNICODE_STRING DriverClassName OPTIONAL,
321 IN PDRIVER_OBJECT DriverObject,
322 IN PDEVICE_OBJECT DeviceObject OPTIONAL,
323 IN ULONG Slot,
324 IN OUT PCM_RESOURCE_LIST *pAllocatedResources
325 );
326
327 /* NON-LEGACY */
328
329 ULONG
330 NTAPI
331 HalpGetSystemInterruptVector_Acpi(
332 ULONG BusNumber,
333 ULONG BusInterruptLevel,
334 ULONG BusInterruptVector,
335 PKIRQL Irql,
336 PKAFFINITY Affinity
337 );
338
339 ULONG
340 NTAPI
341 HalpGetCmosData(
342 IN ULONG BusNumber,
343 IN ULONG SlotNumber,
344 IN PVOID Buffer,
345 IN ULONG Length
346 );
347
348 ULONG
349 NTAPI
350 HalpSetCmosData(
351 IN ULONG BusNumber,
352 IN ULONG SlotNumber,
353 IN PVOID Buffer,
354 IN ULONG Length
355 );
356
357 VOID
358 NTAPI
359 HalpInitializePciBus(
360 VOID
361 );
362
363 VOID
364 NTAPI
365 HalpInitializePciStubs(
366 VOID
367 );
368
369 BOOLEAN
370 NTAPI
371 HalpTranslateBusAddress(
372 IN INTERFACE_TYPE InterfaceType,
373 IN ULONG BusNumber,
374 IN PHYSICAL_ADDRESS BusAddress,
375 IN OUT PULONG AddressSpace,
376 OUT PPHYSICAL_ADDRESS TranslatedAddress
377 );
378
379 BOOLEAN
380 NTAPI
381 HaliTranslateBusAddress(
382 IN INTERFACE_TYPE InterfaceType,
383 IN ULONG BusNumber,
384 IN PHYSICAL_ADDRESS BusAddress,
385 IN OUT PULONG AddressSpace,
386 OUT PPHYSICAL_ADDRESS TranslatedAddress
387 );
388
389 NTSTATUS
390 NTAPI
391 HalpAssignSlotResources(
392 IN PUNICODE_STRING RegistryPath,
393 IN PUNICODE_STRING DriverClassName,
394 IN PDRIVER_OBJECT DriverObject,
395 IN PDEVICE_OBJECT DeviceObject,
396 IN INTERFACE_TYPE BusType,
397 IN ULONG BusNumber,
398 IN ULONG SlotNumber,
399 IN OUT PCM_RESOURCE_LIST *AllocatedResources
400 );
401
402 BOOLEAN
403 NTAPI
404 HalpFindBusAddressTranslation(
405 IN PHYSICAL_ADDRESS BusAddress,
406 IN OUT PULONG AddressSpace,
407 OUT PPHYSICAL_ADDRESS TranslatedAddress,
408 IN OUT PULONG_PTR Context,
409 IN BOOLEAN NextBus
410 );
411
412 VOID
413 NTAPI
414 HalpRegisterPciDebuggingDeviceInfo(
415 VOID
416 );
417
418 /* LEGACY */
419
420 NTSTATUS
421 NTAPI
422 HalpAdjustPCIResourceList(IN PBUS_HANDLER BusHandler,
423 IN PBUS_HANDLER RootHandler,
424 IN OUT PIO_RESOURCE_REQUIREMENTS_LIST *pResourceList);
425
426 ULONG
427 NTAPI
428 HalpGetPCIIntOnISABus(IN PBUS_HANDLER BusHandler,
429 IN PBUS_HANDLER RootHandler,
430 IN ULONG BusInterruptLevel,
431 IN ULONG BusInterruptVector,
432 OUT PKIRQL Irql,
433 OUT PKAFFINITY Affinity);
434 VOID
435 NTAPI
436 HalpPCIPin2ISALine(IN PBUS_HANDLER BusHandler,
437 IN PBUS_HANDLER RootHandler,
438 IN PCI_SLOT_NUMBER SlotNumber,
439 IN PPCI_COMMON_CONFIG PciData);
440
441 VOID
442 NTAPI
443 HalpPCIISALine2Pin(IN PBUS_HANDLER BusHandler,
444 IN PBUS_HANDLER RootHandler,
445 IN PCI_SLOT_NUMBER SlotNumber,
446 IN PPCI_COMMON_CONFIG PciNewData,
447 IN PPCI_COMMON_CONFIG PciOldData);
448
449 NTSTATUS
450 NTAPI
451 HalpGetISAFixedPCIIrq(IN PBUS_HANDLER BusHandler,
452 IN PBUS_HANDLER RootHandler,
453 IN PCI_SLOT_NUMBER PciSlot,
454 OUT PSUPPORTED_RANGE *Range);
455
456 VOID
457 NTAPI
458 HalpInitBusHandler(
459 VOID
460 );
461
462 PBUS_HANDLER
463 FASTCALL
464 HaliReferenceHandlerForConfigSpace(
465 IN BUS_DATA_TYPE ConfigType,
466 IN ULONG BusNumber
467 );
468
469 ULONG
470 NTAPI
471 HalpNoBusData(
472 IN PBUS_HANDLER BusHandler,
473 IN PBUS_HANDLER RootHandler,
474 IN ULONG SlotNumber,
475 IN PVOID Buffer,
476 IN ULONG Offset,
477 IN ULONG Length
478 );
479
480 ULONG
481 NTAPI
482 HalpcGetCmosData(
483 IN PBUS_HANDLER BusHandler,
484 IN PBUS_HANDLER RootHandler,
485 IN ULONG SlotNumber,
486 IN PVOID Buffer,
487 IN ULONG Offset,
488 IN ULONG Length
489 );
490
491 ULONG
492 NTAPI
493 HalpcSetCmosData(
494 IN PBUS_HANDLER BusHandler,
495 IN PBUS_HANDLER RootHandler,
496 IN ULONG SlotNumber,
497 IN PVOID Buffer,
498 IN ULONG Offset,
499 IN ULONG Length
500 );
501
502 BOOLEAN
503 NTAPI
504 HalpTranslateSystemBusAddress(
505 IN PBUS_HANDLER BusHandler,
506 IN PBUS_HANDLER RootHandler,
507 IN PHYSICAL_ADDRESS BusAddress,
508 IN OUT PULONG AddressSpace,
509 OUT PPHYSICAL_ADDRESS TranslatedAddress
510 );
511
512 BOOLEAN
513 NTAPI
514 HalpTranslateIsaBusAddress(
515 IN PBUS_HANDLER BusHandler,
516 IN PBUS_HANDLER RootHandler,
517 IN PHYSICAL_ADDRESS BusAddress,
518 IN OUT PULONG AddressSpace,
519 OUT PPHYSICAL_ADDRESS TranslatedAddress
520 );
521
522 ULONG
523 NTAPI
524 HalpGetSystemInterruptVector(
525 IN PBUS_HANDLER BusHandler,
526 IN PBUS_HANDLER RootHandler,
527 IN ULONG BusInterruptLevel,
528 IN ULONG BusInterruptVector,
529 OUT PKIRQL Irql,
530 OUT PKAFFINITY Affinity
531 );
532
533 extern ULONG HalpBusType;
534 extern BOOLEAN HalpPCIConfigInitialized;
535 extern BUS_HANDLER HalpFakePciBusHandler;
536 extern ULONG HalpMinPciBus, HalpMaxPciBus;
537
538 /* EOF */