reactos/hal/halx86/include/bus.h

   1 #ifndef __INTERNAL_HAL_BUS_H
   2 #define __INTERNAL_HAL_BUS_H
   3
   4 //
   5 // Helper Macros
   6 //
   7 #define PASTE2(x,y)                                                     x ## y
   8 #define POINTER_TO_(x)                                                  PASTE2(P,x)
   9 #define READ_FROM(x)                                                    PASTE2(READ_PORT_, x)
  10 #define WRITE_TO(x)                                                     PASTE2(WRITE_PORT_, x)
  11
  12 //
  13 // Declares a PCI Register Read/Write Routine
  14 //
  15 #define TYPE_DEFINE(x, y)                                               \
  16     ULONG                                                               \
  17     NTAPI                                                               \
  18     x(                                                                  \
  19         IN PPCIPBUSDATA BusData,                                        \
  20         IN y PciCfg,                                                    \
  21         IN PUCHAR Buffer,                                               \
  22         IN ULONG Offset                                                 \
  23     )
  24 #define TYPE1_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS);
  25 #define TYPE2_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS);
  26
  27 //
  28 // Defines a PCI Register Read/Write Type 1 Routine Prologue and Epilogue
  29 //
  30 #define TYPE1_START(x, y)                                               \
  31     TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS)                                 \
  32 {                                                                       \
  33     ULONG i = Offset % sizeof(ULONG);                                   \
  34     PciCfg->u.bits.RegisterNumber = Offset / sizeof(ULONG);             \
  35     WRITE_PORT_ULONG(BusData->Config.Type1.Address, PciCfg->u.AsULONG);
  36 #define TYPE1_END(y)                                                    \
  37     return sizeof(y); }
  38 #define TYPE2_END       TYPE1_END
  39
  40 //
  41 // PCI Register Read Type 1 Routine
  42 //
  43 #define TYPE1_READ(x, y)                                                \
  44     TYPE1_START(x, y)                                                   \
  45     *((POINTER_TO_(y))Buffer) =                                         \
  46     READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i));     \
  47     TYPE1_END(y)
  48
  49 //
  50 // PCI Register Write Type 1 Routine
  51 //
  52 #define TYPE1_WRITE(x, y)                                               \
  53     TYPE1_START(x, y)                                                   \
  54     WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i),       \
  55                 *((POINTER_TO_(y))Buffer));                             \
  56     TYPE1_END(y)
  57
  58 //
  59 // Defines a PCI Register Read/Write Type 2 Routine Prologue and Epilogue
  60 //
  61 #define TYPE2_START(x, y)                                               \
  62     TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS)                             \
  63 {                                                                       \
  64     PciCfg->u.bits.RegisterNumber = (USHORT)Offset;
  65
  66 //
  67 // PCI Register Read Type 2 Routine
  68 //
  69 #define TYPE2_READ(x, y)                                                \
  70     TYPE2_START(x, y)                                                   \
  71     *((POINTER_TO_(y))Buffer) =                                         \
  72         READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT);        \
  73     TYPE2_END(y)
  74
  75 //
  76 // PCI Register Write Type 2 Routine
  77 //
  78 #define TYPE2_WRITE(x, y)                                               \
  79     TYPE2_START(x, y)                                                   \
  80     WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT,              \
  81                 *((POINTER_TO_(y))Buffer));                             \
  82     TYPE2_END(y)
  83
  84 typedef struct _PCIPBUSDATA
  85 {
  86     PCIBUSDATA CommonData;
  87     union
  88     {
  89         struct
  90         {
  91             PULONG Address;
  92             ULONG Data;
  93         } Type1;
  94         struct
  95         {
  96             PUCHAR CSE;
  97             PUCHAR Forward;
  98             ULONG Base;
  99         } Type2;
 100     } Config;
 101     ULONG MaxDevice;
 102 } PCIPBUSDATA, *PPCIPBUSDATA;
 103
 104 typedef ULONG
 105 (NTAPI *FncConfigIO)(
 106     IN PPCIPBUSDATA BusData,
 107     IN PVOID State,
 108     IN PUCHAR Buffer,
 109     IN ULONG Offset
 110 );
 111
 112 typedef VOID
 113 (NTAPI *FncSync)(
 114     IN PBUS_HANDLER BusHandler,
 115     IN PCI_SLOT_NUMBER Slot,
 116     IN PKIRQL Irql,
 117     IN PVOID State
 118 );
 119
 120 typedef VOID
 121 (NTAPI *FncReleaseSync)(
 122     IN PBUS_HANDLER BusHandler,
 123     IN KIRQL Irql
 124 );
 125
 126 typedef struct _PCI_CONFIG_HANDLER
 127 {
 128     FncSync Synchronize;
 129     FncReleaseSync ReleaseSynchronzation;
 130     FncConfigIO ConfigRead[3];
 131     FncConfigIO ConfigWrite[3];
 132 } PCI_CONFIG_HANDLER, *PPCI_CONFIG_HANDLER;
 133
 134 typedef struct _PCI_REGISTRY_INFO_INTERNAL
 135 {
 136     UCHAR MajorRevision;
 137     UCHAR MinorRevision;
 138     UCHAR NoBuses;
 139     UCHAR HardwareMechanism;
 140     ULONG ElementCount;
 141     PCI_CARD_DESCRIPTOR CardList[ANYSIZE_ARRAY];
 142 } PCI_REGISTRY_INFO_INTERNAL, *PPCI_REGISTRY_INFO_INTERNAL;
 143
 144 /* FUNCTIONS *****************************************************************/
 145
 146 VOID
 147 NTAPI
 148 HalpPCISynchronizeType1(
 149     IN PBUS_HANDLER BusHandler,
 150     IN PCI_SLOT_NUMBER Slot,
 151     IN PKIRQL Irql,
 152     IN PPCI_TYPE1_CFG_BITS PciCfg
 153 );
 154
 155 VOID
 156 NTAPI
 157 HalpPCIReleaseSynchronzationType1(
 158     IN PBUS_HANDLER BusHandler,
 159     IN KIRQL Irql
 160 );
 161
 162 VOID
 163 NTAPI
 164 HalpPCISynchronizeType2(
 165     IN PBUS_HANDLER BusHandler,
 166     IN PCI_SLOT_NUMBER Slot,
 167     IN PKIRQL Irql,
 168     IN PPCI_TYPE2_ADDRESS_BITS PciCfg
 169 );
 170
 171 VOID
 172 NTAPI
 173 HalpPCIReleaseSynchronizationType2(
 174     IN PBUS_HANDLER BusHandler,
 175     IN KIRQL Irql
 176 );
 177
 178 TYPE1_DEFINE(HalpPCIReadUcharType1);
 179 TYPE1_DEFINE(HalpPCIReadUshortType1);
 180 TYPE1_DEFINE(HalpPCIReadUlongType1);
 181 TYPE2_DEFINE(HalpPCIReadUcharType2);
 182 TYPE2_DEFINE(HalpPCIReadUshortType2);
 183 TYPE2_DEFINE(HalpPCIReadUlongType2);
 184 TYPE1_DEFINE(HalpPCIWriteUcharType1);
 185 TYPE1_DEFINE(HalpPCIWriteUshortType1);
 186 TYPE1_DEFINE(HalpPCIWriteUlongType1);
 187 TYPE2_DEFINE(HalpPCIWriteUcharType2);
 188 TYPE2_DEFINE(HalpPCIWriteUshortType2);
 189 TYPE2_DEFINE(HalpPCIWriteUlongType2);
 190
 191 BOOLEAN
 192 NTAPI
 193 HalpValidPCISlot(
 194     IN PBUS_HANDLER BusHandler,
 195     IN PCI_SLOT_NUMBER Slot
 196 );
 197
 198 VOID
 199 NTAPI
 200 HalpReadPCIConfig(
 201     IN PBUS_HANDLER BusHandler,
 202     IN PCI_SLOT_NUMBER Slot,
 203     IN PVOID Buffer,
 204     IN ULONG Offset,
 205     IN ULONG Length
 206 );
 207
 208 VOID
 209 NTAPI
 210 HalpWritePCIConfig(
 211     IN PBUS_HANDLER BusHandler,
 212     IN PCI_SLOT_NUMBER Slot,
 213     IN PVOID Buffer,
 214     IN ULONG Offset,
 215     IN ULONG Length
 216 );
 217
 218 ULONG
 219 NTAPI
 220 HalpGetSystemInterruptVector(
 221     ULONG BusNumber,
 222     ULONG BusInterruptLevel,
 223     ULONG BusInterruptVector,
 224     PKIRQL Irql,
 225     PKAFFINITY Affinity
 226 );
 227
 228 ULONG
 229 NTAPI
 230 HalpGetCmosData(
 231     IN ULONG BusNumber,
 232     IN ULONG SlotNumber,
 233     IN PVOID Buffer,
 234     IN ULONG Length
 235 );
 236
 237 ULONG
 238 NTAPI
 239 HalpSetCmosData(
 240     IN ULONG BusNumber,
 241     IN ULONG SlotNumber,
 242     IN PVOID Buffer,
 243     IN ULONG Length
 244 );
 245
 246 ULONG
 247 NTAPI
 248 HalpGetPCIData(
 249     IN PBUS_HANDLER BusHandler,
 250     IN PBUS_HANDLER RootBusHandler,
 251     IN PCI_SLOT_NUMBER SlotNumber,
 252     IN PUCHAR Buffer,
 253     IN ULONG Offset,
 254     IN ULONG Length
 255 );
 256
 257 ULONG
 258 NTAPI
 259 HalpSetPCIData(
 260     IN PBUS_HANDLER BusHandler,
 261     IN PBUS_HANDLER RootBusHandler,
 262     IN PCI_SLOT_NUMBER SlotNumber,
 263     IN PUCHAR Buffer,
 264     IN ULONG Offset,
 265     IN ULONG Length
 266 );
 267
 268 NTSTATUS
 269 NTAPI
 270 HalpAssignPCISlotResources(
 271     IN PBUS_HANDLER BusHandler,
 272     IN PBUS_HANDLER RootHandler,
 273     IN PUNICODE_STRING RegistryPath,
 274     IN PUNICODE_STRING DriverClassName OPTIONAL,
 275     IN PDRIVER_OBJECT DriverObject,
 276     IN PDEVICE_OBJECT DeviceObject OPTIONAL,
 277     IN ULONG Slot,
 278     IN OUT PCM_RESOURCE_LIST *pAllocatedResources
 279 );
 280
 281 VOID
 282 NTAPI
 283 HalpInitializePciBus(
 284     VOID
 285 );
 286
 287 extern ULONG HalpBusType;
 288 extern BOOLEAN HalpPCIConfigInitialized;
 289 extern BUS_HANDLER HalpFakePciBusHandler;
 290 extern ULONG HalpMinPciBus, HalpMaxPciBus;
 291
 292 #endif /* __INTERNAL_HAL_BUS_H */
 293
 294 /* EOF */
 295
 296