reactos/hal/halx86/include/bus.h

   1 #pragma once
   2
   3 #define PCI_ADDRESS_MEMORY_SPACE            0x00000000
   4
   5 //
   6 // Helper Macros
   7 //
   8 #define PASTE2(x,y)                                                     x ## y
   9 #define POINTER_TO_(x)                                                  PASTE2(P,x)
  10 #define READ_FROM(x)                                                    PASTE2(READ_PORT_, x)
  11 #define WRITE_TO(x)                                                     PASTE2(WRITE_PORT_, x)
  12
  13 //
  14 // Declares a PCI Register Read/Write Routine
  15 //
  16 #define TYPE_DEFINE(x, y)                                               \
  17     ULONG                                                               \
  18     NTAPI                                                               \
  19     x(                                                                  \
  20         IN PPCIPBUSDATA BusData,                                        \
  21         IN y PciCfg,                                                    \
  22         IN PUCHAR Buffer,                                               \
  23         IN ULONG Offset                                                 \
  24     )
  25 #define TYPE1_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS);
  26 #define TYPE2_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS);
  27
  28 //
  29 // Defines a PCI Register Read/Write Type 1 Routine Prologue and Epilogue
  30 //
  31 #define TYPE1_START(x, y)                                               \
  32     TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS)                                 \
  33 {                                                                       \
  34     ULONG i = Offset % sizeof(ULONG);                                   \
  35     PciCfg->u.bits.RegisterNumber = Offset / sizeof(ULONG);             \
  36     WRITE_PORT_ULONG(BusData->Config.Type1.Address, PciCfg->u.AsULONG);
  37 #define TYPE1_END(y)                                                    \
  38     return sizeof(y); }
  39 #define TYPE2_END       TYPE1_END
  40
  41 //
  42 // PCI Register Read Type 1 Routine
  43 //
  44 #define TYPE1_READ(x, y)                                                \
  45     TYPE1_START(x, y)                                                   \
  46     *((POINTER_TO_(y))Buffer) =                                         \
  47     READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i));     \
  48     TYPE1_END(y)
  49
  50 //
  51 // PCI Register Write Type 1 Routine
  52 //
  53 #define TYPE1_WRITE(x, y)                                               \
  54     TYPE1_START(x, y)                                                   \
  55     WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i),       \
  56                 *((POINTER_TO_(y))Buffer));                             \
  57     TYPE1_END(y)
  58
  59 //
  60 // Defines a PCI Register Read/Write Type 2 Routine Prologue and Epilogue
  61 //
  62 #define TYPE2_START(x, y)                                               \
  63     TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS)                             \
  64 {                                                                       \
  65     PciCfg->u.bits.RegisterNumber = (USHORT)Offset;
  66
  67 //
  68 // PCI Register Read Type 2 Routine
  69 //
  70 #define TYPE2_READ(x, y)                                                \
  71     TYPE2_START(x, y)                                                   \
  72     *((POINTER_TO_(y))Buffer) =                                         \
  73         READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT);        \
  74     TYPE2_END(y)
  75
  76 //
  77 // PCI Register Write Type 2 Routine
  78 //
  79 #define TYPE2_WRITE(x, y)                                               \
  80     TYPE2_START(x, y)                                                   \
  81     WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT,              \
  82                 *((POINTER_TO_(y))Buffer));                             \
  83     TYPE2_END(y)
  84
  85 typedef NTSTATUS
  86 (NTAPI *PciIrqRange)(
  87     IN PBUS_HANDLER BusHandler,
  88     IN PBUS_HANDLER RootHandler,
  89     IN PCI_SLOT_NUMBER PciSlot,
  90     OUT PSUPPORTED_RANGE *Interrupt
  91 );
  92
  93 typedef struct _PCIPBUSDATA
  94 {
  95     PCIBUSDATA CommonData;
  96     union
  97     {
  98         struct
  99         {
 100             PULONG Address;
 101             ULONG Data;
 102         } Type1;
 103         struct
 104         {
 105             PUCHAR CSE;
 106             PUCHAR Forward;
 107             ULONG Base;
 108         } Type2;
 109     } Config;
 110     ULONG MaxDevice;
 111     PciIrqRange GetIrqRange;
 112     BOOLEAN BridgeConfigRead;
 113     UCHAR ParentBus;
 114     UCHAR Subtractive;
 115     UCHAR reserved[1];
 116     UCHAR SwizzleIn[4];
 117     RTL_BITMAP DeviceConfigured;
 118     ULONG ConfiguredBits[PCI_MAX_DEVICES * PCI_MAX_FUNCTION / 32];
 119 } PCIPBUSDATA, *PPCIPBUSDATA;
 120
 121 typedef ULONG
 122 (NTAPI *FncConfigIO)(
 123     IN PPCIPBUSDATA BusData,
 124     IN PVOID State,
 125     IN PUCHAR Buffer,
 126     IN ULONG Offset
 127 );
 128
 129 typedef VOID
 130 (NTAPI *FncSync)(
 131     IN PBUS_HANDLER BusHandler,
 132     IN PCI_SLOT_NUMBER Slot,
 133     IN PKIRQL Irql,
 134     IN PVOID State
 135 );
 136
 137 typedef VOID
 138 (NTAPI *FncReleaseSync)(
 139     IN PBUS_HANDLER BusHandler,
 140     IN KIRQL Irql
 141 );
 142
 143 typedef struct _PCI_CONFIG_HANDLER
 144 {
 145     FncSync Synchronize;
 146     FncReleaseSync ReleaseSynchronzation;
 147     FncConfigIO ConfigRead[3];
 148     FncConfigIO ConfigWrite[3];
 149 } PCI_CONFIG_HANDLER, *PPCI_CONFIG_HANDLER;
 150
 151 typedef struct _PCI_REGISTRY_INFO_INTERNAL
 152 {
 153     UCHAR MajorRevision;
 154     UCHAR MinorRevision;
 155     UCHAR NoBuses; // Number Of Buses
 156     UCHAR HardwareMechanism;
 157     ULONG ElementCount;
 158     PCI_CARD_DESCRIPTOR CardList[ANYSIZE_ARRAY];
 159 } PCI_REGISTRY_INFO_INTERNAL, *PPCI_REGISTRY_INFO_INTERNAL;
 160
 161 typedef struct _ARRAY
 162 {
 163     ULONG ArraySize;
 164     PVOID Element[ANYSIZE_ARRAY];
 165 } ARRAY, *PARRAY;
 166
 167 typedef struct _HAL_BUS_HANDLER
 168 {
 169     LIST_ENTRY AllHandlers;
 170     ULONG ReferenceCount;
 171     BUS_HANDLER Handler;
 172 } HAL_BUS_HANDLER, *PHAL_BUS_HANDLER;
 173
 174 /* FUNCTIONS *****************************************************************/
 175
 176 VOID
 177 NTAPI
 178 HalpPCISynchronizeType1(
 179     IN PBUS_HANDLER BusHandler,
 180     IN PCI_SLOT_NUMBER Slot,
 181     IN PKIRQL Irql,
 182     IN PPCI_TYPE1_CFG_BITS PciCfg
 183 );
 184
 185 VOID
 186 NTAPI
 187 HalpPCIReleaseSynchronzationType1(
 188     IN PBUS_HANDLER BusHandler,
 189     IN KIRQL Irql
 190 );
 191
 192 VOID
 193 NTAPI
 194 HalpPCISynchronizeType2(
 195     IN PBUS_HANDLER BusHandler,
 196     IN PCI_SLOT_NUMBER Slot,
 197     IN PKIRQL Irql,
 198     IN PPCI_TYPE2_ADDRESS_BITS PciCfg
 199 );
 200
 201 VOID
 202 NTAPI
 203 HalpPCIReleaseSynchronizationType2(
 204     IN PBUS_HANDLER BusHandler,
 205     IN KIRQL Irql
 206 );
 207
 208 TYPE1_DEFINE(HalpPCIReadUcharType1);
 209 TYPE1_DEFINE(HalpPCIReadUshortType1);
 210 TYPE1_DEFINE(HalpPCIReadUlongType1);
 211 TYPE2_DEFINE(HalpPCIReadUcharType2);
 212 TYPE2_DEFINE(HalpPCIReadUshortType2);
 213 TYPE2_DEFINE(HalpPCIReadUlongType2);
 214 TYPE1_DEFINE(HalpPCIWriteUcharType1);
 215 TYPE1_DEFINE(HalpPCIWriteUshortType1);
 216 TYPE1_DEFINE(HalpPCIWriteUlongType1);
 217 TYPE2_DEFINE(HalpPCIWriteUcharType2);
 218 TYPE2_DEFINE(HalpPCIWriteUshortType2);
 219 TYPE2_DEFINE(HalpPCIWriteUlongType2);
 220
 221 BOOLEAN
 222 NTAPI
 223 HalpValidPCISlot(
 224     IN PBUS_HANDLER BusHandler,
 225     IN PCI_SLOT_NUMBER Slot
 226 );
 227
 228 VOID
 229 NTAPI
 230 HalpReadPCIConfig(
 231     IN PBUS_HANDLER BusHandler,
 232     IN PCI_SLOT_NUMBER Slot,
 233     IN PVOID Buffer,
 234     IN ULONG Offset,
 235     IN ULONG Length
 236 );
 237
 238 VOID
 239 NTAPI
 240 HalpWritePCIConfig(
 241     IN PBUS_HANDLER BusHandler,
 242     IN PCI_SLOT_NUMBER Slot,
 243     IN PVOID Buffer,
 244     IN ULONG Offset,
 245     IN ULONG Length
 246 );
 247
 248 ULONG
 249 NTAPI
 250 HalpGetSystemInterruptVector(
 251     ULONG BusNumber,
 252     ULONG BusInterruptLevel,
 253     ULONG BusInterruptVector,
 254     PKIRQL Irql,
 255     PKAFFINITY Affinity
 256 );
 257
 258 ULONG
 259 NTAPI
 260 HalpGetCmosData(
 261     IN ULONG BusNumber,
 262     IN ULONG SlotNumber,
 263     IN PVOID Buffer,
 264     IN ULONG Length
 265 );
 266
 267 ULONG
 268 NTAPI
 269 HalpSetCmosData(
 270     IN ULONG BusNumber,
 271     IN ULONG SlotNumber,
 272     IN PVOID Buffer,
 273     IN ULONG Length
 274 );
 275
 276 ULONG
 277 NTAPI
 278 HalpGetPCIData(
 279     IN PBUS_HANDLER BusHandler,
 280     IN PBUS_HANDLER RootBusHandler,
 281     IN PCI_SLOT_NUMBER SlotNumber,
 282     IN PVOID Buffer,
 283     IN ULONG Offset,
 284     IN ULONG Length
 285 );
 286
 287 ULONG
 288 NTAPI
 289 HalpSetPCIData(
 290     IN PBUS_HANDLER BusHandler,
 291     IN PBUS_HANDLER RootBusHandler,
 292     IN PCI_SLOT_NUMBER SlotNumber,
 293     IN PVOID Buffer,
 294     IN ULONG Offset,
 295     IN ULONG Length
 296 );
 297
 298 NTSTATUS
 299 NTAPI
 300 HalpAssignPCISlotResources(
 301     IN PBUS_HANDLER BusHandler,
 302     IN PBUS_HANDLER RootHandler,
 303     IN PUNICODE_STRING RegistryPath,
 304     IN PUNICODE_STRING DriverClassName OPTIONAL,
 305     IN PDRIVER_OBJECT DriverObject,
 306     IN PDEVICE_OBJECT DeviceObject OPTIONAL,
 307     IN ULONG Slot,
 308     IN OUT PCM_RESOURCE_LIST *pAllocatedResources
 309 );
 310
 311 VOID
 312 NTAPI
 313 HalpInitializePciBus(
 314     VOID
 315 );
 316
 317 VOID
 318 NTAPI
 319 HalpInitializePciStubs(
 320     VOID
 321 );
 322
 323 VOID
 324 NTAPI
 325 HalpInitBusHandler(
 326     VOID
 327 );
 328
 329 BOOLEAN
 330 NTAPI
 331 HalpTranslateBusAddress(
 332     IN INTERFACE_TYPE InterfaceType,
 333     IN ULONG BusNumber,
 334     IN PHYSICAL_ADDRESS BusAddress,
 335     IN OUT PULONG AddressSpace,
 336     OUT PPHYSICAL_ADDRESS TranslatedAddress
 337 );
 338
 339 NTSTATUS
 340 NTAPI
 341 HalpAssignSlotResources(
 342     IN PUNICODE_STRING RegistryPath,
 343     IN PUNICODE_STRING DriverClassName,
 344     IN PDRIVER_OBJECT DriverObject,
 345     IN PDEVICE_OBJECT DeviceObject,
 346     IN INTERFACE_TYPE BusType,
 347     IN ULONG BusNumber,
 348     IN ULONG SlotNumber,
 349     IN OUT PCM_RESOURCE_LIST *AllocatedResources
 350 );
 351
 352 BOOLEAN
 353 NTAPI
 354 HalpFindBusAddressTranslation(
 355     IN PHYSICAL_ADDRESS BusAddress,
 356     IN OUT PULONG AddressSpace,
 357     OUT PPHYSICAL_ADDRESS TranslatedAddress,
 358     IN OUT PULONG_PTR Context,
 359     IN BOOLEAN NextBus
 360 );
 361
 362 extern ULONG HalpBusType;
 363 extern BOOLEAN HalpPCIConfigInitialized;
 364 extern BUS_HANDLER HalpFakePciBusHandler;
 365 extern ULONG HalpMinPciBus, HalpMaxPciBus;
 366
 367 /* EOF */