reactos/hal/halx86/include/hal.h

   1 /*
   2  *
   3  */
   4
   5 #ifndef __INTERNAL_HAL_HAL_H
   6 #define __INTERNAL_HAL_HAL_H
   7
   8 #define HAL_APC_REQUEST     0
   9 #define HAL_DPC_REQUEST     1
  10
  11 /* display.c */
  12 VOID FASTCALL HalInitializeDisplay (PLOADER_PARAMETER_BLOCK LoaderBlock);
  13 VOID FASTCALL HalClearDisplay (UCHAR CharAttribute);
  14
  15 /* adapter.c */
  16 PADAPTER_OBJECT STDCALL HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
  17
  18 /* bus.c */
  19 VOID HalpInitBusHandlers (VOID);
  20
  21 /* irql.c */
  22 VOID HalpInitPICs(VOID);
  23
  24 /* udelay.c */
  25 VOID HalpCalibrateStallExecution(VOID);
  26
  27 /* pci.c */
  28 VOID HalpInitPciBus (VOID);
  29
  30 /* enum.c */
  31 VOID HalpStartEnumerator (VOID);
  32
  33 /* dma.c */
  34 VOID HalpInitDma (VOID);
  35
  36 /* mem.c */
  37 PVOID HalpMapPhysMemory(ULONG PhysAddr, ULONG Size);
  38
  39 /* Non-generic initialization */
  40 VOID HalpInitPhase0 (VOID);
  41
  42 /* DMA Page Register Structure
  43  080     DMA        RESERVED
  44  081     DMA        Page Register (channel 2)
  45  082     DMA        Page Register (channel 3)
  46  083     DMA        Page Register (channel 1)
  47  084     DMA        RESERVED
  48  085     DMA        RESERVED
  49  086     DMA        RESERVED
  50  087     DMA        Page Register (channel 0)
  51  088     DMA        RESERVED
  52  089     PS/2-DMA   Page Register (channel 6)
  53  08A     PS/2-DMA   Page Register (channel 7)
  54  08B     PS/2-DMA   Page Register (channel 5)
  55  08C     PS/2-DMA   RESERVED
  56  08D     PS/2-DMA   RESERVED
  57  08E     PS/2-DMA   RESERVED
  58  08F     PS/2-DMA   Page Register (channel 4)
  59 */
  60  typedef struct _DMA_PAGE{
  61   UCHAR Reserved1;
  62   UCHAR Channel2;
  63   UCHAR Channel3;
  64   UCHAR Channel1;
  65   UCHAR Reserved2[3];
  66   UCHAR Channel0;
  67   UCHAR Reserved3;
  68   UCHAR Channel6;
  69   UCHAR Channel7;
  70   UCHAR Channel5;
  71   UCHAR Reserved4[3];
  72   UCHAR Channel4;
  73 } DMA_PAGE, *PDMA_PAGE;
  74
  75 /* DMA Channel Mask Register Structure
  76
  77 MSB                             LSB
  78       x   x   x   x     x   x   x   x
  79       -------------------   -   -----
  80                |            |     |     00 - Select channel 0 mask bit
  81                |            |     \---- 01 - Select channel 1 mask bit
  82                |            |           10 - Select channel 2 mask bit
  83                |            |           11 - Select channel 3 mask bit
  84                |            |
  85                |            \----------  0 - Clear mask bit
  86                |                         1 - Set mask bit
  87                |
  88                \----------------------- xx - Reserved
  89 */
  90 typedef struct _DMA_CHANNEL_MASK {
  91   UCHAR Channel : 2;
  92   UCHAR SetMask : 1;
  93   UCHAR Reserved : 5;
  94 } DMA_CHANNEL_MASK, *PDMA_CHANNEL_MASK;
  95
  96 /* DMA Mask Register Structure
  97
  98    MSB                             LSB
  99       x   x   x   x     x   x   x   x
 100       \---/   -   -     -----   -----
 101         |     |   |       |       |     00 - Channel 0 select
 102         |     |   |       |       \---- 01 - Channel 1 select
 103         |     |   |       |             10 - Channel 2 select
 104         |     |   |       |             11 - Channel 3 select
 105         |     |   |       |
 106         |     |   |       |             00 - Verify transfer
 107         |     |   |       \------------ 01 - Write transfer
 108         |     |   |                     10 - Read transfer
 109         |     |   |
 110         |     |   \--------------------  0 - Autoinitialized
 111         |     |                          1 - Non-autoinitialized
 112         |     |
 113         |     \------------------------  0 - Address increment select
 114         |
 115         |                               00 - Demand mode
 116         \------------------------------ 01 - Single mode
 117                                         10 - Block mode
 118                                         11 - Cascade mode
 119 */
 120 typedef struct _DMA_MODE {
 121   UCHAR Channel : 2;
 122   UCHAR TransferType : 2;
 123   UCHAR AutoInitialize : 1;
 124   UCHAR AddressDecrement : 1;
 125   UCHAR RequestMode : 2;
 126 } DMA_MODE, *PDMA_MODE;
 127
 128
 129 /* DMA Extended Mode Register Structure
 130
 131    MSB                             LSB
 132       x   x   x   x     x   x   x   x
 133       -   -   -----     -----   -----
 134       |   |     |         |       |     00 - Channel 0 select
 135       |   |     |         |       \---- 01 - Channel 1 select
 136       |   |     |         |             10 - Channel 2 select
 137       |   |     |         |             11 - Channel 3 select
 138       |   |     |         |
 139       |   |     |         |             00 - 8-bit I/O, by bytes
 140       |   |     |         \------------ 01 - 16-bit I/O, by words, address shifted
 141       |   |     |                       10 - 32-bit I/O, by bytes
 142       |   |     |                       11 - 16-bit I/O, by bytes
 143       |   |     |
 144       |   |     \---------------------- 00 - Compatible
 145       |   |                             01 - Type A
 146       |   |                             10 - Type B
 147       |   |                             11 - Burst
 148       |   |
 149       |   \---------------------------- 0 - Terminal Count is Output
 150       |
 151       \---------------------------------0 - Disable Stop Register
 152                                         1 - Enable Stop Register
 153 */
 154 typedef struct _DMA_EXTENDED_MODE {
 155     UCHAR ChannelNumber : 2;
 156     UCHAR TransferSize : 2;
 157     UCHAR TimingMode : 2;
 158     UCHAR TerminalCountIsOutput : 1;
 159     UCHAR EnableStopRegister : 1;
 160 }DMA_EXTENDED_MODE, *PDMA_EXTENDED_MODE;
 161
 162 /* DMA Extended Mode Register Transfer Sizes */
 163 #define B_8BITS 0
 164 #define W_16BITS 1
 165 #define B_32BITS 2
 166 #define B_16BITS 3
 167
 168 /* DMA Extended Mode Register Timing */
 169 #define COMPATIBLE_TIMING 0
 170 #define TYPE_A_TIMING 1
 171 #define TYPE_B_TIMING 2
 172 #define BURST_TIMING 3
 173
 174 /* Channel Stop Registers for each Channel */
 175 typedef struct _DMA_CHANNEL_STOP {
 176   UCHAR ChannelLow;
 177   UCHAR ChannelMid;
 178   UCHAR ChannelHigh;
 179   UCHAR Reserved;
 180 } DMA_CHANNEL_STOP, *PDMA_CHANNEL_STOP;
 181
 182 /* Transfer Types */
 183 #define VERIFY_TRANSFER 0x00
 184 #define READ_TRANSFER 0x01
 185 #define WRITE_TRANSFER 0x02
 186
 187 /* Request Modes */
 188 #define DEMAND_REQUEST_MODE 0x00
 189 #define SINGLE_REQUEST_MODE 0x01
 190 #define BLOCK_REQUEST_MODE 0x02
 191 #define CASCADE_REQUEST_MODE 0x03
 192
 193 #define DMA_SETMASK 4
 194 #define DMA_CLEARMASK 0
 195 #define DMA_READ 4
 196 #define DMA_WRITE 8
 197 #define DMA_SINGLE_TRANSFER 0x40
 198 #define DMA_AUTO_INIT 0x10
 199
 200 typedef struct _DMA1_ADDRESS_COUNT {
 201    UCHAR DmaBaseAddress;
 202    UCHAR DmaBaseCount;
 203 } DMA1_ADDRESS_COUNT, *PDMA1_ADDRESS_COUNT;
 204
 205 typedef struct _DMA2_ADDRESS_COUNT {
 206    UCHAR DmaBaseAddress;
 207    UCHAR Reserved1;
 208    UCHAR DmaBaseCount;
 209    UCHAR Reserved2;
 210 } DMA2_ADDRESS_COUNT, *PDMA2_ADDRESS_COUNT;
 211
 212 typedef struct _DMA1_CONTROL {
 213    DMA1_ADDRESS_COUNT DmaAddressCount[4];
 214    UCHAR DmaStatus;
 215    UCHAR DmaRequest;
 216    UCHAR SingleMask;
 217    UCHAR Mode;
 218    UCHAR ClearBytePointer;
 219    UCHAR MasterClear;
 220    UCHAR ClearMask;
 221    UCHAR AllMask;
 222 } DMA1_CONTROL, *PDMA1_CONTROL;
 223
 224 typedef struct _DMA2_CONTROL {
 225    DMA2_ADDRESS_COUNT DmaAddressCount[4];
 226    UCHAR DmaStatus;
 227    UCHAR Reserved1;
 228    UCHAR DmaRequest;
 229    UCHAR Reserved2;
 230    UCHAR SingleMask;
 231    UCHAR Reserved3;
 232    UCHAR Mode;
 233    UCHAR Reserved4;
 234    UCHAR ClearBytePointer;
 235    UCHAR Reserved5;
 236    UCHAR MasterClear;
 237    UCHAR Reserved6;
 238    UCHAR ClearMask;
 239    UCHAR Reserved7;
 240    UCHAR AllMask;
 241    UCHAR Reserved8;
 242 } DMA2_CONTROL, *PDMA2_CONTROL;
 243
 244 /* This Structure Defines the I/O Map of the 82537 Controller
 245    I've only defined the registers which are likely to be useful to us */
 246 typedef struct _EISA_CONTROL {
 247    /* DMA Controller 1 */
 248    DMA1_CONTROL DmaController1;         /* 00h-0Fh */
 249    UCHAR Reserved1[16];                 /* 0Fh-1Fh */
 250
 251    /* Interrupt Controller 1 (PIC) */
 252    UCHAR Pic1Operation;                 /* 20h     */
 253    UCHAR Pic1Interrupt;                 /* 21h     */
 254    UCHAR Reserved2[30];                 /* 22h-3Fh */
 255
 256    /* Timer */
 257    UCHAR TimerCounter;                  /* 40h     */
 258    UCHAR TimerMemoryRefresh;            /* 41h     */
 259    UCHAR Speaker;                       /* 42h     */
 260    UCHAR TimerOperation;                /* 43h     */
 261    UCHAR TimerMisc;                     /* 44h     */
 262    UCHAR Reserved3[2];                  /* 45-46h  */
 263    UCHAR TimerCounterControl;           /* 47h     */
 264    UCHAR TimerFailSafeCounter;          /* 48h     */
 265    UCHAR Reserved4;                     /* 49h     */
 266    UCHAR TimerCounter2;                 /* 4Ah     */
 267    UCHAR TimerOperation2;               /* 4Bh     */
 268    UCHAR Reserved5[20];                 /* 4Ch-5Fh */
 269
 270    /* NMI / Keyboard / RTC */
 271    UCHAR Keyboard;                      /* 60h     */
 272    UCHAR NmiStatus;                     /* 61h     */
 273    UCHAR Reserved6[14];                 /* 62h-6Fh */
 274    UCHAR NmiEnable;                     /* 70h     */
 275    UCHAR Reserved7[15];                 /* 71h-7Fh */
 276
 277    /* DMA Page Registers Controller 1 */
 278    DMA_PAGE DmaController1Pages;        /* 80h-8Fh */
 279    UCHAR Reserved8[16];                 /* 90h-9Fh */
 280
 281     /* Interrupt Controller 2 (PIC) */
 282    UCHAR Pic2Operation;                 /* 0A0h      */
 283    UCHAR Pic2Interrupt;                 /* 0A1h      */
 284    UCHAR Reserved9[30];                 /* 0A2h-0BFh */
 285
 286    /* DMA Controller 2 */
 287    DMA1_CONTROL DmaController2;         /* 0C0h-0CFh */
 288
 289    /* System Reserved Ports */
 290    UCHAR SystemReserved[816];           /* 0D0h-3FFh */
 291
 292    /* Extended DMA Registers, Controller 1 */
 293    UCHAR DmaHighByteCount1[8];          /* 400h-407h */
 294    UCHAR Reserved10[2];                 /* 408h-409h */
 295    UCHAR DmaChainMode1;                 /* 40Ah      */
 296    UCHAR DmaExtendedMode1;              /* 40Bh      */
 297    UCHAR DmaBufferControl;              /* 40Ch      */
 298    UCHAR Reserved11[84];                /* 40Dh-460h */
 299    UCHAR ExtendedNmiControl;            /* 461h      */
 300    UCHAR NmiCommand;                    /* 462h      */
 301    UCHAR Reserved12;                    /* 463h      */
 302    UCHAR BusMaster;                     /* 464h      */
 303    UCHAR Reserved13[27];                /* 465h-47Fh */
 304
 305    /* DMA Page Registers Controller 2 */
 306    DMA_PAGE DmaController2Pages;        /* 480h-48Fh */
 307    UCHAR Reserved14[48];                /* 490h-4BFh */
 308
 309    /* Extended DMA Registers, Controller 2 */
 310    UCHAR DmaHighByteCount2[16];         /* 4C0h-4CFh */
 311
 312    /* Edge/Level Control Registers */
 313    UCHAR Pic1EdgeLevel;                 /* 4D0h      */
 314    UCHAR Pic2EdgeLevel;                 /* 4D1h      */
 315    UCHAR Reserved15[2];                 /* 4D2h-4D3h */
 316
 317    /* Extended DMA Registers, Controller 2 */
 318    UCHAR DmaChainMode2;                 /* 4D4h      */
 319    UCHAR Reserved16;                    /* 4D5h      */
 320    UCHAR DmaExtendedMode2;              /* 4D6h      */
 321    UCHAR Reserved17[9];                 /* 4D7h-4DFh */
 322
 323    /* DMA Stop Registers */
 324    DMA_CHANNEL_STOP DmaChannelStop[8];  /* 4E0h-4FFh */
 325 } EISA_CONTROL, *PEISA_CONTROL;
 326
 327 extern ULONG HalpEisaDma;
 328 extern PADAPTER_OBJECT MasterAdapter;
 329
 330 EXPORTED ULONG HalpEisaDma;
 331 EXPORTED PADAPTER_OBJECT MasterAdapter;
 332
 333 /*
 334  * ADAPTER_OBJECT - Track a busmaster DMA adapter and its associated resources
 335  *
 336  * NOTES:
 337  *     - I've updated this to the Windows Object Defintion.
 338  */
 339 struct _ADAPTER_OBJECT {
 340   DMA_ADAPTER DmaHeader;
 341   struct _ADAPTER_OBJECT *MasterAdapter;
 342   ULONG MapRegistersPerChannel;
 343   PVOID AdapterBaseVa;
 344   PVOID MapRegisterBase;
 345   ULONG NumberOfMapRegisters;
 346   ULONG CommittedMapRegisters;
 347   PWAIT_CONTEXT_BLOCK CurrentWcb;
 348   KDEVICE_QUEUE ChannelWaitQueue;
 349   PKDEVICE_QUEUE RegisterWaitQueue;
 350   LIST_ENTRY AdapterQueue;
 351   ULONG SpinLock;
 352   PRTL_BITMAP MapRegisters;
 353   PUCHAR PagePort;
 354   UCHAR ChannelNumber;
 355   UCHAR AdapterNumber;
 356   USHORT DmaPortAddress;
 357   union {
 358     DMA_MODE AdapterMode;
 359     UCHAR AdapterModeByte;
 360   };
 361   BOOLEAN NeedsMapRegisters;
 362   BOOLEAN MasterDevice;
 363   UCHAR Width16Bits;
 364   UCHAR ScatterGather;
 365   UCHAR IgnoreCount;
 366   UCHAR Dma32BitAddresses;
 367   UCHAR Dma64BitAddresses;
 368   BOOLEAN LegacyAdapter;
 369   LIST_ENTRY AdapterList;
 370 };
 371
 372 /*
 373 struct _ADAPTER_OBJECT {
 374   INTERFACE_TYPE InterfaceType;
 375   BOOLEAN Master;
 376   int Channel;
 377   PVOID PagePort;
 378   PVOID CountPort;
 379   PVOID OffsetPort;
 380   KSPIN_LOCK SpinLock;
 381   PVOID Buffer;
 382   BOOLEAN Inuse;
 383   ULONG AvailableMapRegisters;
 384   PVOID MapRegisterBase;
 385   ULONG AllocatedMapRegisters;
 386   PWAIT_CONTEXT_BLOCK WaitContextBlock;
 387   KDEVICE_QUEUE DeviceQueue;
 388   BOOLEAN ScatterGather;
 389   BOOLEAN DemandMode;
 390   BOOLEAN AutoInitialize;
 391 };
 392 */
 393
 394 /* sysinfo.c */
 395 NTSTATUS STDCALL
 396 HalpQuerySystemInformation(IN HAL_QUERY_INFORMATION_CLASS InformationClass,
 397                            IN ULONG BufferSize,
 398                            IN OUT PVOID Buffer,
 399                            OUT PULONG ReturnedLength);
 400
 401
 402 /* Non-standard functions */
 403 VOID STDCALL
 404 HalReleaseDisplayOwnership();
 405
 406 BOOLEAN STDCALL
 407 HalQueryDisplayOwnership();
 408
 409 #if defined(__GNUC__)
 410 #define Ki386SaveFlags(x)           __asm__ __volatile__("pushfl ; popl %0":"=g" (x): /* no input */)
 411 #define Ki386RestoreFlags(x)        __asm__ __volatile__("pushl %0 ; popfl": /* no output */ :"g" (x):"memory")
 412 #define Ki386DisableInterrupts()    __asm__ __volatile__("cli\n\t")
 413 #define Ki386EnableInterrupts()     __asm__ __volatile__("sti\n\t")
 414 #define Ki386HaltProcessor()        __asm__ __volatile__("hlt\n\t")
 415 #define Ki386RdTSC(x)               __asm__ __volatile__("rdtsc\n\t" : "=A" (x.u.LowPart), "=d" (x.u.HighPart));
 416 #define Ki386Rdmsr(msr,val1,val2)   __asm__ __volatile__("rdmsr" : "=a" (val1), "=d" (val2) : "c" (msr))
 417 #define Ki386Wrmsr(msr,val1,val2)   __asm__ __volatile__("wrmsr" : /* no outputs */ : "c" (msr), "a" (val1), "d" (val2))
 418
 419 static inline BYTE Ki386ReadFsByte(ULONG offset)
 420 {
 421    BYTE b;
 422    __asm__ __volatile__("movb %%fs:(%1),%0":"=q" (b):"r" (offset));
 423    return b;
 424 }
 425
 426 static inline VOID Ki386WriteFsByte(ULONG offset, BYTE value)
 427 {
 428    __asm__ __volatile__("movb %0,%%fs:(%1)"::"r" (value), "r" (offset));
 429 }
 430
 431 #elif defined(_MSC_VER)
 432 #define Ki386SaveFlags(x)           __asm pushfd  __asm pop x;
 433 #define Ki386RestoreFlags(x)        __asm push x  __asm popfd;
 434 #define Ki386DisableInterrupts()    __asm cli
 435 #define Ki386EnableInterrupts()     __asm sti
 436 #define Ki386HaltProcessor()        __asm hlt
 437 #else
 438 #error Unknown compiler for inline assembler
 439 #endif
 440
 441 typedef struct tagHALP_HOOKS
 442 {
 443   void (*InitPciBus)(ULONG BusNumber, PBUS_HANDLER BusHandler);
 444 } HALP_HOOKS, *PHALP_HOOKS;
 445
 446 extern HALP_HOOKS HalpHooks;
 447
 448 #endif /* __INTERNAL_HAL_HAL_H */