5 #ifndef __INTERNAL_HAL_HAL_H
6 #define __INTERNAL_HAL_HAL_H
8 #define HAL_APC_REQUEST 0
9 #define HAL_DPC_REQUEST 1
12 VOID FASTCALL
HalInitializeDisplay (PLOADER_PARAMETER_BLOCK LoaderBlock
);
13 VOID FASTCALL
HalClearDisplay (UCHAR CharAttribute
);
16 PADAPTER_OBJECT STDCALL
HalpAllocateAdapterEx(ULONG NumberOfMapRegisters
,BOOLEAN IsMaster
, BOOLEAN Dma32BitAddresses
);
19 VOID
HalpInitBusHandlers (VOID
);
22 VOID
HalpInitPICs(VOID
);
25 VOID
HalpCalibrateStallExecution(VOID
);
28 VOID
HalpInitPciBus (VOID
);
31 VOID
HalpStartEnumerator (VOID
);
34 VOID
HalpInitDma (VOID
);
37 PVOID
HalpMapPhysMemory(ULONG PhysAddr
, ULONG Size
);
39 /* Non-generic initialization */
40 VOID
HalpInitPhase0 (VOID
);
42 /* DMA Page Register Structure
44 081 DMA Page Register (channel 2)
45 082 DMA Page Register (channel 3)
46 083 DMA Page Register (channel 1)
50 087 DMA Page Register (channel 0)
52 089 PS/2-DMA Page Register (channel 6)
53 08A PS/2-DMA Page Register (channel 7)
54 08B PS/2-DMA Page Register (channel 5)
58 08F PS/2-DMA Page Register (channel 4)
60 typedef struct _DMA_PAGE
{
73 } DMA_PAGE
, *PDMA_PAGE
;
75 /* DMA Channel Mask Register Structure
79 ------------------- - -----
80 | | | 00 - Select channel 0 mask bit
81 | | \---- 01 - Select channel 1 mask bit
82 | | 10 - Select channel 2 mask bit
83 | | 11 - Select channel 3 mask bit
85 | \---------- 0 - Clear mask bit
88 \----------------------- xx - Reserved
90 typedef struct _DMA_CHANNEL_MASK
{
94 } DMA_CHANNEL_MASK
, *PDMA_CHANNEL_MASK
;
96 /* DMA Mask Register Structure
100 \---/ - - ----- -----
101 | | | | | 00 - Channel 0 select
102 | | | | \---- 01 - Channel 1 select
103 | | | | 10 - Channel 2 select
104 | | | | 11 - Channel 3 select
106 | | | | 00 - Verify transfer
107 | | | \------------ 01 - Write transfer
108 | | | 10 - Read transfer
110 | | \-------------------- 0 - Autoinitialized
111 | | 1 - Non-autoinitialized
113 | \------------------------ 0 - Address increment select
116 \------------------------------ 01 - Single mode
120 typedef struct _DMA_MODE
{
122 UCHAR TransferType
: 2;
123 UCHAR AutoInitialize
: 1;
124 UCHAR AddressDecrement
: 1;
125 UCHAR RequestMode
: 2;
126 } DMA_MODE
, *PDMA_MODE
;
129 /* DMA Extended Mode Register Structure
133 - - ----- ----- -----
134 | | | | | 00 - Channel 0 select
135 | | | | \---- 01 - Channel 1 select
136 | | | | 10 - Channel 2 select
137 | | | | 11 - Channel 3 select
139 | | | | 00 - 8-bit I/O, by bytes
140 | | | \------------ 01 - 16-bit I/O, by words, address shifted
141 | | | 10 - 32-bit I/O, by bytes
142 | | | 11 - 16-bit I/O, by bytes
144 | | \---------------------- 00 - Compatible
149 | \---------------------------- 0 - Terminal Count is Output
151 \---------------------------------0 - Disable Stop Register
152 1 - Enable Stop Register
154 typedef struct _DMA_EXTENDED_MODE
{
155 UCHAR ChannelNumber
: 2;
156 UCHAR TransferSize
: 2;
157 UCHAR TimingMode
: 2;
158 UCHAR TerminalCountIsOutput
: 1;
159 UCHAR EnableStopRegister
: 1;
160 }DMA_EXTENDED_MODE
, *PDMA_EXTENDED_MODE
;
162 /* DMA Extended Mode Register Transfer Sizes */
168 /* DMA Extended Mode Register Timing */
169 #define COMPATIBLE_TIMING 0
170 #define TYPE_A_TIMING 1
171 #define TYPE_B_TIMING 2
172 #define BURST_TIMING 3
174 /* Channel Stop Registers for each Channel */
175 typedef struct _DMA_CHANNEL_STOP
{
180 } DMA_CHANNEL_STOP
, *PDMA_CHANNEL_STOP
;
183 #define VERIFY_TRANSFER 0x00
184 #define READ_TRANSFER 0x01
185 #define WRITE_TRANSFER 0x02
188 #define DEMAND_REQUEST_MODE 0x00
189 #define SINGLE_REQUEST_MODE 0x01
190 #define BLOCK_REQUEST_MODE 0x02
191 #define CASCADE_REQUEST_MODE 0x03
193 #define DMA_SETMASK 4
194 #define DMA_CLEARMASK 0
197 #define DMA_SINGLE_TRANSFER 0x40
198 #define DMA_AUTO_INIT 0x10
200 typedef struct _DMA1_ADDRESS_COUNT
{
201 UCHAR DmaBaseAddress
;
203 } DMA1_ADDRESS_COUNT
, *PDMA1_ADDRESS_COUNT
;
205 typedef struct _DMA2_ADDRESS_COUNT
{
206 UCHAR DmaBaseAddress
;
210 } DMA2_ADDRESS_COUNT
, *PDMA2_ADDRESS_COUNT
;
212 typedef struct _DMA1_CONTROL
{
213 DMA1_ADDRESS_COUNT DmaAddressCount
[4];
218 UCHAR ClearBytePointer
;
222 } DMA1_CONTROL
, *PDMA1_CONTROL
;
224 typedef struct _DMA2_CONTROL
{
225 DMA2_ADDRESS_COUNT DmaAddressCount
[4];
234 UCHAR ClearBytePointer
;
242 } DMA2_CONTROL
, *PDMA2_CONTROL
;
244 /* This Structure Defines the I/O Map of the 82537 Controller
245 I've only defined the registers which are likely to be useful to us */
246 typedef struct _EISA_CONTROL
{
247 /* DMA Controller 1 */
248 DMA1_CONTROL DmaController1
; /* 00h-0Fh */
249 UCHAR Reserved1
[16]; /* 0Fh-1Fh */
251 /* Interrupt Controller 1 (PIC) */
252 UCHAR Pic1Operation
; /* 20h */
253 UCHAR Pic1Interrupt
; /* 21h */
254 UCHAR Reserved2
[30]; /* 22h-3Fh */
257 UCHAR TimerCounter
; /* 40h */
258 UCHAR TimerMemoryRefresh
; /* 41h */
259 UCHAR Speaker
; /* 42h */
260 UCHAR TimerOperation
; /* 43h */
261 UCHAR TimerMisc
; /* 44h */
262 UCHAR Reserved3
[2]; /* 45-46h */
263 UCHAR TimerCounterControl
; /* 47h */
264 UCHAR TimerFailSafeCounter
; /* 48h */
265 UCHAR Reserved4
; /* 49h */
266 UCHAR TimerCounter2
; /* 4Ah */
267 UCHAR TimerOperation2
; /* 4Bh */
268 UCHAR Reserved5
[20]; /* 4Ch-5Fh */
270 /* NMI / Keyboard / RTC */
271 UCHAR Keyboard
; /* 60h */
272 UCHAR NmiStatus
; /* 61h */
273 UCHAR Reserved6
[14]; /* 62h-6Fh */
274 UCHAR NmiEnable
; /* 70h */
275 UCHAR Reserved7
[15]; /* 71h-7Fh */
277 /* DMA Page Registers Controller 1 */
278 DMA_PAGE DmaController1Pages
; /* 80h-8Fh */
279 UCHAR Reserved8
[16]; /* 90h-9Fh */
281 /* Interrupt Controller 2 (PIC) */
282 UCHAR Pic2Operation
; /* 0A0h */
283 UCHAR Pic2Interrupt
; /* 0A1h */
284 UCHAR Reserved9
[30]; /* 0A2h-0BFh */
286 /* DMA Controller 2 */
287 DMA1_CONTROL DmaController2
; /* 0C0h-0DFh */
289 /* System Reserved Ports */
290 UCHAR SystemReserved
[800]; /* 0E0h-3FFh */
292 /* Extended DMA Registers, Controller 1 */
293 UCHAR DmaHighByteCount1
[8]; /* 400h-407h */
294 UCHAR Reserved10
[2]; /* 408h-409h */
295 UCHAR DmaChainMode1
; /* 40Ah */
296 UCHAR DmaExtendedMode1
; /* 40Bh */
297 UCHAR DmaBufferControl
; /* 40Ch */
298 UCHAR Reserved11
[84]; /* 40Dh-460h */
299 UCHAR ExtendedNmiControl
; /* 461h */
300 UCHAR NmiCommand
; /* 462h */
301 UCHAR Reserved12
; /* 463h */
302 UCHAR BusMaster
; /* 464h */
303 UCHAR Reserved13
[27]; /* 465h-47Fh */
305 /* DMA Page Registers Controller 2 */
306 DMA_PAGE DmaController2Pages
; /* 480h-48Fh */
307 UCHAR Reserved14
[48]; /* 490h-4BFh */
309 /* Extended DMA Registers, Controller 2 */
310 UCHAR DmaHighByteCount2
[16]; /* 4C0h-4CFh */
312 /* Edge/Level Control Registers */
313 UCHAR Pic1EdgeLevel
; /* 4D0h */
314 UCHAR Pic2EdgeLevel
; /* 4D1h */
315 UCHAR Reserved15
[2]; /* 4D2h-4D3h */
317 /* Extended DMA Registers, Controller 2 */
318 UCHAR DmaChainMode2
; /* 4D4h */
319 UCHAR Reserved16
; /* 4D5h */
320 UCHAR DmaExtendedMode2
; /* 4D6h */
321 UCHAR Reserved17
[9]; /* 4D7h-4DFh */
323 /* DMA Stop Registers */
324 DMA_CHANNEL_STOP DmaChannelStop
[8]; /* 4E0h-4FFh */
325 } EISA_CONTROL
, *PEISA_CONTROL
;
327 extern ULONG HalpEisaDma
;
328 extern PADAPTER_OBJECT MasterAdapter
;
330 EXPORTED ULONG HalpEisaDma
;
331 EXPORTED PADAPTER_OBJECT MasterAdapter
;
334 * ADAPTER_OBJECT - Track a busmaster DMA adapter and its associated resources
337 * - I've updated this to the Windows Object Defintion.
339 struct _ADAPTER_OBJECT
{
340 DMA_ADAPTER DmaHeader
;
341 struct _ADAPTER_OBJECT
*MasterAdapter
;
342 ULONG MapRegistersPerChannel
;
344 PVOID MapRegisterBase
;
345 ULONG NumberOfMapRegisters
;
346 ULONG CommittedMapRegisters
;
347 PWAIT_CONTEXT_BLOCK CurrentWcb
;
348 KDEVICE_QUEUE ChannelWaitQueue
;
349 PKDEVICE_QUEUE RegisterWaitQueue
;
350 LIST_ENTRY AdapterQueue
;
352 PRTL_BITMAP MapRegisters
;
356 USHORT DmaPortAddress
;
358 BOOLEAN NeedsMapRegisters
;
359 BOOLEAN MasterDevice
;
363 UCHAR Dma32BitAddresses
;
364 UCHAR Dma64BitAddresses
;
365 BOOLEAN LegacyAdapter
;
366 LIST_ENTRY AdapterList
;
370 struct _ADAPTER_OBJECT {
371 INTERFACE_TYPE InterfaceType;
380 ULONG AvailableMapRegisters;
381 PVOID MapRegisterBase;
382 ULONG AllocatedMapRegisters;
383 PWAIT_CONTEXT_BLOCK WaitContextBlock;
384 KDEVICE_QUEUE DeviceQueue;
385 BOOLEAN ScatterGather;
387 BOOLEAN AutoInitialize;
393 HalpQuerySystemInformation(IN HAL_QUERY_INFORMATION_CLASS InformationClass
,
396 OUT PULONG ReturnedLength
);
399 /* Non-standard functions */
401 HalReleaseDisplayOwnership();
404 HalQueryDisplayOwnership();
406 #if defined(__GNUC__)
407 #define Ki386SaveFlags(x) __asm__ __volatile__("pushfl ; popl %0":"=g" (x): /* no input */)
408 #define Ki386RestoreFlags(x) __asm__ __volatile__("pushl %0 ; popfl": /* no output */ :"g" (x):"memory")
409 #define Ki386DisableInterrupts() __asm__ __volatile__("cli\n\t")
410 #define Ki386EnableInterrupts() __asm__ __volatile__("sti\n\t")
411 #define Ki386HaltProcessor() __asm__ __volatile__("hlt\n\t")
412 #define Ki386RdTSC(x) __asm__ __volatile__("rdtsc\n\t" : "=A" (x.u.LowPart), "=d" (x.u.HighPart));
414 static inline BYTE
Ki386ReadFsByte(ULONG offset
)
417 __asm__
__volatile__("movb %%fs:(%1),%0":"=g" (b
):"0" (offset
));
421 static inline VOID
Ki386WriteFsByte(ULONG offset
, BYTE value
)
423 __asm__
__volatile__("movb %0,%%fs:(%1)"::"r" (value
), "r" (offset
));
426 #elif defined(_MSC_VER)
427 #define Ki386SaveFlags(x) __asm pushfd __asm pop x;
428 #define Ki386RestoreFlags(x) __asm push x __asm popfd;
429 #define Ki386DisableInterrupts() __asm cli
430 #define Ki386EnableInterrupts() __asm sti
431 #define Ki386HaltProcessor() __asm hlt
433 #error Unknown compiler for inline assembler
436 typedef struct tagHALP_HOOKS
438 void (*InitPciBus
)(ULONG BusNumber
, PBUS_HANDLER BusHandler
);
439 } HALP_HOOKS
, *PHALP_HOOKS
;
441 extern HALP_HOOKS HalpHooks
;
443 #endif /* __INTERNAL_HAL_HAL_H */