5 * DMA Page Register Structure
7 * 081 DMA Page Register (channel 2)
8 * 082 DMA Page Register (channel 3)
9 * 083 DMA Page Register (channel 1)
13 * 087 DMA Page Register (channel 0)
15 * 089 PS/2-DMA Page Register (channel 6)
16 * 08A PS/2-DMA Page Register (channel 7)
17 * 08B PS/2-DMA Page Register (channel 5)
18 * 08C PS/2-DMA RESERVED
19 * 08D PS/2-DMA RESERVED
20 * 08E PS/2-DMA RESERVED
21 * 08F PS/2-DMA Page Register (channel 4)
24 typedef struct _DMA_PAGE
38 } DMA_PAGE
, *PDMA_PAGE
;
41 * DMA Channel Mask Register Structure
45 * ------------------- - -----
46 * | | | 00 - Select channel 0 mask bit
47 * | | \---- 01 - Select channel 1 mask bit
48 * | | 10 - Select channel 2 mask bit
49 * | | 11 - Select channel 3 mask bit
51 * | \---------- 0 - Clear mask bit
54 * \----------------------- xx - Reserved
57 typedef struct _DMA_CHANNEL_MASK
62 } DMA_CHANNEL_MASK
, *PDMA_CHANNEL_MASK
;
65 * DMA Mask Register Structure
69 * \---/ - - ----- -----
70 * | | | | | 00 - Channel 0 select
71 * | | | | \---- 01 - Channel 1 select
72 * | | | | 10 - Channel 2 select
73 * | | | | 11 - Channel 3 select
75 * | | | | 00 - Verify transfer
76 * | | | \------------ 01 - Write transfer
77 * | | | 10 - Read transfer
79 * | | \-------------------- 0 - Autoinitialized
80 * | | 1 - Non-autoinitialized
82 * | \------------------------ 0 - Address increment select
85 * \------------------------------ 01 - Single mode
90 typedef union _DMA_MODE
95 UCHAR TransferType
: 2;
96 UCHAR AutoInitialize
: 1;
97 UCHAR AddressDecrement
: 1;
101 } DMA_MODE
, *PDMA_MODE
;
104 * DMA Extended Mode Register Structure
108 * - - ----- ----- -----
109 * | | | | | 00 - Channel 0 select
110 * | | | | \---- 01 - Channel 1 select
111 * | | | | 10 - Channel 2 select
112 * | | | | 11 - Channel 3 select
114 * | | | | 00 - 8-bit I/O, by bytes
115 * | | | \------------ 01 - 16-bit I/O, by words, address shifted
116 * | | | 10 - 32-bit I/O, by bytes
117 * | | | 11 - 16-bit I/O, by bytes
119 * | | \---------------------- 00 - Compatible
124 * | \---------------------------- 0 - Terminal Count is Output
126 * \---------------------------------0 - Disable Stop Register
127 * 1 - Enable Stop Register
130 typedef union _DMA_EXTENDED_MODE
134 UCHAR ChannelNumber
: 2;
135 UCHAR TransferSize
: 2;
137 UCHAR TerminalCountIsOutput
: 1;
138 UCHAR EnableStopRegister
: 1;
141 } DMA_EXTENDED_MODE
, *PDMA_EXTENDED_MODE
;
143 /* DMA Extended Mode Register Transfer Sizes */
149 /* DMA Extended Mode Register Timing */
150 #define COMPATIBLE_TIMING 0
151 #define TYPE_A_TIMING 1
152 #define TYPE_B_TIMING 2
153 #define BURST_TIMING 3
155 /* Channel Stop Registers for each Channel */
156 typedef struct _DMA_CHANNEL_STOP
162 } DMA_CHANNEL_STOP
, *PDMA_CHANNEL_STOP
;
165 #define VERIFY_TRANSFER 0x00
166 #define READ_TRANSFER 0x01
167 #define WRITE_TRANSFER 0x02
170 #define DEMAND_REQUEST_MODE 0x00
171 #define SINGLE_REQUEST_MODE 0x01
172 #define BLOCK_REQUEST_MODE 0x02
173 #define CASCADE_REQUEST_MODE 0x03
175 #define DMA_SETMASK 4
176 #define DMA_CLEARMASK 0
179 #define DMA_SINGLE_TRANSFER 0x40
180 #define DMA_AUTO_INIT 0x10
182 typedef struct _DMA1_ADDRESS_COUNT
184 UCHAR DmaBaseAddress
;
186 } DMA1_ADDRESS_COUNT
, *PDMA1_ADDRESS_COUNT
;
188 typedef struct _DMA2_ADDRESS_COUNT
190 UCHAR DmaBaseAddress
;
194 } DMA2_ADDRESS_COUNT
, *PDMA2_ADDRESS_COUNT
;
196 typedef struct _DMA1_CONTROL
198 DMA1_ADDRESS_COUNT DmaAddressCount
[4];
203 UCHAR ClearBytePointer
;
207 } DMA1_CONTROL
, *PDMA1_CONTROL
;
209 typedef struct _DMA2_CONTROL
211 DMA2_ADDRESS_COUNT DmaAddressCount
[4];
220 UCHAR ClearBytePointer
;
228 } DMA2_CONTROL
, *PDMA2_CONTROL
;
230 /* This structure defines the I/O Map of the 82537 controller. */
231 typedef struct _EISA_CONTROL
233 /* DMA Controller 1 */
234 DMA1_CONTROL DmaController1
; /* 00h-0Fh */
235 UCHAR Reserved1
[16]; /* 0Fh-1Fh */
237 /* Interrupt Controller 1 (PIC) */
238 UCHAR Pic1Operation
; /* 20h */
239 UCHAR Pic1Interrupt
; /* 21h */
240 UCHAR Reserved2
[30]; /* 22h-3Fh */
243 UCHAR TimerCounter
; /* 40h */
244 UCHAR TimerMemoryRefresh
; /* 41h */
245 UCHAR Speaker
; /* 42h */
246 UCHAR TimerOperation
; /* 43h */
247 UCHAR TimerMisc
; /* 44h */
248 UCHAR Reserved3
[2]; /* 45-46h */
249 UCHAR TimerCounterControl
; /* 47h */
250 UCHAR TimerFailSafeCounter
; /* 48h */
251 UCHAR Reserved4
; /* 49h */
252 UCHAR TimerCounter2
; /* 4Ah */
253 UCHAR TimerOperation2
; /* 4Bh */
254 UCHAR Reserved5
[20]; /* 4Ch-5Fh */
256 /* NMI / Keyboard / RTC */
257 UCHAR Keyboard
; /* 60h */
258 UCHAR NmiStatus
; /* 61h */
259 UCHAR Reserved6
[14]; /* 62h-6Fh */
260 UCHAR NmiEnable
; /* 70h */
261 UCHAR Reserved7
[15]; /* 71h-7Fh */
263 /* DMA Page Registers Controller 1 */
264 DMA_PAGE DmaController1Pages
; /* 80h-8Fh */
265 UCHAR Reserved8
[16]; /* 90h-9Fh */
267 /* Interrupt Controller 2 (PIC) */
268 UCHAR Pic2Operation
; /* 0A0h */
269 UCHAR Pic2Interrupt
; /* 0A1h */
270 UCHAR Reserved9
[30]; /* 0A2h-0BFh */
272 /* DMA Controller 2 */
273 DMA1_CONTROL DmaController2
; /* 0C0h-0CFh */
275 /* System Reserved Ports */
276 UCHAR SystemReserved
[816]; /* 0D0h-3FFh */
278 /* Extended DMA Registers, Controller 1 */
279 UCHAR DmaHighByteCount1
[8]; /* 400h-407h */
280 UCHAR Reserved10
[2]; /* 408h-409h */
281 UCHAR DmaChainMode1
; /* 40Ah */
282 UCHAR DmaExtendedMode1
; /* 40Bh */
283 UCHAR DmaBufferControl
; /* 40Ch */
284 UCHAR Reserved11
[84]; /* 40Dh-460h */
285 UCHAR ExtendedNmiControl
; /* 461h */
286 UCHAR NmiCommand
; /* 462h */
287 UCHAR Reserved12
; /* 463h */
288 UCHAR BusMaster
; /* 464h */
289 UCHAR Reserved13
[27]; /* 465h-47Fh */
291 /* DMA Page Registers Controller 2 */
292 DMA_PAGE DmaController2Pages
; /* 480h-48Fh */
293 UCHAR Reserved14
[48]; /* 490h-4BFh */
295 /* Extended DMA Registers, Controller 2 */
296 UCHAR DmaHighByteCount2
[16]; /* 4C0h-4CFh */
298 /* Edge/Level Control Registers */
299 UCHAR Pic1EdgeLevel
; /* 4D0h */
300 UCHAR Pic2EdgeLevel
; /* 4D1h */
301 UCHAR Reserved15
[2]; /* 4D2h-4D3h */
303 /* Extended DMA Registers, Controller 2 */
304 UCHAR DmaChainMode2
; /* 4D4h */
305 UCHAR Reserved16
; /* 4D5h */
306 UCHAR DmaExtendedMode2
; /* 4D6h */
307 UCHAR Reserved17
[9]; /* 4D7h-4DFh */
309 /* DMA Stop Registers */
310 DMA_CHANNEL_STOP DmaChannelStop
[8]; /* 4E0h-4FFh */
311 } EISA_CONTROL
, *PEISA_CONTROL
;
313 typedef struct _MAP_REGISTER_ENTRY
315 PVOID VirtualAddress
;
316 PHYSICAL_ADDRESS PhysicalAddress
;
318 } MAP_REGISTER_ENTRY
, *PMAP_REGISTER_ENTRY
;
320 struct _ADAPTER_OBJECT
{
322 * New style DMA object definition. The fact that it is at the beginning
323 * of the ADAPTER_OBJECT structure allows us to easily implement the
324 * fallback implementation of IoGetDmaAdapter.
326 DMA_ADAPTER DmaHeader
;
329 * For normal adapter objects pointer to master adapter that takes care
330 * of channel allocation. For master adapter set to NULL.
332 struct _ADAPTER_OBJECT
*MasterAdapter
;
334 ULONG MapRegistersPerChannel
;
336 PMAP_REGISTER_ENTRY MapRegisterBase
;
338 ULONG NumberOfMapRegisters
;
339 ULONG CommittedMapRegisters
;
341 PWAIT_CONTEXT_BLOCK CurrentWcb
;
342 KDEVICE_QUEUE ChannelWaitQueue
;
343 PKDEVICE_QUEUE RegisterWaitQueue
;
344 LIST_ENTRY AdapterQueue
;
346 PRTL_BITMAP MapRegisters
;
350 USHORT DmaPortAddress
;
351 DMA_MODE AdapterMode
;
352 BOOLEAN NeedsMapRegisters
;
353 BOOLEAN MasterDevice
;
355 BOOLEAN ScatterGather
;
357 BOOLEAN Dma32BitAddresses
;
358 BOOLEAN Dma64BitAddresses
;
359 LIST_ENTRY AdapterList
;
362 typedef struct _GROW_WORK_ITEM
{
363 WORK_QUEUE_ITEM WorkQueueItem
;
364 PADAPTER_OBJECT AdapterObject
;
365 ULONG NumberOfMapRegisters
;
366 } GROW_WORK_ITEM
, *PGROW_WORK_ITEM
;
368 #define MAP_BASE_SW_SG 1
370 PADAPTER_OBJECT STDCALL
371 HalpDmaAllocateMasterAdapter(VOID
);
375 PADAPTER_OBJECT AdapterObject
);
378 HalpDmaGetDmaAlignment(
379 PADAPTER_OBJECT AdapterObject
);
382 IoAllocateAdapterChannel(
383 IN PADAPTER_OBJECT AdapterObject
,
384 IN PDEVICE_OBJECT DeviceObject
,
385 IN ULONG NumberOfMapRegisters
,
386 IN PDRIVER_CONTROL ExecutionRoutine
,
389 #endif /* HALDMA_H */