reactos/hal/halx86/include/halp.h

   1 /*
   2  *
   3  */
   4
   5 #pragma once
   6
   7 #if defined(__GNUC__) && !defined(_MINIHAL_)
   8 #define INIT_SECTION __attribute__((section ("INIT")))
   9 #else
  10 #define INIT_SECTION /* Done via alloc_text for MSC */
  11 #endif
  12
  13
  14 #ifdef _MSC_VER
  15 #define REGISTERCALL FASTCALL
  16 #else
  17 #define REGISTERCALL __attribute__((regparm(3)))
  18 #endif
  19
  20 #ifdef CONFIG_SMP
  21 #define HAL_BUILD_TYPE (DBG ? PRCB_BUILD_DEBUG : 0)
  22 #else
  23 #define HAL_BUILD_TYPE ((DBG ? PRCB_BUILD_DEBUG : 0) | PRCB_BUILD_UNIPROCESSOR)
  24 #endif
  25
  26 typedef struct _HAL_BIOS_FRAME
  27 {
  28     ULONG SegSs;
  29     ULONG Esp;
  30     ULONG EFlags;
  31     ULONG SegCs;
  32     ULONG Eip;
  33     PKTRAP_FRAME TrapFrame;
  34     ULONG CsLimit;
  35     ULONG CsBase;
  36     ULONG CsFlags;
  37     ULONG SsLimit;
  38     ULONG SsBase;
  39     ULONG SsFlags;
  40     ULONG Prefix;
  41 } HAL_BIOS_FRAME, *PHAL_BIOS_FRAME;
  42
  43 typedef
  44 VOID
  45 (*PHAL_SW_INTERRUPT_HANDLER)(
  46     VOID
  47 );
  48
  49 typedef
  50 VOID
  51 (FASTCALL *PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY)(
  52     IN PKTRAP_FRAME TrapFrame
  53 );
  54
  55 #define HAL_APC_REQUEST         0
  56 #define HAL_DPC_REQUEST         1
  57
  58 /* CMOS Registers and Ports */
  59 #define CMOS_CONTROL_PORT       (PUCHAR)0x70
  60 #define CMOS_DATA_PORT          (PUCHAR)0x71
  61 #define RTC_REGISTER_A          0x0A
  62 #define   RTC_REG_A_UIP         0x80
  63 #define RTC_REGISTER_B          0x0B
  64 #define   RTC_REG_B_PI          0x40
  65 #define RTC_REGISTER_C          0x0C
  66 #define   RTC_REG_C_IRQ         0x80
  67 #define RTC_REGISTER_D          0x0D
  68 #define RTC_REGISTER_CENTURY    0x32
  69
  70 /* Usage flags */
  71 #define IDT_REGISTERED          0x01
  72 #define IDT_LATCHED             0x02
  73 #define IDT_READ_ONLY           0x04
  74 #define IDT_INTERNAL            0x11
  75 #define IDT_DEVICE              0x21
  76
  77 /* Conversion functions */
  78 #define BCD_INT(bcd)            \
  79     (((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F))
  80 #define INT_BCD(int)            \
  81     (UCHAR)(((int / 10) << 4) + (int % 10))
  82
  83 //
  84 // BIOS Interrupts
  85 //
  86 #define VIDEO_SERVICES   0x10
  87
  88 //
  89 // Operations for INT 10h (in AH)
  90 //
  91 #define SET_VIDEO_MODE   0x00
  92
  93 //
  94 // Video Modes for INT10h AH=00 (in AL)
  95 //
  96 #define GRAPHICS_MODE_12 0x12           /* 80x30         8x16  640x480   16/256K */
  97
  98 //
  99 // Commonly stated as being 1.19318MHz
 100 //
 101 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 102 // P. 471
 103 //
 104 // However, the true value is closer to 1.19318181[...]81MHz since this is 1/3rd
 105 // of the NTSC color subcarrier frequency which runs at 3.57954545[...]45MHz.
 106 //
 107 // Note that Windows uses 1.193167MHz which seems to have no basis. However, if
 108 // one takes the NTSC color subcarrier frequency as being 3.579545 (trimming the
 109 // infinite series) and divides it by three, one obtains 1.19318167.
 110 //
 111 // It may be that the original NT HAL source code introduced a typo and turned
 112 // 119318167 into 1193167 by ommitting the "18". This is very plausible as the
 113 // number is quite long.
 114 //
 115 #define PIT_FREQUENCY 1193182
 116
 117 //
 118 // These ports are controlled by the i8254 Programmable Interrupt Timer (PIT)
 119 //
 120 #define TIMER_CHANNEL0_DATA_PORT 0x40
 121 #define TIMER_CHANNEL1_DATA_PORT 0x41
 122 #define TIMER_CHANNEL2_DATA_PORT 0x42
 123 #define TIMER_CONTROL_PORT       0x43
 124
 125 //
 126 // Mode 0 - Interrupt On Terminal Count
 127 // Mode 1 - Hardware Re-triggerable One-Shot
 128 // Mode 2 - Rate Generator
 129 // Mode 3 - Square Wave Generator
 130 // Mode 4 - Software Triggered Strobe
 131 // Mode 5 - Hardware Triggered Strobe
 132 //
 133 typedef enum _TIMER_OPERATING_MODES
 134 {
 135     PitOperatingMode0,
 136     PitOperatingMode1,
 137     PitOperatingMode2,
 138     PitOperatingMode3,
 139     PitOperatingMode4,
 140     PitOperatingMode5,
 141     PitOperatingMode2Reserved,
 142     PitOperatingMode5Reserved
 143 } TIMER_OPERATING_MODES;
 144
 145 typedef enum _TIMER_ACCESS_MODES
 146 {
 147     PitAccessModeCounterLatch,
 148     PitAccessModeLow,
 149     PitAccessModeHigh,
 150     PitAccessModeLowHigh
 151 } TIMER_ACCESS_MODES;
 152
 153 typedef enum _TIMER_CHANNELS
 154 {
 155     PitChannel0,
 156     PitChannel1,
 157     PitChannel2,
 158     PitReadBack
 159 } TIMER_CHANNELS;
 160
 161 typedef union _TIMER_CONTROL_PORT_REGISTER
 162 {
 163     struct
 164     {
 165         UCHAR BcdMode:1;
 166         UCHAR OperatingMode:3;
 167         UCHAR AccessMode:2;
 168         UCHAR Channel:2;
 169     };
 170     UCHAR Bits;
 171 } TIMER_CONTROL_PORT_REGISTER, *PTIMER_CONTROL_PORT_REGISTER;
 172
 173 //
 174 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 175 // P. 400
 176 //
 177 // This port is controled by the i8255 Programmable Peripheral Interface (PPI)
 178 //
 179 #define SYSTEM_CONTROL_PORT_A   0x92
 180 #define SYSTEM_CONTROL_PORT_B   0x61
 181 typedef union _SYSTEM_CONTROL_PORT_B_REGISTER
 182 {
 183     struct
 184     {
 185         UCHAR Timer2GateToSpeaker:1;
 186         UCHAR SpeakerDataEnable:1;
 187         UCHAR ParityCheckEnable:1;
 188         UCHAR ChannelCheckEnable:1;
 189         UCHAR RefreshRequest:1;
 190         UCHAR Timer2Output:1;
 191         UCHAR ChannelCheck:1;
 192         UCHAR ParityCheck:1;
 193     };
 194     UCHAR Bits;
 195 } SYSTEM_CONTROL_PORT_B_REGISTER, *PSYSTEM_CONTROL_PORT_B_REGISTER;
 196
 197 //
 198 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 199 // P. 396, 397
 200 //
 201 // These ports are controlled by the i8259 Programmable Interrupt Controller (PIC)
 202 //
 203 #define PIC1_CONTROL_PORT      0x20
 204 #define PIC1_DATA_PORT         0x21
 205 #define PIC2_CONTROL_PORT      0xA0
 206 #define PIC2_DATA_PORT         0xA1
 207
 208 //
 209 // Definitions for ICW/OCW Bits
 210 //
 211 typedef enum _I8259_ICW1_OPERATING_MODE
 212 {
 213     Cascade,
 214     Single
 215 } I8259_ICW1_OPERATING_MODE;
 216
 217 typedef enum _I8259_ICW1_INTERRUPT_MODE
 218 {
 219     EdgeTriggered,
 220     LevelTriggered
 221 } I8259_ICW1_INTERRUPT_MODE;
 222
 223 typedef enum _I8259_ICW1_INTERVAL
 224 {
 225     Interval8,
 226     Interval4
 227 } I8259_ICW1_INTERVAL;
 228
 229 typedef enum _I8259_ICW4_SYSTEM_MODE
 230 {
 231     Mcs8085Mode,
 232     New8086Mode
 233 } I8259_ICW4_SYSTEM_MODE;
 234
 235 typedef enum _I8259_ICW4_EOI_MODE
 236 {
 237     NormalEoi,
 238     AutomaticEoi
 239 } I8259_ICW4_EOI_MODE;
 240
 241 typedef enum _I8259_ICW4_BUFFERED_MODE
 242 {
 243     NonBuffered,
 244     NonBuffered2,
 245     BufferedSlave,
 246     BufferedMaster
 247 } I8259_ICW4_BUFFERED_MODE;
 248
 249 typedef enum _I8259_READ_REQUEST
 250 {
 251     InvalidRequest,
 252     InvalidRequest2,
 253     ReadIdr,
 254     ReadIsr
 255 } I8259_READ_REQUEST;
 256
 257 typedef enum _I8259_EOI_MODE
 258 {
 259     RotateAutoEoiClear,
 260     NonSpecificEoi,
 261     InvalidEoiMode,
 262     SpecificEoi,
 263     RotateAutoEoiSet,
 264     RotateNonSpecific,
 265     SetPriority,
 266     RotateSpecific
 267 } I8259_EOI_MODE;
 268
 269 //
 270 // Definitions for ICW Registers
 271 //
 272 typedef union _I8259_ICW1
 273 {
 274     struct
 275     {
 276         UCHAR NeedIcw4:1;
 277         UCHAR OperatingMode:1;
 278         UCHAR Interval:1;
 279         UCHAR InterruptMode:1;
 280         UCHAR Init:1;
 281         UCHAR InterruptVectorAddress:3;
 282     };
 283     UCHAR Bits;
 284 } I8259_ICW1, *PI8259_ICW1;
 285
 286 typedef union _I8259_ICW2
 287 {
 288     struct
 289     {
 290         UCHAR Sbz:3;
 291         UCHAR InterruptVector:5;
 292     };
 293     UCHAR Bits;
 294 } I8259_ICW2, *PI8259_ICW2;
 295
 296 typedef union _I8259_ICW3
 297 {
 298     union
 299     {
 300         struct
 301         {
 302             UCHAR SlaveIrq0:1;
 303             UCHAR SlaveIrq1:1;
 304             UCHAR SlaveIrq2:1;
 305             UCHAR SlaveIrq3:1;
 306             UCHAR SlaveIrq4:1;
 307             UCHAR SlaveIrq5:1;
 308             UCHAR SlaveIrq6:1;
 309             UCHAR SlaveIrq7:1;
 310         };
 311         struct
 312         {
 313             UCHAR SlaveId:3;
 314             UCHAR Reserved:5;
 315         };
 316     };
 317     UCHAR Bits;
 318 } I8259_ICW3, *PI8259_ICW3;
 319
 320 typedef union _I8259_ICW4
 321 {
 322     struct
 323     {
 324         UCHAR SystemMode:1;
 325         UCHAR EoiMode:1;
 326         UCHAR BufferedMode:2;
 327         UCHAR SpecialFullyNestedMode:1;
 328         UCHAR Reserved:3;
 329     };
 330     UCHAR Bits;
 331 } I8259_ICW4, *PI8259_ICW4;
 332
 333 typedef union _I8259_OCW2
 334 {
 335     struct
 336     {
 337         UCHAR IrqNumber:3;
 338         UCHAR Sbz:2;
 339         UCHAR EoiMode:3;
 340     };
 341     UCHAR Bits;
 342 } I8259_OCW2, *PI8259_OCW2;
 343
 344 typedef union _I8259_OCW3
 345 {
 346     struct
 347     {
 348         UCHAR ReadRequest:2;
 349         UCHAR PollCommand:1;
 350         UCHAR Sbo:1;
 351         UCHAR Sbz:1;
 352         UCHAR SpecialMaskMode:2;
 353         UCHAR Reserved:1;
 354     };
 355     UCHAR Bits;
 356 } I8259_OCW3, *PI8259_OCW3;
 357
 358 typedef union _I8259_ISR
 359 {
 360     union
 361     {
 362         struct
 363         {
 364             UCHAR Irq0:1;
 365             UCHAR Irq1:1;
 366             UCHAR Irq2:1;
 367             UCHAR Irq3:1;
 368             UCHAR Irq4:1;
 369             UCHAR Irq5:1;
 370             UCHAR Irq6:1;
 371             UCHAR Irq7:1;
 372         };
 373     };
 374     UCHAR Bits;
 375 } I8259_ISR, *PI8259_ISR;
 376
 377 typedef I8259_ISR I8259_IDR, *PI8259_IDR;
 378
 379 //
 380 // See EISA System Architecture 2nd Edition (Tom Shanley, Don Anderson, John Swindle)
 381 // P. 34, 35
 382 //
 383 // These ports are controlled by the i8259A Programmable Interrupt Controller (PIC)
 384 //
 385 #define EISA_ELCR_MASTER       0x4D0
 386 #define EISA_ELCR_SLAVE        0x4D1
 387
 388 typedef union _EISA_ELCR
 389 {
 390     struct
 391     {
 392         struct
 393         {
 394             UCHAR Irq0Level:1;
 395             UCHAR Irq1Level:1;
 396             UCHAR Irq2Level:1;
 397             UCHAR Irq3Level:1;
 398             UCHAR Irq4Level:1;
 399             UCHAR Irq5Level:1;
 400             UCHAR Irq6Level:1;
 401             UCHAR Irq7Level:1;
 402         } Master;
 403         struct
 404         {
 405             UCHAR Irq8Level:1;
 406             UCHAR Irq9Level:1;
 407             UCHAR Irq10Level:1;
 408             UCHAR Irq11Level:1;
 409             UCHAR Irq12Level:1;
 410             UCHAR Irq13Level:1;
 411             UCHAR Irq14Level:1;
 412             UCHAR Irq15Level:1;
 413         } Slave;
 414     };
 415     USHORT Bits;
 416 } EISA_ELCR, *PEISA_ELCR;
 417
 418 typedef struct _PIC_MASK
 419 {
 420     union
 421     {
 422         struct
 423         {
 424             UCHAR Master;
 425             UCHAR Slave;
 426         };
 427         USHORT Both;
 428     };
 429 } PIC_MASK, *PPIC_MASK;
 430
 431 typedef
 432 BOOLEAN
 433 ( REGISTERCALL *PHAL_DISMISS_INTERRUPT)(
 434     IN KIRQL Irql,
 435     IN ULONG Irq,
 436     OUT PKIRQL OldIrql
 437 );
 438
 439 BOOLEAN
 440 REGISTERCALL
 441 HalpDismissIrqGeneric(
 442     IN KIRQL Irql,
 443     IN ULONG Irq,
 444     OUT PKIRQL OldIrql
 445 );
 446
 447 BOOLEAN
 448 REGISTERCALL
 449 HalpDismissIrq15(
 450     IN KIRQL Irql,
 451     IN ULONG Irq,
 452     OUT PKIRQL OldIrql
 453 );
 454
 455 BOOLEAN
 456 REGISTERCALL
 457 HalpDismissIrq13(
 458     IN KIRQL Irql,
 459     IN ULONG Irq,
 460     OUT PKIRQL OldIrql
 461 );
 462
 463 BOOLEAN
 464 REGISTERCALL
 465 HalpDismissIrq07(
 466     IN KIRQL Irql,
 467     IN ULONG Irq,
 468     OUT PKIRQL OldIrql
 469 );
 470
 471 BOOLEAN
 472 REGISTERCALL
 473 HalpDismissIrqLevel(
 474     IN KIRQL Irql,
 475     IN ULONG Irq,
 476     OUT PKIRQL OldIrql
 477 );
 478
 479 BOOLEAN
 480 REGISTERCALL
 481 HalpDismissIrq15Level(
 482     IN KIRQL Irql,
 483     IN ULONG Irq,
 484     OUT PKIRQL OldIrql
 485 );
 486
 487 BOOLEAN
 488 REGISTERCALL
 489 HalpDismissIrq13Level(
 490     IN KIRQL Irql,
 491     IN ULONG Irq,
 492     OUT PKIRQL OldIrql
 493 );
 494
 495 BOOLEAN
 496 REGISTERCALL
 497 HalpDismissIrq07Level(
 498     IN KIRQL Irql,
 499     IN ULONG Irq,
 500     OUT PKIRQL OldIrql
 501 );
 502
 503 VOID
 504 HalpHardwareInterruptLevel(
 505     VOID
 506 );
 507
 508 //
 509 // Hack Flags
 510 //
 511 #define HALP_REVISION_FROM_HACK_FLAGS(x)    ((x) >> 24)
 512 #define HALP_REVISION_HACK_FLAGS(x)         ((x) >> 12)
 513 #define HALP_HACK_FLAGS(x)                  ((x) & 0xFFF)
 514
 515 //
 516 // Feature flags
 517 //
 518 #define HALP_CARD_FEATURE_FULL_DECODE   0x0001
 519
 520 //
 521 // Match Flags
 522 //
 523 #define HALP_CHECK_CARD_REVISION_ID     0x10000
 524 #define HALP_CHECK_CARD_SUBVENDOR_ID    0x20000
 525 #define HALP_CHECK_CARD_SUBSYSTEM_ID    0x40000
 526
 527 //
 528 // Mm PTE/PDE to Hal PTE/PDE
 529 //
 530 #define HalAddressToPde(x) (PHARDWARE_PTE)MiAddressToPde(x)
 531 #define HalAddressToPte(x) (PHARDWARE_PTE)MiAddressToPte(x)
 532
 533 typedef struct _IDTUsageFlags
 534 {
 535     UCHAR Flags;
 536 } IDTUsageFlags;
 537
 538 typedef struct
 539 {
 540     KIRQL Irql;
 541     UCHAR BusReleativeVector;
 542 } IDTUsage;
 543
 544 typedef struct _HalAddressUsage
 545 {
 546     struct _HalAddressUsage *Next;
 547     CM_RESOURCE_TYPE Type;
 548     UCHAR Flags;
 549     struct
 550     {
 551         ULONG Start;
 552         ULONG Length;
 553     } Element[];
 554 } ADDRESS_USAGE, *PADDRESS_USAGE;
 555
 556 /* adapter.c */
 557 PADAPTER_OBJECT NTAPI HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
 558
 559 /* sysinfo.c */
 560 VOID
 561 NTAPI
 562 HalpRegisterVector(IN UCHAR Flags,
 563                    IN ULONG BusVector,
 564                    IN ULONG SystemVector,
 565                    IN KIRQL Irql);
 566
 567 VOID
 568 NTAPI
 569 HalpEnableInterruptHandler(IN UCHAR Flags,
 570                            IN ULONG BusVector,
 571                            IN ULONG SystemVector,
 572                            IN KIRQL Irql,
 573                            IN PVOID Handler,
 574                            IN KINTERRUPT_MODE Mode);
 575
 576 /* pic.c */
 577 VOID NTAPI HalpInitializePICs(IN BOOLEAN EnableInterrupts);
 578 VOID HalpApcInterrupt(VOID);
 579 VOID HalpDispatchInterrupt(VOID);
 580 VOID HalpDispatchInterrupt2(VOID);
 581 DECLSPEC_NORETURN VOID FASTCALL HalpApcInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
 582 DECLSPEC_NORETURN VOID FASTCALL HalpDispatchInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
 583
 584 /* profil.c */
 585 extern BOOLEAN HalpProfilingStopped;
 586
 587 /* timer.c */
 588 VOID NTAPI HalpInitializeClock(VOID);
 589 VOID HalpClockInterrupt(VOID);
 590 VOID HalpProfileInterrupt(VOID);
 591
 592 VOID
 593 NTAPI
 594 HalpCalibrateStallExecution(VOID);
 595
 596 /* pci.c */
 597 VOID HalpInitPciBus (VOID);
 598
 599 /* dma.c */
 600 VOID HalpInitDma (VOID);
 601
 602 /* Non-generic initialization */
 603 VOID HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock);
 604 VOID HalpInitPhase1(VOID);
 605
 606 VOID
 607 NTAPI
 608 HalpFlushTLB(VOID);
 609
 610 //
 611 // KD Support
 612 //
 613 VOID
 614 NTAPI
 615 HalpCheckPowerButton(
 616     VOID
 617 );
 618
 619 VOID
 620 NTAPI
 621 HalpRegisterKdSupportFunctions(
 622     VOID
 623 );
 624
 625 NTSTATUS
 626 NTAPI
 627 HalpSetupPciDeviceForDebugging(
 628     IN PVOID LoaderBlock,
 629     IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
 630 );
 631
 632 NTSTATUS
 633 NTAPI
 634 HalpReleasePciDeviceForDebugging(
 635     IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
 636 );
 637
 638 //
 639 // Memory routines
 640 //
 641 ULONG_PTR
 642 NTAPI
 643 HalpAllocPhysicalMemory(
 644     IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 645     IN ULONG_PTR MaxAddress,
 646     IN PFN_NUMBER PageCount,
 647     IN BOOLEAN Aligned
 648 );
 649
 650 PVOID
 651 NTAPI
 652 HalpMapPhysicalMemory64(
 653     IN PHYSICAL_ADDRESS PhysicalAddress,
 654     IN PFN_COUNT PageCount
 655 );
 656
 657 VOID
 658 NTAPI
 659 HalpUnmapVirtualAddress(
 660     IN PVOID VirtualAddress,
 661     IN PFN_COUNT NumberPages
 662 );
 663
 664 /* sysinfo.c */
 665 NTSTATUS
 666 NTAPI
 667 HaliQuerySystemInformation(
 668     IN HAL_QUERY_INFORMATION_CLASS InformationClass,
 669     IN ULONG BufferSize,
 670     IN OUT PVOID Buffer,
 671     OUT PULONG ReturnedLength
 672 );
 673
 674 NTSTATUS
 675 NTAPI
 676 HaliSetSystemInformation(
 677     IN HAL_SET_INFORMATION_CLASS InformationClass,
 678     IN ULONG BufferSize,
 679     IN OUT PVOID Buffer
 680 );
 681
 682 //
 683 // BIOS Routines
 684 //
 685 BOOLEAN
 686 NTAPI
 687 HalpBiosDisplayReset(
 688     VOID
 689 );
 690
 691 VOID
 692 FASTCALL
 693 HalpExitToV86(
 694     PKTRAP_FRAME TrapFrame
 695 );
 696
 697 VOID
 698 DECLSPEC_NORETURN
 699 HalpRealModeStart(
 700     VOID
 701 );
 702
 703 //
 704 // Processor Halt Routine
 705 //
 706 VOID
 707 NTAPI
 708 HaliHaltSystem(
 709     VOID
 710 );
 711
 712 //
 713 // CMOS Routines
 714 //
 715 VOID
 716 NTAPI
 717 HalpInitializeCmos(
 718     VOID
 719 );
 720
 721 UCHAR
 722 NTAPI
 723 HalpReadCmos(
 724     IN UCHAR Reg
 725 );
 726
 727 VOID
 728 NTAPI
 729 HalpWriteCmos(
 730     IN UCHAR Reg,
 731     IN UCHAR Value
 732 );
 733
 734 //
 735 // Spinlock for protecting CMOS access
 736 //
 737 VOID
 738 NTAPI
 739 HalpAcquireCmosSpinLock(
 740     VOID
 741 );
 742
 743 VOID
 744 NTAPI
 745 HalpReleaseCmosSpinLock(
 746     VOID
 747 );
 748
 749 NTSTATUS
 750 NTAPI
 751 HalpOpenRegistryKey(
 752     IN PHANDLE KeyHandle,
 753     IN HANDLE RootKey,
 754     IN PUNICODE_STRING KeyName,
 755     IN ACCESS_MASK DesiredAccess,
 756     IN BOOLEAN Create
 757 );
 758
 759 VOID
 760 NTAPI
 761 HalpGetNMICrashFlag(
 762     VOID
 763 );
 764
 765 BOOLEAN
 766 NTAPI
 767 HalpGetDebugPortTable(
 768     VOID
 769 );
 770
 771 VOID
 772 NTAPI
 773 HalpReportSerialNumber(
 774     VOID
 775 );
 776
 777 NTSTATUS
 778 NTAPI
 779 HalpMarkAcpiHal(
 780     VOID
 781 );
 782
 783 VOID
 784 NTAPI
 785 HalpBuildAddressMap(
 786     VOID
 787 );
 788
 789 VOID
 790 NTAPI
 791 HalpReportResourceUsage(
 792     IN PUNICODE_STRING HalName,
 793     IN INTERFACE_TYPE InterfaceType
 794 );
 795
 796 ULONG
 797 NTAPI
 798 HalpIs16BitPortDecodeSupported(
 799     VOID
 800 );
 801
 802 NTSTATUS
 803 NTAPI
 804 HalpQueryAcpiResourceRequirements(
 805     OUT PIO_RESOURCE_REQUIREMENTS_LIST *Requirements
 806 );
 807
 808 VOID
 809 FASTCALL
 810 KeUpdateSystemTime(
 811     IN PKTRAP_FRAME TrapFrame,
 812     IN ULONG Increment,
 813     IN KIRQL OldIrql
 814 );
 815
 816 VOID
 817 NTAPI
 818 HalpInitBusHandlers(
 819     VOID
 820 );
 821
 822 NTSTATUS
 823 NTAPI
 824 HaliInitPnpDriver(
 825     VOID
 826 );
 827
 828 VOID
 829 NTAPI
 830 HalpDebugPciDumpBus(
 831     IN ULONG i,
 832     IN ULONG j,
 833     IN ULONG k,
 834     IN PPCI_COMMON_CONFIG PciData
 835 );
 836
 837 VOID
 838 NTAPI
 839 HalpInitProcessor(
 840     IN ULONG ProcessorNumber,
 841     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 842 );
 843
 844 #ifdef _M_AMD64
 845 #define KfLowerIrql KeLowerIrql
 846 #define KiEnterInterruptTrap(TrapFrame) /* We do all neccessary in asm code */
 847 #define KiEoiHelper(TrapFrame) return /* Just return to the caller */
 848 #define HalBeginSystemInterrupt(Irql, Vector, OldIrql) ((*(OldIrql) = PASSIVE_LEVEL), TRUE)
 849 #ifndef CONFIG_SMP
 850 /* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
 851 #define KiAcquireSpinLock(SpinLock)
 852 #define KiReleaseSpinLock(SpinLock)
 853 #define KfAcquireSpinLock(SpinLock) KfRaiseIrql(DISPATCH_LEVEL);
 854 #define KfReleaseSpinLock(SpinLock, OldIrql) KeLowerIrql(OldIrql);
 855 #endif // !CONFIG_SMP
 856 #endif // _M_AMD64
 857
 858 extern BOOLEAN HalpNMIInProgress;
 859
 860 extern ADDRESS_USAGE HalpDefaultIoSpace;
 861
 862 extern KSPIN_LOCK HalpSystemHardwareLock;
 863
 864 extern PADDRESS_USAGE HalpAddressUsageList;
 865
 866 extern LARGE_INTEGER HalpPerfCounter;
 867
 868 extern KAFFINITY HalpActiveProcessors;
 869
 870 extern BOOLEAN HalDisableFirmwareMapper;
 871 extern PWCHAR HalHardwareIdString;
 872 extern PWCHAR HalName;
 873
 874 extern KAFFINITY HalpDefaultInterruptAffinity;
 875
 876 extern IDTUsageFlags HalpIDTUsageFlags[MAXIMUM_IDTVECTOR+1];
 877
 878 extern const USHORT HalpBuildType;