reactos/hal/halx86/include/halp.h

   1 /*
   2  *
   3  */
   4
   5 #ifndef __INTERNAL_HAL_HAL_H
   6 #define __INTERNAL_HAL_HAL_H
   7
   8 typedef struct _HAL_BIOS_FRAME
   9 {
  10     ULONG SegSs;
  11     ULONG Esp;
  12     ULONG EFlags;
  13     ULONG SegCs;
  14     ULONG Eip;
  15     PKTRAP_FRAME TrapFrame;
  16     ULONG CsLimit;
  17     ULONG CsBase;
  18     ULONG CsFlags;
  19     ULONG SsLimit;
  20     ULONG SsBase;
  21     ULONG SsFlags;
  22     ULONG Prefix;
  23 } HAL_BIOS_FRAME, *PHAL_BIOS_FRAME;
  24
  25 typedef
  26 VOID
  27 (*PHAL_SW_INTERRUPT_HANDLER)(
  28     VOID
  29 );
  30
  31 typedef
  32 FASTCALL
  33 VOID
  34 DECLSPEC_NORETURN
  35 (*PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY)(
  36     IN PKTRAP_FRAME TrapFrame
  37 );
  38
  39 #define HAL_APC_REQUEST         0
  40 #define HAL_DPC_REQUEST         1
  41
  42 /* CMOS Registers and Ports */
  43 #define CMOS_CONTROL_PORT       (PUCHAR)0x70
  44 #define CMOS_DATA_PORT          (PUCHAR)0x71
  45 #define RTC_REGISTER_A          0x0A
  46 #define RTC_REGISTER_B          0x0B
  47 #define RTC_REG_A_UIP           0x80
  48 #define RTC_REGISTER_CENTURY    0x32
  49
  50 /* Usage flags */
  51 #define IDT_REGISTERED          0x01
  52 #define IDT_LATCHED             0x02
  53 #define IDT_INTERNAL            0x11
  54 #define IDT_DEVICE              0x21
  55
  56 /* Conversion functions */
  57 #define BCD_INT(bcd)            \
  58     (((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F))
  59 #define INT_BCD(int)            \
  60     (UCHAR)(((int / 10) << 4) + (int % 10))
  61
  62 //
  63 // BIOS Interrupts
  64 //
  65 #define VIDEO_SERVICES   0x10
  66
  67 //
  68 // Operations for INT 10h (in AH)
  69 //
  70 #define SET_VIDEO_MODE   0x00
  71
  72 //
  73 // Video Modes for INT10h AH=00 (in AL)
  74 //
  75 #define GRAPHICS_MODE_12 0x12           /* 80x30         8x16  640x480   16/256K */
  76
  77 //
  78 // Generates a 16-bit (real-mode or Virtual 8086) BIOS interrupt with a given AX */
  79 //
  80 VOID
  81 FORCEINLINE
  82 HalpCallBiosInterrupt(IN ULONG Interrupt,
  83                       IN ULONG Ax)
  84 {
  85     __asm__ __volatile__
  86     (
  87         ".byte 0x66\n"
  88         "movl $%c[v], %%eax\n"
  89         "int $%c[i]\n"
  90         :
  91         : [v] "i"(Ax),
  92           [i] "i"(Interrupt)
  93     );
  94 }
  95
  96 //
  97 // Constructs a stack of the given size and alignment in the real-mode .text region */
  98 //
  99 VOID
 100 FORCEINLINE
 101 HalpRealModeStack(IN ULONG Alignment,
 102                   IN ULONG Size)
 103 {
 104     __asm__ __volatile__
 105     (
 106         ".align %c[v]\n"
 107         ".space %c[i]\n"
 108         ".globl _HalpRealModeEnd\n_HalpRealModeEnd:\n"
 109         :
 110         : [v] "i"(Alignment),
 111           [i] "i"(Size)
 112     );
 113 }
 114
 115 //
 116 // Commonly stated as being 1.19318MHz
 117 //
 118 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 119 // P. 471
 120 //
 121 // However, the true value is closer to 1.19318181[...]81MHz since this is 1/3rd
 122 // of the NTSC color subcarrier frequency which runs at 3.57954545[...]45MHz.
 123 //
 124 // Note that Windows uses 1.193167MHz which seems to have no basis. However, if
 125 // one takes the NTSC color subcarrier frequency as being 3.579545 (trimming the
 126 // infinite series) and divides it by three, one obtains 1.19318167.
 127 //
 128 // It may be that the original NT HAL source code introduced a typo and turned
 129 // 119318167 into 1193167 by ommitting the "18". This is very plausible as the
 130 // number is quite long.
 131 //
 132 #define PIT_FREQUENCY 1193182
 133
 134 //
 135 // These ports are controlled by the i8254 Programmable Interrupt Timer (PIT)
 136 //
 137 #define TIMER_CHANNEL0_DATA_PORT 0x40
 138 #define TIMER_CHANNEL1_DATA_PORT 0x41
 139 #define TIMER_CHANNEL2_DATA_PORT 0x42
 140 #define TIMER_CONTROL_PORT       0x43
 141
 142 //
 143 // Mode 0 - Interrupt On Terminal Count
 144 // Mode 1 - Hardware Re-triggerable One-Shot
 145 // Mode 2 - Rate Generator
 146 // Mode 3 - Square Wave Generator
 147 // Mode 4 - Software Triggered Strobe
 148 // Mode 5 - Hardware Triggered Strobe
 149 //
 150 typedef enum _TIMER_OPERATING_MODES
 151 {
 152     PitOperatingMode0,
 153     PitOperatingMode1,
 154     PitOperatingMode2,
 155     PitOperatingMode3,
 156     PitOperatingMode4,
 157     PitOperatingMode5,
 158     PitOperatingMode2Reserved,
 159     PitOperatingMode5Reserved
 160 } TIMER_OPERATING_MODES;
 161
 162 typedef enum _TIMER_ACCESS_MODES
 163 {
 164     PitAccessModeCounterLatch,
 165     PitAccessModeLow,
 166     PitAccessModeHigh,
 167     PitAccessModeLowHigh
 168 } TIMER_ACCESS_MODES;
 169
 170 typedef enum _TIMER_CHANNELS
 171 {
 172     PitChannel0,
 173     PitChannel1,
 174     PitChannel2,
 175     PitReadBack
 176 } TIMER_CHANNELS;
 177
 178 typedef union _TIMER_CONTROL_PORT_REGISTER
 179 {
 180     struct
 181     {
 182         UCHAR BcdMode:1;
 183         TIMER_OPERATING_MODES OperatingMode:3;
 184         TIMER_ACCESS_MODES AccessMode:2;
 185         TIMER_CHANNELS Channel:2;
 186     };
 187     UCHAR Bits;
 188 } TIMER_CONTROL_PORT_REGISTER, *PTIMER_CONTROL_PORT_REGISTER;
 189
 190 //
 191 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 192 // P. 400
 193 //
 194 // This port is controled by the i8255 Programmable Peripheral Interface (PPI)
 195 //
 196 #define SYSTEM_CONTROL_PORT_A   0x92
 197 #define SYSTEM_CONTROL_PORT_B   0x61
 198 typedef union _SYSTEM_CONTROL_PORT_B_REGISTER
 199 {
 200     struct
 201     {
 202         UCHAR Timer2GateToSpeaker:1;
 203         UCHAR SpeakerDataEnable:1;
 204         UCHAR ParityCheckEnable:1;
 205         UCHAR ChannelCheckEnable:1;
 206         UCHAR RefreshRequest:1;
 207         UCHAR Timer2Output:1;
 208         UCHAR ChannelCheck:1;
 209         UCHAR ParityCheck:1;
 210     };
 211     UCHAR Bits;
 212 } SYSTEM_CONTROL_PORT_B_REGISTER, *PSYSTEM_CONTROL_PORT_B_REGISTER;
 213
 214 //
 215 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 216 // P. 396, 397
 217 //
 218 // These ports are controlled by the i8259 Programmable Interrupt Controller (PIC)
 219 //
 220 #define PIC1_CONTROL_PORT      0x20
 221 #define PIC1_DATA_PORT         0x21
 222 #define PIC2_CONTROL_PORT      0xA0
 223 #define PIC2_DATA_PORT         0xA1
 224
 225 //
 226 // Definitions for ICW/OCW Bits
 227 //
 228 typedef enum _I8259_ICW1_OPERATING_MODE
 229 {
 230     Cascade,
 231     Single
 232 } I8259_ICW1_OPERATING_MODE;
 233
 234 typedef enum _I8259_ICW1_INTERRUPT_MODE
 235 {
 236     EdgeTriggered,
 237     LevelTriggered
 238 } I8259_ICW1_INTERRUPT_MODE;
 239
 240 typedef enum _I8259_ICW1_INTERVAL
 241 {
 242     Interval8,
 243     Interval4
 244 } I8259_ICW1_INTERVAL;
 245
 246 typedef enum _I8259_ICW4_SYSTEM_MODE
 247 {
 248     Mcs8085Mode,
 249     New8086Mode
 250 } I8259_ICW4_SYSTEM_MODE;
 251
 252 typedef enum _I8259_ICW4_EOI_MODE
 253 {
 254     NormalEoi,
 255     AutomaticEoi
 256 } I8259_ICW4_EOI_MODE;
 257
 258 typedef enum _I8259_ICW4_BUFFERED_MODE
 259 {
 260     NonBuffered,
 261     NonBuffered2,
 262     BufferedSlave,
 263     BufferedMaster
 264 } I8259_ICW4_BUFFERED_MODE;
 265
 266 typedef enum _I8259_READ_REQUEST
 267 {
 268     InvalidRequest,
 269     InvalidRequest2,
 270     ReadIdr,
 271     ReadIsr
 272 } I8259_READ_REQUEST;
 273
 274 typedef enum _I8259_EOI_MODE
 275 {
 276     RotateAutoEoiClear,
 277     NonSpecificEoi,
 278     InvalidEoiMode,
 279     SpecificEoi,
 280     RotateAutoEoiSet,
 281     RotateNonSpecific,
 282     SetPriority,
 283     RotateSpecific
 284 } I8259_EOI_MODE;
 285
 286 //
 287 // Definitions for ICW Registers
 288 //
 289 typedef union _I8259_ICW1
 290 {
 291     struct
 292     {
 293         UCHAR NeedIcw4:1;
 294         I8259_ICW1_OPERATING_MODE OperatingMode:1;
 295         I8259_ICW1_INTERVAL Interval:1;
 296         I8259_ICW1_INTERRUPT_MODE InterruptMode:1;
 297         UCHAR Init:1;
 298         UCHAR InterruptVectorAddress:3;
 299     };
 300     UCHAR Bits;
 301 } I8259_ICW1, *PI8259_ICW1;
 302
 303 typedef union _I8259_ICW2
 304 {
 305     struct
 306     {
 307         UCHAR Sbz:3;
 308         UCHAR InterruptVector:5;
 309     };
 310     UCHAR Bits;
 311 } I8259_ICW2, *PI8259_ICW2;
 312
 313 typedef union _I8259_ICW3
 314 {
 315     union
 316     {
 317         struct
 318         {
 319             UCHAR SlaveIrq0:1;
 320             UCHAR SlaveIrq1:1;
 321             UCHAR SlaveIrq2:1;
 322             UCHAR SlaveIrq3:1;
 323             UCHAR SlaveIrq4:1;
 324             UCHAR SlaveIrq5:1;
 325             UCHAR SlaveIrq6:1;
 326             UCHAR SlaveIrq7:1;
 327         };
 328         struct
 329         {
 330             UCHAR SlaveId:3;
 331             UCHAR Reserved:5;
 332         };
 333     };
 334     UCHAR Bits;
 335 } I8259_ICW3, *PI8259_ICW3;
 336
 337 typedef union _I8259_ICW4
 338 {
 339     struct
 340     {
 341         I8259_ICW4_SYSTEM_MODE SystemMode:1;
 342         I8259_ICW4_EOI_MODE EoiMode:1;
 343         I8259_ICW4_BUFFERED_MODE BufferedMode:2;
 344         UCHAR SpecialFullyNestedMode:1;
 345         UCHAR Reserved:3;
 346     };
 347     UCHAR Bits;
 348 } I8259_ICW4, *PI8259_ICW4;
 349
 350 typedef union _I8259_OCW2
 351 {
 352     struct
 353     {
 354         UCHAR IrqNumber:3;
 355         UCHAR Sbz:2;
 356         I8259_EOI_MODE EoiMode:3;
 357     };
 358     UCHAR Bits;
 359 } I8259_OCW2, *PI8259_OCW2;
 360
 361 typedef union _I8259_OCW3
 362 {
 363     struct
 364     {
 365         I8259_READ_REQUEST ReadRequest:2;
 366         UCHAR PollCommand:1;
 367         UCHAR Sbo:1;
 368         UCHAR Sbz:1;
 369         UCHAR SpecialMaskMode:2;
 370         UCHAR Reserved:1;
 371     };
 372     UCHAR Bits;
 373 } I8259_OCW3, *PI8259_OCW3;
 374
 375 typedef union _I8259_ISR
 376 {
 377     union
 378     {
 379         struct
 380         {
 381             UCHAR Irq0:1;
 382             UCHAR Irq1:1;
 383             UCHAR Irq2:1;
 384             UCHAR Irq3:1;
 385             UCHAR Irq4:1;
 386             UCHAR Irq5:1;
 387             UCHAR Irq6:1;
 388             UCHAR Irq7:1;
 389         };
 390     };
 391     UCHAR Bits;
 392 } I8259_ISR, *PI8259_ISR;
 393
 394 typedef I8259_ISR I8259_IDR, *PI8259_IDR;
 395
 396 //
 397 // See EISA System Architecture 2nd Edition (Tom Shanley, Don Anderson, John Swindle)
 398 // P. 34, 35
 399 //
 400 // These ports are controlled by the i8259A Programmable Interrupt Controller (PIC)
 401 //
 402 #define EISA_ELCR_MASTER       0x4D0
 403 #define EISA_ELCR_SLAVE        0x4D1
 404
 405 typedef union _EISA_ELCR
 406 {
 407     struct
 408     {
 409         struct
 410         {
 411             UCHAR Irq0Level:1;
 412             UCHAR Irq1Level:1;
 413             UCHAR Irq2Level:1;
 414             UCHAR Irq3Level:1;
 415             UCHAR Irq4Level:1;
 416             UCHAR Irq5Level:1;
 417             UCHAR Irq6Level:1;
 418             UCHAR Irq7Level:1;
 419         } Master;
 420         struct
 421         {
 422             UCHAR Irq8Level:1;
 423             UCHAR Irq9Level:1;
 424             UCHAR Irq10Level:1;
 425             UCHAR Irq11Level:1;
 426             UCHAR Irq12Level:1;
 427             UCHAR Irq13Level:1;
 428             UCHAR Irq14Level:1;
 429             UCHAR Irq15Level:1;
 430         } Slave;
 431     };
 432     USHORT Bits;
 433 } EISA_ELCR, *PEISA_ELCR;
 434
 435 typedef struct _PIC_MASK
 436 {
 437     union
 438     {
 439         struct
 440         {
 441             UCHAR Master;
 442             UCHAR Slave;
 443         };
 444         USHORT Both;
 445     };
 446 } PIC_MASK, *PPIC_MASK;
 447
 448 typedef
 449 BOOLEAN
 450 __attribute__((regparm(3)))
 451 (*PHAL_DISMISS_INTERRUPT)(
 452     IN KIRQL Irql,
 453     IN ULONG Irq,
 454     OUT PKIRQL OldIrql
 455 );
 456
 457 BOOLEAN
 458 __attribute__((regparm(3)))
 459 HalpDismissIrqGeneric(
 460     IN KIRQL Irql,
 461     IN ULONG Irq,
 462     OUT PKIRQL OldIrql
 463 );
 464
 465 BOOLEAN
 466 __attribute__((regparm(3)))
 467 HalpDismissIrq15(
 468     IN KIRQL Irql,
 469     IN ULONG Irq,
 470     OUT PKIRQL OldIrql
 471 );
 472
 473 BOOLEAN
 474 __attribute__((regparm(3)))
 475 HalpDismissIrq13(
 476     IN KIRQL Irql,
 477     IN ULONG Irq,
 478     OUT PKIRQL OldIrql
 479 );
 480
 481 BOOLEAN
 482 __attribute__((regparm(3)))
 483 HalpDismissIrq07(
 484     IN KIRQL Irql,
 485     IN ULONG Irq,
 486     OUT PKIRQL OldIrql
 487 );
 488
 489 BOOLEAN
 490 __attribute__((regparm(3)))
 491 HalpDismissIrqLevel(
 492     IN KIRQL Irql,
 493     IN ULONG Irq,
 494     OUT PKIRQL OldIrql
 495 );
 496
 497 BOOLEAN
 498 __attribute__((regparm(3)))
 499 HalpDismissIrq15Level(
 500     IN KIRQL Irql,
 501     IN ULONG Irq,
 502     OUT PKIRQL OldIrql
 503 );
 504
 505 BOOLEAN
 506 __attribute__((regparm(3)))
 507 HalpDismissIrq13Level(
 508     IN KIRQL Irql,
 509     IN ULONG Irq,
 510     OUT PKIRQL OldIrql
 511 );
 512
 513 BOOLEAN
 514 __attribute__((regparm(3)))
 515 HalpDismissIrq07Level(
 516     IN KIRQL Irql,
 517     IN ULONG Irq,
 518     OUT PKIRQL OldIrql
 519 );
 520
 521 VOID
 522 HalpHardwareInterruptLevel(
 523     VOID
 524 );
 525
 526 //
 527 // Mm PTE/PDE to Hal PTE/PDE
 528 //
 529 #define HalAddressToPde(x) (PHARDWARE_PTE)MiAddressToPde(x)
 530 #define HalAddressToPte(x) (PHARDWARE_PTE)MiAddressToPte(x)
 531
 532 typedef struct _IDTUsageFlags
 533 {
 534     UCHAR Flags;
 535 } IDTUsageFlags;
 536
 537 typedef struct
 538 {
 539     KIRQL Irql;
 540     UCHAR BusReleativeVector;
 541 } IDTUsage;
 542
 543 typedef struct _HalAddressUsage
 544 {
 545     struct _HalAddressUsage *Next;
 546     CM_RESOURCE_TYPE Type;
 547     UCHAR Flags;
 548     struct
 549     {
 550         ULONG Start;
 551         ULONG Length;
 552     } Element[];
 553 } ADDRESS_USAGE, *PADDRESS_USAGE;
 554
 555 /* adapter.c */
 556 PADAPTER_OBJECT NTAPI HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
 557
 558 /* sysinfo.c */
 559 VOID
 560 NTAPI
 561 HalpRegisterVector(IN UCHAR Flags,
 562                    IN ULONG BusVector,
 563                    IN ULONG SystemVector,
 564                    IN KIRQL Irql);
 565
 566 VOID
 567 NTAPI
 568 HalpEnableInterruptHandler(IN UCHAR Flags,
 569                            IN ULONG BusVector,
 570                            IN ULONG SystemVector,
 571                            IN KIRQL Irql,
 572                            IN PVOID Handler,
 573                            IN KINTERRUPT_MODE Mode);
 574
 575 /* pic.c */
 576 VOID NTAPI HalpInitializePICs(IN BOOLEAN EnableInterrupts);
 577 VOID HalpApcInterrupt(VOID);
 578 VOID HalpDispatchInterrupt(VOID);
 579 VOID HalpDispatchInterrupt2(VOID);
 580 VOID FASTCALL DECLSPEC_NORETURN HalpApcInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
 581 VOID FASTCALL DECLSPEC_NORETURN HalpDispatchInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
 582
 583 /* timer.c */
 584 VOID NTAPI HalpInitializeClock(VOID);
 585 VOID HalpClockInterrupt(VOID);
 586 VOID HalpProfileInterrupt(VOID);
 587
 588 VOID
 589 NTAPI
 590 HalpCalibrateStallExecution(VOID);
 591
 592 /* pci.c */
 593 VOID HalpInitPciBus (VOID);
 594
 595 /* dma.c */
 596 VOID HalpInitDma (VOID);
 597
 598 /* Non-generic initialization */
 599 VOID HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock);
 600 VOID HalpInitPhase1(VOID);
 601
 602 VOID
 603 NTAPI
 604 HalpFlushTLB(VOID);
 605
 606 //
 607 // KD Support
 608 //
 609 VOID
 610 NTAPI
 611 HalpCheckPowerButton(
 612     VOID
 613 );
 614
 615 VOID
 616 NTAPI
 617 HalpRegisterKdSupportFunctions(
 618     VOID
 619 );
 620
 621 NTSTATUS
 622 NTAPI
 623 HalpSetupPciDeviceForDebugging(
 624     IN PVOID LoaderBlock,
 625     IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
 626 );
 627
 628 NTSTATUS
 629 NTAPI
 630 HalpReleasePciDeviceForDebugging(
 631     IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
 632 );
 633
 634 //
 635 // Memory routines
 636 //
 637 PVOID
 638 NTAPI
 639 HalpMapPhysicalMemory64(
 640     IN PHYSICAL_ADDRESS PhysicalAddress,
 641     IN ULONG NumberPage
 642 );
 643
 644 VOID
 645 NTAPI
 646 HalpUnmapVirtualAddress(
 647     IN PVOID VirtualAddress,
 648     IN ULONG NumberPages
 649 );
 650
 651 /* sysinfo.c */
 652 NTSTATUS
 653 NTAPI
 654 HaliQuerySystemInformation(
 655     IN HAL_QUERY_INFORMATION_CLASS InformationClass,
 656     IN ULONG BufferSize,
 657     IN OUT PVOID Buffer,
 658     OUT PULONG ReturnedLength
 659 );
 660
 661 NTSTATUS
 662 NTAPI
 663 HaliSetSystemInformation(
 664     IN HAL_SET_INFORMATION_CLASS InformationClass,
 665     IN ULONG BufferSize,
 666     IN OUT PVOID Buffer
 667 );
 668
 669 //
 670 // BIOS Routines
 671 //
 672 BOOLEAN
 673 NTAPI
 674 HalpBiosDisplayReset(
 675     VOID
 676 );
 677
 678 //
 679 // Processor Halt Routine
 680 //
 681 VOID
 682 NTAPI
 683 HaliHaltSystem(
 684     VOID
 685 );
 686
 687 //
 688 // CMOS initialization
 689 //
 690 VOID
 691 NTAPI
 692 HalpInitializeCmos(
 693     VOID
 694 );
 695
 696 //
 697 // Spinlock for protecting CMOS access
 698 //
 699 VOID
 700 NTAPI
 701 HalpAcquireSystemHardwareSpinLock(
 702     VOID
 703 );
 704
 705 VOID
 706 NTAPI
 707 HalpReleaseCmosSpinLock(
 708     VOID
 709 );
 710
 711 //
 712 // This is duplicated from ke_x.h
 713 //
 714 #ifdef CONFIG_SMP
 715 //
 716 // Spinlock Acquisition at IRQL >= DISPATCH_LEVEL
 717 //
 718 FORCEINLINE
 719 VOID
 720 KxAcquireSpinLock(IN PKSPIN_LOCK SpinLock)
 721 {
 722     /* Make sure that we don't own the lock already */
 723     if (((KSPIN_LOCK)KeGetCurrentThread() | 1) == *SpinLock)
 724     {
 725         /* We do, bugcheck! */
 726         KeBugCheckEx(SPIN_LOCK_ALREADY_OWNED, (ULONG_PTR)SpinLock, 0, 0, 0);
 727     }
 728
 729     for (;;)
 730     {
 731         /* Try to acquire it */
 732         if (InterlockedBitTestAndSet((PLONG)SpinLock, 0))
 733         {
 734             /* Value changed... wait until it's locked */
 735             while (*(volatile KSPIN_LOCK *)SpinLock == 1)
 736             {
 737 #ifdef DBG
 738                 /* On debug builds, we use a much slower but useful routine */
 739                 //Kii386SpinOnSpinLock(SpinLock, 5);
 740
 741                 /* FIXME: Do normal yield for now */
 742                 YieldProcessor();
 743 #else
 744                 /* Otherwise, just yield and keep looping */
 745                 YieldProcessor();
 746 #endif
 747             }
 748         }
 749         else
 750         {
 751 #ifdef DBG
 752             /* On debug builds, we OR in the KTHREAD */
 753             *SpinLock = (KSPIN_LOCK)KeGetCurrentThread() | 1;
 754 #endif
 755             /* All is well, break out */
 756             break;
 757         }
 758     }
 759 }
 760
 761 //
 762 // Spinlock Release at IRQL >= DISPATCH_LEVEL
 763 //
 764 FORCEINLINE
 765 VOID
 766 KxReleaseSpinLock(IN PKSPIN_LOCK SpinLock)
 767 {
 768 #ifdef DBG
 769     /* Make sure that the threads match */
 770     if (((KSPIN_LOCK)KeGetCurrentThread() | 1) != *SpinLock)
 771     {
 772         /* They don't, bugcheck */
 773         KeBugCheckEx(SPIN_LOCK_NOT_OWNED, (ULONG_PTR)SpinLock, 0, 0, 0);
 774     }
 775 #endif
 776     /* Clear the lock */
 777     InterlockedAnd((PLONG)SpinLock, 0);
 778 }
 779
 780 #else
 781
 782 //
 783 // Spinlock Acquire at IRQL >= DISPATCH_LEVEL
 784 //
 785 FORCEINLINE
 786 VOID
 787 KxAcquireSpinLock(IN PKSPIN_LOCK SpinLock)
 788 {
 789     /* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
 790     UNREFERENCED_PARAMETER(SpinLock);
 791 }
 792
 793 //
 794 // Spinlock Release at IRQL >= DISPATCH_LEVEL
 795 //
 796 FORCEINLINE
 797 VOID
 798 KxReleaseSpinLock(IN PKSPIN_LOCK SpinLock)
 799 {
 800     /* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
 801     UNREFERENCED_PARAMETER(SpinLock);
 802 }
 803
 804 #endif
 805
 806 VOID
 807 FASTCALL
 808 KeUpdateSystemTime(
 809     IN PKTRAP_FRAME TrapFrame,
 810     IN ULONG Increment,
 811     IN KIRQL OldIrql
 812 );
 813
 814 #ifdef _M_AMD64
 815 #define KfLowerIrql KeLowerIrql
 816 #ifndef CONFIG_SMP
 817 /* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
 818 #define KiAcquireSpinLock(SpinLock)
 819 #define KiReleaseSpinLock(SpinLock)
 820 #define KfAcquireSpinLock(SpinLock) KfRaiseIrql(DISPATCH_LEVEL);
 821 #define KfReleaseSpinLock(SpinLock, OldIrql) KeLowerIrql(OldIrql);
 822 #endif // !CONFIG_SMP
 823 #endif // _M_AMD64
 824
 825 extern BOOLEAN HalpNMIInProgress;
 826
 827 extern ADDRESS_USAGE HalpDefaultIoSpace;
 828
 829 extern KSPIN_LOCK HalpSystemHardwareLock;
 830
 831 extern PADDRESS_USAGE HalpAddressUsageList;
 832
 833 extern LARGE_INTEGER HalpPerfCounter;
 834
 835 #endif /* __INTERNAL_HAL_HAL_H */