reactos/hal/halx86/include/halp.h

   1 /*
   2  *
   3  */
   4
   5 #pragma once
   6
   7 typedef struct _HAL_BIOS_FRAME
   8 {
   9     ULONG SegSs;
  10     ULONG Esp;
  11     ULONG EFlags;
  12     ULONG SegCs;
  13     ULONG Eip;
  14     PKTRAP_FRAME TrapFrame;
  15     ULONG CsLimit;
  16     ULONG CsBase;
  17     ULONG CsFlags;
  18     ULONG SsLimit;
  19     ULONG SsBase;
  20     ULONG SsFlags;
  21     ULONG Prefix;
  22 } HAL_BIOS_FRAME, *PHAL_BIOS_FRAME;
  23
  24 typedef
  25 VOID
  26 (*PHAL_SW_INTERRUPT_HANDLER)(
  27     VOID
  28 );
  29
  30 typedef
  31 FASTCALL
  32 VOID
  33 DECLSPEC_NORETURN
  34 (*PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY)(
  35     IN PKTRAP_FRAME TrapFrame
  36 );
  37
  38 #define HAL_APC_REQUEST         0
  39 #define HAL_DPC_REQUEST         1
  40
  41 /* CMOS Registers and Ports */
  42 #define CMOS_CONTROL_PORT       (PUCHAR)0x70
  43 #define CMOS_DATA_PORT          (PUCHAR)0x71
  44 #define RTC_REGISTER_A          0x0A
  45 #define RTC_REGISTER_B          0x0B
  46 #define RTC_REG_A_UIP           0x80
  47 #define RTC_REGISTER_CENTURY    0x32
  48
  49 /* Usage flags */
  50 #define IDT_REGISTERED          0x01
  51 #define IDT_LATCHED             0x02
  52 #define IDT_INTERNAL            0x11
  53 #define IDT_DEVICE              0x21
  54
  55 /* Conversion functions */
  56 #define BCD_INT(bcd)            \
  57     (((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F))
  58 #define INT_BCD(int)            \
  59     (UCHAR)(((int / 10) << 4) + (int % 10))
  60
  61 //
  62 // BIOS Interrupts
  63 //
  64 #define VIDEO_SERVICES   0x10
  65
  66 //
  67 // Operations for INT 10h (in AH)
  68 //
  69 #define SET_VIDEO_MODE   0x00
  70
  71 //
  72 // Video Modes for INT10h AH=00 (in AL)
  73 //
  74 #define GRAPHICS_MODE_12 0x12           /* 80x30         8x16  640x480   16/256K */
  75
  76 //
  77 // Commonly stated as being 1.19318MHz
  78 //
  79 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
  80 // P. 471
  81 //
  82 // However, the true value is closer to 1.19318181[...]81MHz since this is 1/3rd
  83 // of the NTSC color subcarrier frequency which runs at 3.57954545[...]45MHz.
  84 //
  85 // Note that Windows uses 1.193167MHz which seems to have no basis. However, if
  86 // one takes the NTSC color subcarrier frequency as being 3.579545 (trimming the
  87 // infinite series) and divides it by three, one obtains 1.19318167.
  88 //
  89 // It may be that the original NT HAL source code introduced a typo and turned
  90 // 119318167 into 1193167 by ommitting the "18". This is very plausible as the
  91 // number is quite long.
  92 //
  93 #define PIT_FREQUENCY 1193182
  94
  95 //
  96 // These ports are controlled by the i8254 Programmable Interrupt Timer (PIT)
  97 //
  98 #define TIMER_CHANNEL0_DATA_PORT 0x40
  99 #define TIMER_CHANNEL1_DATA_PORT 0x41
 100 #define TIMER_CHANNEL2_DATA_PORT 0x42
 101 #define TIMER_CONTROL_PORT       0x43
 102
 103 //
 104 // Mode 0 - Interrupt On Terminal Count
 105 // Mode 1 - Hardware Re-triggerable One-Shot
 106 // Mode 2 - Rate Generator
 107 // Mode 3 - Square Wave Generator
 108 // Mode 4 - Software Triggered Strobe
 109 // Mode 5 - Hardware Triggered Strobe
 110 //
 111 typedef enum _TIMER_OPERATING_MODES
 112 {
 113     PitOperatingMode0,
 114     PitOperatingMode1,
 115     PitOperatingMode2,
 116     PitOperatingMode3,
 117     PitOperatingMode4,
 118     PitOperatingMode5,
 119     PitOperatingMode2Reserved,
 120     PitOperatingMode5Reserved
 121 } TIMER_OPERATING_MODES;
 122
 123 typedef enum _TIMER_ACCESS_MODES
 124 {
 125     PitAccessModeCounterLatch,
 126     PitAccessModeLow,
 127     PitAccessModeHigh,
 128     PitAccessModeLowHigh
 129 } TIMER_ACCESS_MODES;
 130
 131 typedef enum _TIMER_CHANNELS
 132 {
 133     PitChannel0,
 134     PitChannel1,
 135     PitChannel2,
 136     PitReadBack
 137 } TIMER_CHANNELS;
 138
 139 typedef union _TIMER_CONTROL_PORT_REGISTER
 140 {
 141     struct
 142     {
 143         UCHAR BcdMode:1;
 144         TIMER_OPERATING_MODES OperatingMode:3;
 145         TIMER_ACCESS_MODES AccessMode:2;
 146         TIMER_CHANNELS Channel:2;
 147     };
 148     UCHAR Bits;
 149 } TIMER_CONTROL_PORT_REGISTER, *PTIMER_CONTROL_PORT_REGISTER;
 150
 151 //
 152 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 153 // P. 400
 154 //
 155 // This port is controled by the i8255 Programmable Peripheral Interface (PPI)
 156 //
 157 #define SYSTEM_CONTROL_PORT_A   0x92
 158 #define SYSTEM_CONTROL_PORT_B   0x61
 159 typedef union _SYSTEM_CONTROL_PORT_B_REGISTER
 160 {
 161     struct
 162     {
 163         UCHAR Timer2GateToSpeaker:1;
 164         UCHAR SpeakerDataEnable:1;
 165         UCHAR ParityCheckEnable:1;
 166         UCHAR ChannelCheckEnable:1;
 167         UCHAR RefreshRequest:1;
 168         UCHAR Timer2Output:1;
 169         UCHAR ChannelCheck:1;
 170         UCHAR ParityCheck:1;
 171     };
 172     UCHAR Bits;
 173 } SYSTEM_CONTROL_PORT_B_REGISTER, *PSYSTEM_CONTROL_PORT_B_REGISTER;
 174
 175 //
 176 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 177 // P. 396, 397
 178 //
 179 // These ports are controlled by the i8259 Programmable Interrupt Controller (PIC)
 180 //
 181 #define PIC1_CONTROL_PORT      0x20
 182 #define PIC1_DATA_PORT         0x21
 183 #define PIC2_CONTROL_PORT      0xA0
 184 #define PIC2_DATA_PORT         0xA1
 185
 186 //
 187 // Definitions for ICW/OCW Bits
 188 //
 189 typedef enum _I8259_ICW1_OPERATING_MODE
 190 {
 191     Cascade,
 192     Single
 193 } I8259_ICW1_OPERATING_MODE;
 194
 195 typedef enum _I8259_ICW1_INTERRUPT_MODE
 196 {
 197     EdgeTriggered,
 198     LevelTriggered
 199 } I8259_ICW1_INTERRUPT_MODE;
 200
 201 typedef enum _I8259_ICW1_INTERVAL
 202 {
 203     Interval8,
 204     Interval4
 205 } I8259_ICW1_INTERVAL;
 206
 207 typedef enum _I8259_ICW4_SYSTEM_MODE
 208 {
 209     Mcs8085Mode,
 210     New8086Mode
 211 } I8259_ICW4_SYSTEM_MODE;
 212
 213 typedef enum _I8259_ICW4_EOI_MODE
 214 {
 215     NormalEoi,
 216     AutomaticEoi
 217 } I8259_ICW4_EOI_MODE;
 218
 219 typedef enum _I8259_ICW4_BUFFERED_MODE
 220 {
 221     NonBuffered,
 222     NonBuffered2,
 223     BufferedSlave,
 224     BufferedMaster
 225 } I8259_ICW4_BUFFERED_MODE;
 226
 227 typedef enum _I8259_READ_REQUEST
 228 {
 229     InvalidRequest,
 230     InvalidRequest2,
 231     ReadIdr,
 232     ReadIsr
 233 } I8259_READ_REQUEST;
 234
 235 typedef enum _I8259_EOI_MODE
 236 {
 237     RotateAutoEoiClear,
 238     NonSpecificEoi,
 239     InvalidEoiMode,
 240     SpecificEoi,
 241     RotateAutoEoiSet,
 242     RotateNonSpecific,
 243     SetPriority,
 244     RotateSpecific
 245 } I8259_EOI_MODE;
 246
 247 //
 248 // Definitions for ICW Registers
 249 //
 250 typedef union _I8259_ICW1
 251 {
 252     struct
 253     {
 254         UCHAR NeedIcw4:1;
 255         I8259_ICW1_OPERATING_MODE OperatingMode:1;
 256         I8259_ICW1_INTERVAL Interval:1;
 257         I8259_ICW1_INTERRUPT_MODE InterruptMode:1;
 258         UCHAR Init:1;
 259         UCHAR InterruptVectorAddress:3;
 260     };
 261     UCHAR Bits;
 262 } I8259_ICW1, *PI8259_ICW1;
 263
 264 typedef union _I8259_ICW2
 265 {
 266     struct
 267     {
 268         UCHAR Sbz:3;
 269         UCHAR InterruptVector:5;
 270     };
 271     UCHAR Bits;
 272 } I8259_ICW2, *PI8259_ICW2;
 273
 274 typedef union _I8259_ICW3
 275 {
 276     union
 277     {
 278         struct
 279         {
 280             UCHAR SlaveIrq0:1;
 281             UCHAR SlaveIrq1:1;
 282             UCHAR SlaveIrq2:1;
 283             UCHAR SlaveIrq3:1;
 284             UCHAR SlaveIrq4:1;
 285             UCHAR SlaveIrq5:1;
 286             UCHAR SlaveIrq6:1;
 287             UCHAR SlaveIrq7:1;
 288         };
 289         struct
 290         {
 291             UCHAR SlaveId:3;
 292             UCHAR Reserved:5;
 293         };
 294     };
 295     UCHAR Bits;
 296 } I8259_ICW3, *PI8259_ICW3;
 297
 298 typedef union _I8259_ICW4
 299 {
 300     struct
 301     {
 302         I8259_ICW4_SYSTEM_MODE SystemMode:1;
 303         I8259_ICW4_EOI_MODE EoiMode:1;
 304         I8259_ICW4_BUFFERED_MODE BufferedMode:2;
 305         UCHAR SpecialFullyNestedMode:1;
 306         UCHAR Reserved:3;
 307     };
 308     UCHAR Bits;
 309 } I8259_ICW4, *PI8259_ICW4;
 310
 311 typedef union _I8259_OCW2
 312 {
 313     struct
 314     {
 315         UCHAR IrqNumber:3;
 316         UCHAR Sbz:2;
 317         I8259_EOI_MODE EoiMode:3;
 318     };
 319     UCHAR Bits;
 320 } I8259_OCW2, *PI8259_OCW2;
 321
 322 typedef union _I8259_OCW3
 323 {
 324     struct
 325     {
 326         I8259_READ_REQUEST ReadRequest:2;
 327         UCHAR PollCommand:1;
 328         UCHAR Sbo:1;
 329         UCHAR Sbz:1;
 330         UCHAR SpecialMaskMode:2;
 331         UCHAR Reserved:1;
 332     };
 333     UCHAR Bits;
 334 } I8259_OCW3, *PI8259_OCW3;
 335
 336 typedef union _I8259_ISR
 337 {
 338     union
 339     {
 340         struct
 341         {
 342             UCHAR Irq0:1;
 343             UCHAR Irq1:1;
 344             UCHAR Irq2:1;
 345             UCHAR Irq3:1;
 346             UCHAR Irq4:1;
 347             UCHAR Irq5:1;
 348             UCHAR Irq6:1;
 349             UCHAR Irq7:1;
 350         };
 351     };
 352     UCHAR Bits;
 353 } I8259_ISR, *PI8259_ISR;
 354
 355 typedef I8259_ISR I8259_IDR, *PI8259_IDR;
 356
 357 //
 358 // See EISA System Architecture 2nd Edition (Tom Shanley, Don Anderson, John Swindle)
 359 // P. 34, 35
 360 //
 361 // These ports are controlled by the i8259A Programmable Interrupt Controller (PIC)
 362 //
 363 #define EISA_ELCR_MASTER       0x4D0
 364 #define EISA_ELCR_SLAVE        0x4D1
 365
 366 typedef union _EISA_ELCR
 367 {
 368     struct
 369     {
 370         struct
 371         {
 372             UCHAR Irq0Level:1;
 373             UCHAR Irq1Level:1;
 374             UCHAR Irq2Level:1;
 375             UCHAR Irq3Level:1;
 376             UCHAR Irq4Level:1;
 377             UCHAR Irq5Level:1;
 378             UCHAR Irq6Level:1;
 379             UCHAR Irq7Level:1;
 380         } Master;
 381         struct
 382         {
 383             UCHAR Irq8Level:1;
 384             UCHAR Irq9Level:1;
 385             UCHAR Irq10Level:1;
 386             UCHAR Irq11Level:1;
 387             UCHAR Irq12Level:1;
 388             UCHAR Irq13Level:1;
 389             UCHAR Irq14Level:1;
 390             UCHAR Irq15Level:1;
 391         } Slave;
 392     };
 393     USHORT Bits;
 394 } EISA_ELCR, *PEISA_ELCR;
 395
 396 typedef struct _PIC_MASK
 397 {
 398     union
 399     {
 400         struct
 401         {
 402             UCHAR Master;
 403             UCHAR Slave;
 404         };
 405         USHORT Both;
 406     };
 407 } PIC_MASK, *PPIC_MASK;
 408
 409 typedef
 410 BOOLEAN
 411 __attribute__((regparm(3)))
 412 (*PHAL_DISMISS_INTERRUPT)(
 413     IN KIRQL Irql,
 414     IN ULONG Irq,
 415     OUT PKIRQL OldIrql
 416 );
 417
 418 BOOLEAN
 419 __attribute__((regparm(3)))
 420 HalpDismissIrqGeneric(
 421     IN KIRQL Irql,
 422     IN ULONG Irq,
 423     OUT PKIRQL OldIrql
 424 );
 425
 426 BOOLEAN
 427 __attribute__((regparm(3)))
 428 HalpDismissIrq15(
 429     IN KIRQL Irql,
 430     IN ULONG Irq,
 431     OUT PKIRQL OldIrql
 432 );
 433
 434 BOOLEAN
 435 __attribute__((regparm(3)))
 436 HalpDismissIrq13(
 437     IN KIRQL Irql,
 438     IN ULONG Irq,
 439     OUT PKIRQL OldIrql
 440 );
 441
 442 BOOLEAN
 443 __attribute__((regparm(3)))
 444 HalpDismissIrq07(
 445     IN KIRQL Irql,
 446     IN ULONG Irq,
 447     OUT PKIRQL OldIrql
 448 );
 449
 450 BOOLEAN
 451 __attribute__((regparm(3)))
 452 HalpDismissIrqLevel(
 453     IN KIRQL Irql,
 454     IN ULONG Irq,
 455     OUT PKIRQL OldIrql
 456 );
 457
 458 BOOLEAN
 459 __attribute__((regparm(3)))
 460 HalpDismissIrq15Level(
 461     IN KIRQL Irql,
 462     IN ULONG Irq,
 463     OUT PKIRQL OldIrql
 464 );
 465
 466 BOOLEAN
 467 __attribute__((regparm(3)))
 468 HalpDismissIrq13Level(
 469     IN KIRQL Irql,
 470     IN ULONG Irq,
 471     OUT PKIRQL OldIrql
 472 );
 473
 474 BOOLEAN
 475 __attribute__((regparm(3)))
 476 HalpDismissIrq07Level(
 477     IN KIRQL Irql,
 478     IN ULONG Irq,
 479     OUT PKIRQL OldIrql
 480 );
 481
 482 VOID
 483 HalpHardwareInterruptLevel(
 484     VOID
 485 );
 486
 487 //
 488 // Mm PTE/PDE to Hal PTE/PDE
 489 //
 490 #define HalAddressToPde(x) (PHARDWARE_PTE)MiAddressToPde(x)
 491 #define HalAddressToPte(x) (PHARDWARE_PTE)MiAddressToPte(x)
 492
 493 typedef struct _IDTUsageFlags
 494 {
 495     UCHAR Flags;
 496 } IDTUsageFlags;
 497
 498 typedef struct
 499 {
 500     KIRQL Irql;
 501     UCHAR BusReleativeVector;
 502 } IDTUsage;
 503
 504 typedef struct _HalAddressUsage
 505 {
 506     struct _HalAddressUsage *Next;
 507     CM_RESOURCE_TYPE Type;
 508     UCHAR Flags;
 509     struct
 510     {
 511         ULONG Start;
 512         ULONG Length;
 513     } Element[];
 514 } ADDRESS_USAGE, *PADDRESS_USAGE;
 515
 516 /* adapter.c */
 517 PADAPTER_OBJECT NTAPI HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
 518
 519 /* sysinfo.c */
 520 VOID
 521 NTAPI
 522 HalpRegisterVector(IN UCHAR Flags,
 523                    IN ULONG BusVector,
 524                    IN ULONG SystemVector,
 525                    IN KIRQL Irql);
 526
 527 VOID
 528 NTAPI
 529 HalpEnableInterruptHandler(IN UCHAR Flags,
 530                            IN ULONG BusVector,
 531                            IN ULONG SystemVector,
 532                            IN KIRQL Irql,
 533                            IN PVOID Handler,
 534                            IN KINTERRUPT_MODE Mode);
 535
 536 /* pic.c */
 537 VOID NTAPI HalpInitializePICs(IN BOOLEAN EnableInterrupts);
 538 VOID HalpApcInterrupt(VOID);
 539 VOID HalpDispatchInterrupt(VOID);
 540 VOID HalpDispatchInterrupt2(VOID);
 541 VOID FASTCALL DECLSPEC_NORETURN HalpApcInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
 542 VOID FASTCALL DECLSPEC_NORETURN HalpDispatchInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
 543
 544 /* timer.c */
 545 VOID NTAPI HalpInitializeClock(VOID);
 546 VOID HalpClockInterrupt(VOID);
 547 VOID HalpProfileInterrupt(VOID);
 548
 549 VOID
 550 NTAPI
 551 HalpCalibrateStallExecution(VOID);
 552
 553 /* pci.c */
 554 VOID HalpInitPciBus (VOID);
 555
 556 /* dma.c */
 557 VOID HalpInitDma (VOID);
 558
 559 /* Non-generic initialization */
 560 VOID HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock);
 561 VOID HalpInitPhase1(VOID);
 562
 563 VOID
 564 NTAPI
 565 HalpFlushTLB(VOID);
 566
 567 //
 568 // KD Support
 569 //
 570 VOID
 571 NTAPI
 572 HalpCheckPowerButton(
 573     VOID
 574 );
 575
 576 VOID
 577 NTAPI
 578 HalpRegisterKdSupportFunctions(
 579     VOID
 580 );
 581
 582 NTSTATUS
 583 NTAPI
 584 HalpSetupPciDeviceForDebugging(
 585     IN PVOID LoaderBlock,
 586     IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
 587 );
 588
 589 NTSTATUS
 590 NTAPI
 591 HalpReleasePciDeviceForDebugging(
 592     IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
 593 );
 594
 595 //
 596 // Memory routines
 597 //
 598 PVOID
 599 NTAPI
 600 HalpMapPhysicalMemory64(
 601     IN PHYSICAL_ADDRESS PhysicalAddress,
 602     IN ULONG NumberPage
 603 );
 604
 605 VOID
 606 NTAPI
 607 HalpUnmapVirtualAddress(
 608     IN PVOID VirtualAddress,
 609     IN ULONG NumberPages
 610 );
 611
 612 /* sysinfo.c */
 613 NTSTATUS
 614 NTAPI
 615 HaliQuerySystemInformation(
 616     IN HAL_QUERY_INFORMATION_CLASS InformationClass,
 617     IN ULONG BufferSize,
 618     IN OUT PVOID Buffer,
 619     OUT PULONG ReturnedLength
 620 );
 621
 622 NTSTATUS
 623 NTAPI
 624 HaliSetSystemInformation(
 625     IN HAL_SET_INFORMATION_CLASS InformationClass,
 626     IN ULONG BufferSize,
 627     IN OUT PVOID Buffer
 628 );
 629
 630 //
 631 // BIOS Routines
 632 //
 633 BOOLEAN
 634 NTAPI
 635 HalpBiosDisplayReset(
 636     VOID
 637 );
 638
 639 VOID
 640 FASTCALL
 641 HalpExitToV86(
 642     PKTRAP_FRAME TrapFrame
 643 );
 644
 645 VOID
 646 DECLSPEC_NORETURN
 647 HalpRealModeStart(
 648     VOID
 649 );
 650
 651 //
 652 // Processor Halt Routine
 653 //
 654 VOID
 655 NTAPI
 656 HaliHaltSystem(
 657     VOID
 658 );
 659
 660 //
 661 // CMOS initialization
 662 //
 663 VOID
 664 NTAPI
 665 HalpInitializeCmos(
 666     VOID
 667 );
 668
 669 //
 670 // Spinlock for protecting CMOS access
 671 //
 672 VOID
 673 NTAPI
 674 HalpAcquireSystemHardwareSpinLock(
 675     VOID
 676 );
 677
 678 VOID
 679 NTAPI
 680 HalpReleaseCmosSpinLock(
 681     VOID
 682 );
 683
 684 ULONG
 685 NTAPI
 686 HalpAllocPhysicalMemory(
 687     IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 688     IN ULONG MaxAddress,
 689     IN ULONG PageCount,
 690     IN BOOLEAN Aligned
 691 );
 692
 693 PVOID
 694 NTAPI
 695 HalpMapPhysicalMemory64(
 696     IN PHYSICAL_ADDRESS PhysicalAddress,
 697     IN ULONG PageCount
 698 );
 699
 700 VOID
 701 FASTCALL
 702 KeUpdateSystemTime(
 703     IN PKTRAP_FRAME TrapFrame,
 704     IN ULONG Increment,
 705     IN KIRQL OldIrql
 706 );
 707
 708 #ifdef _M_AMD64
 709 #define KfLowerIrql KeLowerIrql
 710 #ifndef CONFIG_SMP
 711 /* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
 712 #define KiAcquireSpinLock(SpinLock)
 713 #define KiReleaseSpinLock(SpinLock)
 714 #define KfAcquireSpinLock(SpinLock) KfRaiseIrql(DISPATCH_LEVEL);
 715 #define KfReleaseSpinLock(SpinLock, OldIrql) KeLowerIrql(OldIrql);
 716 #endif // !CONFIG_SMP
 717 #endif // _M_AMD64
 718
 719 extern BOOLEAN HalpNMIInProgress;
 720
 721 extern ADDRESS_USAGE HalpDefaultIoSpace;
 722
 723 extern KSPIN_LOCK HalpSystemHardwareLock;
 724
 725 extern PADDRESS_USAGE HalpAddressUsageList;
 726
 727 extern LARGE_INTEGER HalpPerfCounter;