reactos/hal/halx86/include/halp.h

   1 /*
   2  *
   3  */
   4
   5 #pragma once
   6
   7 #if defined(__GNUC__) && !defined(_MINIHAL_)
   8 #define INIT_SECTION __attribute__((section ("INIT")))
   9 #else
  10 #define INIT_SECTION /* Done via alloc_text for MSC */
  11 #endif
  12
  13
  14 #ifdef _MSC_VER
  15 #define REGISTERCALL FASTCALL
  16 #else
  17 #define REGISTERCALL __attribute__((regparm(3)))
  18 #endif
  19
  20 #ifdef CONFIG_SMP
  21 #define HAL_BUILD_TYPE (DBG ? PRCB_BUILD_DEBUG : 0)
  22 #else
  23 #define HAL_BUILD_TYPE ((DBG ? PRCB_BUILD_DEBUG : 0) | PRCB_BUILD_UNIPROCESSOR)
  24 #endif
  25
  26 typedef struct _HAL_BIOS_FRAME
  27 {
  28     ULONG SegSs;
  29     ULONG Esp;
  30     ULONG EFlags;
  31     ULONG SegCs;
  32     ULONG Eip;
  33     PKTRAP_FRAME TrapFrame;
  34     ULONG CsLimit;
  35     ULONG CsBase;
  36     ULONG CsFlags;
  37     ULONG SsLimit;
  38     ULONG SsBase;
  39     ULONG SsFlags;
  40     ULONG Prefix;
  41 } HAL_BIOS_FRAME, *PHAL_BIOS_FRAME;
  42
  43 typedef
  44 VOID
  45 (*PHAL_SW_INTERRUPT_HANDLER)(
  46     VOID
  47 );
  48
  49 typedef
  50 VOID
  51 ATTRIB_NORETURN
  52 (FASTCALL *PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY)(
  53     IN PKTRAP_FRAME TrapFrame
  54 );
  55
  56 #define HAL_APC_REQUEST         0
  57 #define HAL_DPC_REQUEST         1
  58
  59 /* CMOS Registers and Ports */
  60 #define CMOS_CONTROL_PORT       (PUCHAR)0x70
  61 #define CMOS_DATA_PORT          (PUCHAR)0x71
  62 #define RTC_REGISTER_A          0x0A
  63 #define   RTC_REG_A_UIP         0x80
  64 #define RTC_REGISTER_B          0x0B
  65 #define   RTC_REG_B_PI          0x40
  66 #define RTC_REGISTER_C          0x0C
  67 #define   RTC_REG_C_IRQ         0x80
  68 #define RTC_REGISTER_D          0x0D
  69 #define RTC_REGISTER_CENTURY    0x32
  70
  71 /* Usage flags */
  72 #define IDT_REGISTERED          0x01
  73 #define IDT_LATCHED             0x02
  74 #define IDT_READ_ONLY           0x04
  75 #define IDT_INTERNAL            0x11
  76 #define IDT_DEVICE              0x21
  77
  78 /* Conversion functions */
  79 #define BCD_INT(bcd)            \
  80     (((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F))
  81 #define INT_BCD(int)            \
  82     (UCHAR)(((int / 10) << 4) + (int % 10))
  83
  84 //
  85 // BIOS Interrupts
  86 //
  87 #define VIDEO_SERVICES   0x10
  88
  89 //
  90 // Operations for INT 10h (in AH)
  91 //
  92 #define SET_VIDEO_MODE   0x00
  93
  94 //
  95 // Video Modes for INT10h AH=00 (in AL)
  96 //
  97 #define GRAPHICS_MODE_12 0x12           /* 80x30         8x16  640x480   16/256K */
  98
  99 //
 100 // Commonly stated as being 1.19318MHz
 101 //
 102 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 103 // P. 471
 104 //
 105 // However, the true value is closer to 1.19318181[...]81MHz since this is 1/3rd
 106 // of the NTSC color subcarrier frequency which runs at 3.57954545[...]45MHz.
 107 //
 108 // Note that Windows uses 1.193167MHz which seems to have no basis. However, if
 109 // one takes the NTSC color subcarrier frequency as being 3.579545 (trimming the
 110 // infinite series) and divides it by three, one obtains 1.19318167.
 111 //
 112 // It may be that the original NT HAL source code introduced a typo and turned
 113 // 119318167 into 1193167 by ommitting the "18". This is very plausible as the
 114 // number is quite long.
 115 //
 116 #define PIT_FREQUENCY 1193182
 117
 118 //
 119 // These ports are controlled by the i8254 Programmable Interrupt Timer (PIT)
 120 //
 121 #define TIMER_CHANNEL0_DATA_PORT 0x40
 122 #define TIMER_CHANNEL1_DATA_PORT 0x41
 123 #define TIMER_CHANNEL2_DATA_PORT 0x42
 124 #define TIMER_CONTROL_PORT       0x43
 125
 126 //
 127 // Mode 0 - Interrupt On Terminal Count
 128 // Mode 1 - Hardware Re-triggerable One-Shot
 129 // Mode 2 - Rate Generator
 130 // Mode 3 - Square Wave Generator
 131 // Mode 4 - Software Triggered Strobe
 132 // Mode 5 - Hardware Triggered Strobe
 133 //
 134 typedef enum _TIMER_OPERATING_MODES
 135 {
 136     PitOperatingMode0,
 137     PitOperatingMode1,
 138     PitOperatingMode2,
 139     PitOperatingMode3,
 140     PitOperatingMode4,
 141     PitOperatingMode5,
 142     PitOperatingMode2Reserved,
 143     PitOperatingMode5Reserved
 144 } TIMER_OPERATING_MODES;
 145
 146 typedef enum _TIMER_ACCESS_MODES
 147 {
 148     PitAccessModeCounterLatch,
 149     PitAccessModeLow,
 150     PitAccessModeHigh,
 151     PitAccessModeLowHigh
 152 } TIMER_ACCESS_MODES;
 153
 154 typedef enum _TIMER_CHANNELS
 155 {
 156     PitChannel0,
 157     PitChannel1,
 158     PitChannel2,
 159     PitReadBack
 160 } TIMER_CHANNELS;
 161
 162 typedef union _TIMER_CONTROL_PORT_REGISTER
 163 {
 164     struct
 165     {
 166         UCHAR BcdMode:1;
 167         UCHAR OperatingMode:3;
 168         UCHAR AccessMode:2;
 169         UCHAR Channel:2;
 170     };
 171     UCHAR Bits;
 172 } TIMER_CONTROL_PORT_REGISTER, *PTIMER_CONTROL_PORT_REGISTER;
 173
 174 //
 175 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 176 // P. 400
 177 //
 178 // This port is controled by the i8255 Programmable Peripheral Interface (PPI)
 179 //
 180 #define SYSTEM_CONTROL_PORT_A   0x92
 181 #define SYSTEM_CONTROL_PORT_B   0x61
 182 typedef union _SYSTEM_CONTROL_PORT_B_REGISTER
 183 {
 184     struct
 185     {
 186         UCHAR Timer2GateToSpeaker:1;
 187         UCHAR SpeakerDataEnable:1;
 188         UCHAR ParityCheckEnable:1;
 189         UCHAR ChannelCheckEnable:1;
 190         UCHAR RefreshRequest:1;
 191         UCHAR Timer2Output:1;
 192         UCHAR ChannelCheck:1;
 193         UCHAR ParityCheck:1;
 194     };
 195     UCHAR Bits;
 196 } SYSTEM_CONTROL_PORT_B_REGISTER, *PSYSTEM_CONTROL_PORT_B_REGISTER;
 197
 198 //
 199 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 200 // P. 396, 397
 201 //
 202 // These ports are controlled by the i8259 Programmable Interrupt Controller (PIC)
 203 //
 204 #define PIC1_CONTROL_PORT      0x20
 205 #define PIC1_DATA_PORT         0x21
 206 #define PIC2_CONTROL_PORT      0xA0
 207 #define PIC2_DATA_PORT         0xA1
 208
 209 //
 210 // Definitions for ICW/OCW Bits
 211 //
 212 typedef enum _I8259_ICW1_OPERATING_MODE
 213 {
 214     Cascade,
 215     Single
 216 } I8259_ICW1_OPERATING_MODE;
 217
 218 typedef enum _I8259_ICW1_INTERRUPT_MODE
 219 {
 220     EdgeTriggered,
 221     LevelTriggered
 222 } I8259_ICW1_INTERRUPT_MODE;
 223
 224 typedef enum _I8259_ICW1_INTERVAL
 225 {
 226     Interval8,
 227     Interval4
 228 } I8259_ICW1_INTERVAL;
 229
 230 typedef enum _I8259_ICW4_SYSTEM_MODE
 231 {
 232     Mcs8085Mode,
 233     New8086Mode
 234 } I8259_ICW4_SYSTEM_MODE;
 235
 236 typedef enum _I8259_ICW4_EOI_MODE
 237 {
 238     NormalEoi,
 239     AutomaticEoi
 240 } I8259_ICW4_EOI_MODE;
 241
 242 typedef enum _I8259_ICW4_BUFFERED_MODE
 243 {
 244     NonBuffered,
 245     NonBuffered2,
 246     BufferedSlave,
 247     BufferedMaster
 248 } I8259_ICW4_BUFFERED_MODE;
 249
 250 typedef enum _I8259_READ_REQUEST
 251 {
 252     InvalidRequest,
 253     InvalidRequest2,
 254     ReadIdr,
 255     ReadIsr
 256 } I8259_READ_REQUEST;
 257
 258 typedef enum _I8259_EOI_MODE
 259 {
 260     RotateAutoEoiClear,
 261     NonSpecificEoi,
 262     InvalidEoiMode,
 263     SpecificEoi,
 264     RotateAutoEoiSet,
 265     RotateNonSpecific,
 266     SetPriority,
 267     RotateSpecific
 268 } I8259_EOI_MODE;
 269
 270 //
 271 // Definitions for ICW Registers
 272 //
 273 typedef union _I8259_ICW1
 274 {
 275     struct
 276     {
 277         UCHAR NeedIcw4:1;
 278         UCHAR OperatingMode:1;
 279         UCHAR Interval:1;
 280         UCHAR InterruptMode:1;
 281         UCHAR Init:1;
 282         UCHAR InterruptVectorAddress:3;
 283     };
 284     UCHAR Bits;
 285 } I8259_ICW1, *PI8259_ICW1;
 286
 287 typedef union _I8259_ICW2
 288 {
 289     struct
 290     {
 291         UCHAR Sbz:3;
 292         UCHAR InterruptVector:5;
 293     };
 294     UCHAR Bits;
 295 } I8259_ICW2, *PI8259_ICW2;
 296
 297 typedef union _I8259_ICW3
 298 {
 299     union
 300     {
 301         struct
 302         {
 303             UCHAR SlaveIrq0:1;
 304             UCHAR SlaveIrq1:1;
 305             UCHAR SlaveIrq2:1;
 306             UCHAR SlaveIrq3:1;
 307             UCHAR SlaveIrq4:1;
 308             UCHAR SlaveIrq5:1;
 309             UCHAR SlaveIrq6:1;
 310             UCHAR SlaveIrq7:1;
 311         };
 312         struct
 313         {
 314             UCHAR SlaveId:3;
 315             UCHAR Reserved:5;
 316         };
 317     };
 318     UCHAR Bits;
 319 } I8259_ICW3, *PI8259_ICW3;
 320
 321 typedef union _I8259_ICW4
 322 {
 323     struct
 324     {
 325         UCHAR SystemMode:1;
 326         UCHAR EoiMode:1;
 327         UCHAR BufferedMode:2;
 328         UCHAR SpecialFullyNestedMode:1;
 329         UCHAR Reserved:3;
 330     };
 331     UCHAR Bits;
 332 } I8259_ICW4, *PI8259_ICW4;
 333
 334 typedef union _I8259_OCW2
 335 {
 336     struct
 337     {
 338         UCHAR IrqNumber:3;
 339         UCHAR Sbz:2;
 340         UCHAR EoiMode:3;
 341     };
 342     UCHAR Bits;
 343 } I8259_OCW2, *PI8259_OCW2;
 344
 345 typedef union _I8259_OCW3
 346 {
 347     struct
 348     {
 349         UCHAR ReadRequest:2;
 350         UCHAR PollCommand:1;
 351         UCHAR Sbo:1;
 352         UCHAR Sbz:1;
 353         UCHAR SpecialMaskMode:2;
 354         UCHAR Reserved:1;
 355     };
 356     UCHAR Bits;
 357 } I8259_OCW3, *PI8259_OCW3;
 358
 359 typedef union _I8259_ISR
 360 {
 361     union
 362     {
 363         struct
 364         {
 365             UCHAR Irq0:1;
 366             UCHAR Irq1:1;
 367             UCHAR Irq2:1;
 368             UCHAR Irq3:1;
 369             UCHAR Irq4:1;
 370             UCHAR Irq5:1;
 371             UCHAR Irq6:1;
 372             UCHAR Irq7:1;
 373         };
 374     };
 375     UCHAR Bits;
 376 } I8259_ISR, *PI8259_ISR;
 377
 378 typedef I8259_ISR I8259_IDR, *PI8259_IDR;
 379
 380 //
 381 // See EISA System Architecture 2nd Edition (Tom Shanley, Don Anderson, John Swindle)
 382 // P. 34, 35
 383 //
 384 // These ports are controlled by the i8259A Programmable Interrupt Controller (PIC)
 385 //
 386 #define EISA_ELCR_MASTER       0x4D0
 387 #define EISA_ELCR_SLAVE        0x4D1
 388
 389 typedef union _EISA_ELCR
 390 {
 391     struct
 392     {
 393         struct
 394         {
 395             UCHAR Irq0Level:1;
 396             UCHAR Irq1Level:1;
 397             UCHAR Irq2Level:1;
 398             UCHAR Irq3Level:1;
 399             UCHAR Irq4Level:1;
 400             UCHAR Irq5Level:1;
 401             UCHAR Irq6Level:1;
 402             UCHAR Irq7Level:1;
 403         } Master;
 404         struct
 405         {
 406             UCHAR Irq8Level:1;
 407             UCHAR Irq9Level:1;
 408             UCHAR Irq10Level:1;
 409             UCHAR Irq11Level:1;
 410             UCHAR Irq12Level:1;
 411             UCHAR Irq13Level:1;
 412             UCHAR Irq14Level:1;
 413             UCHAR Irq15Level:1;
 414         } Slave;
 415     };
 416     USHORT Bits;
 417 } EISA_ELCR, *PEISA_ELCR;
 418
 419 typedef struct _PIC_MASK
 420 {
 421     union
 422     {
 423         struct
 424         {
 425             UCHAR Master;
 426             UCHAR Slave;
 427         };
 428         USHORT Both;
 429     };
 430 } PIC_MASK, *PPIC_MASK;
 431
 432 typedef
 433 BOOLEAN
 434 ( REGISTERCALL *PHAL_DISMISS_INTERRUPT)(
 435     IN KIRQL Irql,
 436     IN ULONG Irq,
 437     OUT PKIRQL OldIrql
 438 );
 439
 440 BOOLEAN
 441 REGISTERCALL
 442 HalpDismissIrqGeneric(
 443     IN KIRQL Irql,
 444     IN ULONG Irq,
 445     OUT PKIRQL OldIrql
 446 );
 447
 448 BOOLEAN
 449 REGISTERCALL
 450 HalpDismissIrq15(
 451     IN KIRQL Irql,
 452     IN ULONG Irq,
 453     OUT PKIRQL OldIrql
 454 );
 455
 456 BOOLEAN
 457 REGISTERCALL
 458 HalpDismissIrq13(
 459     IN KIRQL Irql,
 460     IN ULONG Irq,
 461     OUT PKIRQL OldIrql
 462 );
 463
 464 BOOLEAN
 465 REGISTERCALL
 466 HalpDismissIrq07(
 467     IN KIRQL Irql,
 468     IN ULONG Irq,
 469     OUT PKIRQL OldIrql
 470 );
 471
 472 BOOLEAN
 473 REGISTERCALL
 474 HalpDismissIrqLevel(
 475     IN KIRQL Irql,
 476     IN ULONG Irq,
 477     OUT PKIRQL OldIrql
 478 );
 479
 480 BOOLEAN
 481 REGISTERCALL
 482 HalpDismissIrq15Level(
 483     IN KIRQL Irql,
 484     IN ULONG Irq,
 485     OUT PKIRQL OldIrql
 486 );
 487
 488 BOOLEAN
 489 REGISTERCALL
 490 HalpDismissIrq13Level(
 491     IN KIRQL Irql,
 492     IN ULONG Irq,
 493     OUT PKIRQL OldIrql
 494 );
 495
 496 BOOLEAN
 497 REGISTERCALL
 498 HalpDismissIrq07Level(
 499     IN KIRQL Irql,
 500     IN ULONG Irq,
 501     OUT PKIRQL OldIrql
 502 );
 503
 504 VOID
 505 HalpHardwareInterruptLevel(
 506     VOID
 507 );
 508
 509 //
 510 // Hack Flags
 511 //
 512 #define HALP_REVISION_FROM_HACK_FLAGS(x)    ((x) >> 24)
 513 #define HALP_REVISION_HACK_FLAGS(x)         ((x) >> 12)
 514 #define HALP_HACK_FLAGS(x)                  ((x) & 0xFFF)
 515
 516 //
 517 // Feature flags
 518 //
 519 #define HALP_CARD_FEATURE_FULL_DECODE   0x0001
 520
 521 //
 522 // Match Flags
 523 //
 524 #define HALP_CHECK_CARD_REVISION_ID     0x10000
 525 #define HALP_CHECK_CARD_SUBVENDOR_ID    0x20000
 526 #define HALP_CHECK_CARD_SUBSYSTEM_ID    0x40000
 527
 528 //
 529 // Mm PTE/PDE to Hal PTE/PDE
 530 //
 531 #define HalAddressToPde(x) (PHARDWARE_PTE)MiAddressToPde(x)
 532 #define HalAddressToPte(x) (PHARDWARE_PTE)MiAddressToPte(x)
 533
 534 typedef struct _IDTUsageFlags
 535 {
 536     UCHAR Flags;
 537 } IDTUsageFlags;
 538
 539 typedef struct
 540 {
 541     KIRQL Irql;
 542     UCHAR BusReleativeVector;
 543 } IDTUsage;
 544
 545 typedef struct _HalAddressUsage
 546 {
 547     struct _HalAddressUsage *Next;
 548     CM_RESOURCE_TYPE Type;
 549     UCHAR Flags;
 550     struct
 551     {
 552         ULONG Start;
 553         ULONG Length;
 554     } Element[];
 555 } ADDRESS_USAGE, *PADDRESS_USAGE;
 556
 557 /* adapter.c */
 558 PADAPTER_OBJECT NTAPI HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
 559
 560 /* sysinfo.c */
 561 VOID
 562 NTAPI
 563 HalpRegisterVector(IN UCHAR Flags,
 564                    IN ULONG BusVector,
 565                    IN ULONG SystemVector,
 566                    IN KIRQL Irql);
 567
 568 VOID
 569 NTAPI
 570 HalpEnableInterruptHandler(IN UCHAR Flags,
 571                            IN ULONG BusVector,
 572                            IN ULONG SystemVector,
 573                            IN KIRQL Irql,
 574                            IN PVOID Handler,
 575                            IN KINTERRUPT_MODE Mode);
 576
 577 /* pic.c */
 578 VOID NTAPI HalpInitializePICs(IN BOOLEAN EnableInterrupts);
 579 VOID HalpApcInterrupt(VOID);
 580 VOID HalpDispatchInterrupt(VOID);
 581 VOID HalpDispatchInterrupt2(VOID);
 582 DECLSPEC_NORETURN VOID FASTCALL HalpApcInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
 583 DECLSPEC_NORETURN VOID FASTCALL HalpDispatchInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
 584
 585 /* profil.c */
 586 extern BOOLEAN HalpProfilingStopped;
 587
 588 /* timer.c */
 589 VOID NTAPI HalpInitializeClock(VOID);
 590 VOID HalpClockInterrupt(VOID);
 591 VOID HalpProfileInterrupt(VOID);
 592
 593 VOID
 594 NTAPI
 595 HalpCalibrateStallExecution(VOID);
 596
 597 /* pci.c */
 598 VOID HalpInitPciBus (VOID);
 599
 600 /* dma.c */
 601 VOID HalpInitDma (VOID);
 602
 603 /* Non-generic initialization */
 604 VOID HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock);
 605 VOID HalpInitPhase1(VOID);
 606
 607 VOID
 608 NTAPI
 609 HalpFlushTLB(VOID);
 610
 611 //
 612 // KD Support
 613 //
 614 VOID
 615 NTAPI
 616 HalpCheckPowerButton(
 617     VOID
 618 );
 619
 620 VOID
 621 NTAPI
 622 HalpRegisterKdSupportFunctions(
 623     VOID
 624 );
 625
 626 NTSTATUS
 627 NTAPI
 628 HalpSetupPciDeviceForDebugging(
 629     IN PVOID LoaderBlock,
 630     IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
 631 );
 632
 633 NTSTATUS
 634 NTAPI
 635 HalpReleasePciDeviceForDebugging(
 636     IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
 637 );
 638
 639 //
 640 // Memory routines
 641 //
 642 ULONG_PTR
 643 NTAPI
 644 HalpAllocPhysicalMemory(
 645     IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 646     IN ULONG_PTR MaxAddress,
 647     IN PFN_NUMBER PageCount,
 648     IN BOOLEAN Aligned
 649 );
 650
 651 PVOID
 652 NTAPI
 653 HalpMapPhysicalMemory64(
 654     IN PHYSICAL_ADDRESS PhysicalAddress,
 655     IN PFN_COUNT PageCount
 656 );
 657
 658 VOID
 659 NTAPI
 660 HalpUnmapVirtualAddress(
 661     IN PVOID VirtualAddress,
 662     IN PFN_COUNT NumberPages
 663 );
 664
 665 /* sysinfo.c */
 666 NTSTATUS
 667 NTAPI
 668 HaliQuerySystemInformation(
 669     IN HAL_QUERY_INFORMATION_CLASS InformationClass,
 670     IN ULONG BufferSize,
 671     IN OUT PVOID Buffer,
 672     OUT PULONG ReturnedLength
 673 );
 674
 675 NTSTATUS
 676 NTAPI
 677 HaliSetSystemInformation(
 678     IN HAL_SET_INFORMATION_CLASS InformationClass,
 679     IN ULONG BufferSize,
 680     IN OUT PVOID Buffer
 681 );
 682
 683 //
 684 // BIOS Routines
 685 //
 686 BOOLEAN
 687 NTAPI
 688 HalpBiosDisplayReset(
 689     VOID
 690 );
 691
 692 VOID
 693 FASTCALL
 694 HalpExitToV86(
 695     PKTRAP_FRAME TrapFrame
 696 );
 697
 698 VOID
 699 DECLSPEC_NORETURN
 700 HalpRealModeStart(
 701     VOID
 702 );
 703
 704 //
 705 // Processor Halt Routine
 706 //
 707 VOID
 708 NTAPI
 709 HaliHaltSystem(
 710     VOID
 711 );
 712
 713 //
 714 // CMOS Routines
 715 //
 716 VOID
 717 NTAPI
 718 HalpInitializeCmos(
 719     VOID
 720 );
 721
 722 UCHAR
 723 NTAPI
 724 HalpReadCmos(
 725     IN UCHAR Reg
 726 );
 727
 728 VOID
 729 NTAPI
 730 HalpWriteCmos(
 731     IN UCHAR Reg,
 732     IN UCHAR Value
 733 );
 734
 735 //
 736 // Spinlock for protecting CMOS access
 737 //
 738 VOID
 739 NTAPI
 740 HalpAcquireCmosSpinLock(
 741     VOID
 742 );
 743
 744 VOID
 745 NTAPI
 746 HalpReleaseCmosSpinLock(
 747     VOID
 748 );
 749
 750 NTSTATUS
 751 NTAPI
 752 HalpOpenRegistryKey(
 753     IN PHANDLE KeyHandle,
 754     IN HANDLE RootKey,
 755     IN PUNICODE_STRING KeyName,
 756     IN ACCESS_MASK DesiredAccess,
 757     IN BOOLEAN Create
 758 );
 759
 760 VOID
 761 NTAPI
 762 HalpGetNMICrashFlag(
 763     VOID
 764 );
 765
 766 BOOLEAN
 767 NTAPI
 768 HalpGetDebugPortTable(
 769     VOID
 770 );
 771
 772 VOID
 773 NTAPI
 774 HalpReportSerialNumber(
 775     VOID
 776 );
 777
 778 NTSTATUS
 779 NTAPI
 780 HalpMarkAcpiHal(
 781     VOID
 782 );
 783
 784 VOID
 785 NTAPI
 786 HalpBuildAddressMap(
 787     VOID
 788 );
 789
 790 VOID
 791 NTAPI
 792 HalpReportResourceUsage(
 793     IN PUNICODE_STRING HalName,
 794     IN INTERFACE_TYPE InterfaceType
 795 );
 796
 797 ULONG
 798 NTAPI
 799 HalpIs16BitPortDecodeSupported(
 800     VOID
 801 );
 802
 803 NTSTATUS
 804 NTAPI
 805 HalpQueryAcpiResourceRequirements(
 806     OUT PIO_RESOURCE_REQUIREMENTS_LIST *Requirements
 807 );
 808
 809 VOID
 810 FASTCALL
 811 KeUpdateSystemTime(
 812     IN PKTRAP_FRAME TrapFrame,
 813     IN ULONG Increment,
 814     IN KIRQL OldIrql
 815 );
 816
 817 VOID
 818 NTAPI
 819 HalpInitBusHandlers(
 820     VOID
 821 );
 822
 823 NTSTATUS
 824 NTAPI
 825 HaliInitPnpDriver(
 826     VOID
 827 );
 828
 829 VOID
 830 NTAPI
 831 HalpDebugPciDumpBus(
 832     IN ULONG i,
 833     IN ULONG j,
 834     IN ULONG k,
 835     IN PPCI_COMMON_CONFIG PciData
 836 );
 837
 838 VOID
 839 NTAPI
 840 HalpInitProcessor(
 841     IN ULONG ProcessorNumber,
 842     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 843 );
 844
 845 #ifdef _M_AMD64
 846 #define KfLowerIrql KeLowerIrql
 847 #define KiEnterInterruptTrap(TrapFrame) /* We do all neccessary in asm code */
 848 #define KiEoiHelper(TrapFrame) return /* Just return to the caller */
 849 #define HalBeginSystemInterrupt(Irql, Vector, OldIrql) ((*(OldIrql) = PASSIVE_LEVEL), TRUE)
 850 #ifndef CONFIG_SMP
 851 /* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
 852 #define KiAcquireSpinLock(SpinLock)
 853 #define KiReleaseSpinLock(SpinLock)
 854 #define KfAcquireSpinLock(SpinLock) KfRaiseIrql(DISPATCH_LEVEL);
 855 #define KfReleaseSpinLock(SpinLock, OldIrql) KeLowerIrql(OldIrql);
 856 #endif // !CONFIG_SMP
 857 #endif // _M_AMD64
 858
 859 extern BOOLEAN HalpNMIInProgress;
 860
 861 extern ADDRESS_USAGE HalpDefaultIoSpace;
 862
 863 extern KSPIN_LOCK HalpSystemHardwareLock;
 864
 865 extern PADDRESS_USAGE HalpAddressUsageList;
 866
 867 extern LARGE_INTEGER HalpPerfCounter;
 868
 869 extern KAFFINITY HalpActiveProcessors;
 870
 871 extern BOOLEAN HalDisableFirmwareMapper;
 872 extern PWCHAR HalHardwareIdString;
 873 extern PWCHAR HalName;
 874
 875 extern KAFFINITY HalpDefaultInterruptAffinity;
 876
 877 extern IDTUsageFlags HalpIDTUsageFlags[MAXIMUM_IDTVECTOR+1];
 878
 879 extern const USHORT HalpBuildType;