reactos/hal/halx86/include/halp.h

   1 /*
   2  *
   3  */
   4
   5 #pragma once
   6
   7 #define PLACE_IN_SECTION(s)     __attribute__((section (s)))
   8 #ifdef __GNUC__
   9 #define INIT_FUNCTION
  10 #define PAGE_LOCKED_FUNCTION    PLACE_IN_SECTION("pagelk")
  11 #define PAGE_UNLOCKED_FUNCTION  PLACE_IN_SECTION("pagepo")
  12 #else
  13 #define INIT_FUNCTION
  14 #define PAGE_LOCKED_FUNCTION
  15 #define PAGE_UNLOCKED_FUNCTION
  16 #endif
  17
  18 #ifdef _MSC_VER
  19 #define REGISTERCALL FASTCALL
  20 #else
  21 #define REGISTERCALL __attribute__((regparm(3)))
  22 #endif
  23
  24 #ifdef CONFIG_SMP
  25 #define HAL_BUILD_TYPE (DBG ? PRCB_BUILD_DEBUG : 0)
  26 #else
  27 #define HAL_BUILD_TYPE ((DBG ? PRCB_BUILD_DEBUG : 0) | PRCB_BUILD_UNIPROCESSOR)
  28 #endif
  29
  30 typedef struct _HAL_BIOS_FRAME
  31 {
  32     ULONG SegSs;
  33     ULONG Esp;
  34     ULONG EFlags;
  35     ULONG SegCs;
  36     ULONG Eip;
  37     PKTRAP_FRAME TrapFrame;
  38     ULONG CsLimit;
  39     ULONG CsBase;
  40     ULONG CsFlags;
  41     ULONG SsLimit;
  42     ULONG SsBase;
  43     ULONG SsFlags;
  44     ULONG Prefix;
  45 } HAL_BIOS_FRAME, *PHAL_BIOS_FRAME;
  46
  47 typedef
  48 VOID
  49 (*PHAL_SW_INTERRUPT_HANDLER)(
  50     VOID
  51 );
  52
  53 typedef
  54 VOID
  55 ATTRIB_NORETURN
  56 (FASTCALL *PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY)(
  57     IN PKTRAP_FRAME TrapFrame
  58 );
  59
  60 #define HAL_APC_REQUEST         0
  61 #define HAL_DPC_REQUEST         1
  62
  63 /* CMOS Registers and Ports */
  64 #define CMOS_CONTROL_PORT       (PUCHAR)0x70
  65 #define CMOS_DATA_PORT          (PUCHAR)0x71
  66 #define RTC_REGISTER_A          0x0A
  67 #define   RTC_REG_A_UIP         0x80
  68 #define RTC_REGISTER_B          0x0B
  69 #define   RTC_REG_B_PI          0x40
  70 #define RTC_REGISTER_C          0x0C
  71 #define   RTC_REG_C_IRQ         0x80
  72 #define RTC_REGISTER_D          0x0D
  73 #define RTC_REGISTER_CENTURY    0x32
  74
  75 /* Usage flags */
  76 #define IDT_REGISTERED          0x01
  77 #define IDT_LATCHED             0x02
  78 #define IDT_READ_ONLY           0x04
  79 #define IDT_INTERNAL            0x11
  80 #define IDT_DEVICE              0x21
  81
  82 /* Conversion functions */
  83 #define BCD_INT(bcd)            \
  84     (((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F))
  85 #define INT_BCD(int)            \
  86     (UCHAR)(((int / 10) << 4) + (int % 10))
  87
  88 //
  89 // BIOS Interrupts
  90 //
  91 #define VIDEO_SERVICES   0x10
  92
  93 //
  94 // Operations for INT 10h (in AH)
  95 //
  96 #define SET_VIDEO_MODE   0x00
  97
  98 //
  99 // Video Modes for INT10h AH=00 (in AL)
 100 //
 101 #define GRAPHICS_MODE_12 0x12           /* 80x30         8x16  640x480   16/256K */
 102
 103 //
 104 // Commonly stated as being 1.19318MHz
 105 //
 106 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 107 // P. 471
 108 //
 109 // However, the true value is closer to 1.19318181[...]81MHz since this is 1/3rd
 110 // of the NTSC color subcarrier frequency which runs at 3.57954545[...]45MHz.
 111 //
 112 // Note that Windows uses 1.193167MHz which seems to have no basis. However, if
 113 // one takes the NTSC color subcarrier frequency as being 3.579545 (trimming the
 114 // infinite series) and divides it by three, one obtains 1.19318167.
 115 //
 116 // It may be that the original NT HAL source code introduced a typo and turned
 117 // 119318167 into 1193167 by ommitting the "18". This is very plausible as the
 118 // number is quite long.
 119 //
 120 #define PIT_FREQUENCY 1193182
 121
 122 //
 123 // These ports are controlled by the i8254 Programmable Interrupt Timer (PIT)
 124 //
 125 #define TIMER_CHANNEL0_DATA_PORT 0x40
 126 #define TIMER_CHANNEL1_DATA_PORT 0x41
 127 #define TIMER_CHANNEL2_DATA_PORT 0x42
 128 #define TIMER_CONTROL_PORT       0x43
 129
 130 //
 131 // Mode 0 - Interrupt On Terminal Count
 132 // Mode 1 - Hardware Re-triggerable One-Shot
 133 // Mode 2 - Rate Generator
 134 // Mode 3 - Square Wave Generator
 135 // Mode 4 - Software Triggered Strobe
 136 // Mode 5 - Hardware Triggered Strobe
 137 //
 138 typedef enum _TIMER_OPERATING_MODES
 139 {
 140     PitOperatingMode0,
 141     PitOperatingMode1,
 142     PitOperatingMode2,
 143     PitOperatingMode3,
 144     PitOperatingMode4,
 145     PitOperatingMode5,
 146     PitOperatingMode2Reserved,
 147     PitOperatingMode5Reserved
 148 } TIMER_OPERATING_MODES;
 149
 150 typedef enum _TIMER_ACCESS_MODES
 151 {
 152     PitAccessModeCounterLatch,
 153     PitAccessModeLow,
 154     PitAccessModeHigh,
 155     PitAccessModeLowHigh
 156 } TIMER_ACCESS_MODES;
 157
 158 typedef enum _TIMER_CHANNELS
 159 {
 160     PitChannel0,
 161     PitChannel1,
 162     PitChannel2,
 163     PitReadBack
 164 } TIMER_CHANNELS;
 165
 166 typedef union _TIMER_CONTROL_PORT_REGISTER
 167 {
 168     struct
 169     {
 170         UCHAR BcdMode:1;
 171         UCHAR OperatingMode:3;
 172         UCHAR AccessMode:2;
 173         UCHAR Channel:2;
 174     };
 175     UCHAR Bits;
 176 } TIMER_CONTROL_PORT_REGISTER, *PTIMER_CONTROL_PORT_REGISTER;
 177
 178 //
 179 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 180 // P. 400
 181 //
 182 // This port is controled by the i8255 Programmable Peripheral Interface (PPI)
 183 //
 184 #define SYSTEM_CONTROL_PORT_A   0x92
 185 #define SYSTEM_CONTROL_PORT_B   0x61
 186 typedef union _SYSTEM_CONTROL_PORT_B_REGISTER
 187 {
 188     struct
 189     {
 190         UCHAR Timer2GateToSpeaker:1;
 191         UCHAR SpeakerDataEnable:1;
 192         UCHAR ParityCheckEnable:1;
 193         UCHAR ChannelCheckEnable:1;
 194         UCHAR RefreshRequest:1;
 195         UCHAR Timer2Output:1;
 196         UCHAR ChannelCheck:1;
 197         UCHAR ParityCheck:1;
 198     };
 199     UCHAR Bits;
 200 } SYSTEM_CONTROL_PORT_B_REGISTER, *PSYSTEM_CONTROL_PORT_B_REGISTER;
 201
 202 //
 203 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 204 // P. 396, 397
 205 //
 206 // These ports are controlled by the i8259 Programmable Interrupt Controller (PIC)
 207 //
 208 #define PIC1_CONTROL_PORT      0x20
 209 #define PIC1_DATA_PORT         0x21
 210 #define PIC2_CONTROL_PORT      0xA0
 211 #define PIC2_DATA_PORT         0xA1
 212
 213 //
 214 // Definitions for ICW/OCW Bits
 215 //
 216 typedef enum _I8259_ICW1_OPERATING_MODE
 217 {
 218     Cascade,
 219     Single
 220 } I8259_ICW1_OPERATING_MODE;
 221
 222 typedef enum _I8259_ICW1_INTERRUPT_MODE
 223 {
 224     EdgeTriggered,
 225     LevelTriggered
 226 } I8259_ICW1_INTERRUPT_MODE;
 227
 228 typedef enum _I8259_ICW1_INTERVAL
 229 {
 230     Interval8,
 231     Interval4
 232 } I8259_ICW1_INTERVAL;
 233
 234 typedef enum _I8259_ICW4_SYSTEM_MODE
 235 {
 236     Mcs8085Mode,
 237     New8086Mode
 238 } I8259_ICW4_SYSTEM_MODE;
 239
 240 typedef enum _I8259_ICW4_EOI_MODE
 241 {
 242     NormalEoi,
 243     AutomaticEoi
 244 } I8259_ICW4_EOI_MODE;
 245
 246 typedef enum _I8259_ICW4_BUFFERED_MODE
 247 {
 248     NonBuffered,
 249     NonBuffered2,
 250     BufferedSlave,
 251     BufferedMaster
 252 } I8259_ICW4_BUFFERED_MODE;
 253
 254 typedef enum _I8259_READ_REQUEST
 255 {
 256     InvalidRequest,
 257     InvalidRequest2,
 258     ReadIdr,
 259     ReadIsr
 260 } I8259_READ_REQUEST;
 261
 262 typedef enum _I8259_EOI_MODE
 263 {
 264     RotateAutoEoiClear,
 265     NonSpecificEoi,
 266     InvalidEoiMode,
 267     SpecificEoi,
 268     RotateAutoEoiSet,
 269     RotateNonSpecific,
 270     SetPriority,
 271     RotateSpecific
 272 } I8259_EOI_MODE;
 273
 274 //
 275 // Definitions for ICW Registers
 276 //
 277 typedef union _I8259_ICW1
 278 {
 279     struct
 280     {
 281         UCHAR NeedIcw4:1;
 282         UCHAR OperatingMode:1;
 283         UCHAR Interval:1;
 284         UCHAR InterruptMode:1;
 285         UCHAR Init:1;
 286         UCHAR InterruptVectorAddress:3;
 287     };
 288     UCHAR Bits;
 289 } I8259_ICW1, *PI8259_ICW1;
 290
 291 typedef union _I8259_ICW2
 292 {
 293     struct
 294     {
 295         UCHAR Sbz:3;
 296         UCHAR InterruptVector:5;
 297     };
 298     UCHAR Bits;
 299 } I8259_ICW2, *PI8259_ICW2;
 300
 301 typedef union _I8259_ICW3
 302 {
 303     union
 304     {
 305         struct
 306         {
 307             UCHAR SlaveIrq0:1;
 308             UCHAR SlaveIrq1:1;
 309             UCHAR SlaveIrq2:1;
 310             UCHAR SlaveIrq3:1;
 311             UCHAR SlaveIrq4:1;
 312             UCHAR SlaveIrq5:1;
 313             UCHAR SlaveIrq6:1;
 314             UCHAR SlaveIrq7:1;
 315         };
 316         struct
 317         {
 318             UCHAR SlaveId:3;
 319             UCHAR Reserved:5;
 320         };
 321     };
 322     UCHAR Bits;
 323 } I8259_ICW3, *PI8259_ICW3;
 324
 325 typedef union _I8259_ICW4
 326 {
 327     struct
 328     {
 329         UCHAR SystemMode:1;
 330         UCHAR EoiMode:1;
 331         UCHAR BufferedMode:2;
 332         UCHAR SpecialFullyNestedMode:1;
 333         UCHAR Reserved:3;
 334     };
 335     UCHAR Bits;
 336 } I8259_ICW4, *PI8259_ICW4;
 337
 338 typedef union _I8259_OCW2
 339 {
 340     struct
 341     {
 342         UCHAR IrqNumber:3;
 343         UCHAR Sbz:2;
 344         UCHAR EoiMode:3;
 345     };
 346     UCHAR Bits;
 347 } I8259_OCW2, *PI8259_OCW2;
 348
 349 typedef union _I8259_OCW3
 350 {
 351     struct
 352     {
 353         UCHAR ReadRequest:2;
 354         UCHAR PollCommand:1;
 355         UCHAR Sbo:1;
 356         UCHAR Sbz:1;
 357         UCHAR SpecialMaskMode:2;
 358         UCHAR Reserved:1;
 359     };
 360     UCHAR Bits;
 361 } I8259_OCW3, *PI8259_OCW3;
 362
 363 typedef union _I8259_ISR
 364 {
 365     union
 366     {
 367         struct
 368         {
 369             UCHAR Irq0:1;
 370             UCHAR Irq1:1;
 371             UCHAR Irq2:1;
 372             UCHAR Irq3:1;
 373             UCHAR Irq4:1;
 374             UCHAR Irq5:1;
 375             UCHAR Irq6:1;
 376             UCHAR Irq7:1;
 377         };
 378     };
 379     UCHAR Bits;
 380 } I8259_ISR, *PI8259_ISR;
 381
 382 typedef I8259_ISR I8259_IDR, *PI8259_IDR;
 383
 384 //
 385 // See EISA System Architecture 2nd Edition (Tom Shanley, Don Anderson, John Swindle)
 386 // P. 34, 35
 387 //
 388 // These ports are controlled by the i8259A Programmable Interrupt Controller (PIC)
 389 //
 390 #define EISA_ELCR_MASTER       0x4D0
 391 #define EISA_ELCR_SLAVE        0x4D1
 392
 393 typedef union _EISA_ELCR
 394 {
 395     struct
 396     {
 397         struct
 398         {
 399             UCHAR Irq0Level:1;
 400             UCHAR Irq1Level:1;
 401             UCHAR Irq2Level:1;
 402             UCHAR Irq3Level:1;
 403             UCHAR Irq4Level:1;
 404             UCHAR Irq5Level:1;
 405             UCHAR Irq6Level:1;
 406             UCHAR Irq7Level:1;
 407         } Master;
 408         struct
 409         {
 410             UCHAR Irq8Level:1;
 411             UCHAR Irq9Level:1;
 412             UCHAR Irq10Level:1;
 413             UCHAR Irq11Level:1;
 414             UCHAR Irq12Level:1;
 415             UCHAR Irq13Level:1;
 416             UCHAR Irq14Level:1;
 417             UCHAR Irq15Level:1;
 418         } Slave;
 419     };
 420     USHORT Bits;
 421 } EISA_ELCR, *PEISA_ELCR;
 422
 423 typedef struct _PIC_MASK
 424 {
 425     union
 426     {
 427         struct
 428         {
 429             UCHAR Master;
 430             UCHAR Slave;
 431         };
 432         USHORT Both;
 433     };
 434 } PIC_MASK, *PPIC_MASK;
 435
 436 typedef
 437 BOOLEAN
 438 ( REGISTERCALL *PHAL_DISMISS_INTERRUPT)(
 439     IN KIRQL Irql,
 440     IN ULONG Irq,
 441     OUT PKIRQL OldIrql
 442 );
 443
 444 BOOLEAN
 445 REGISTERCALL
 446 HalpDismissIrqGeneric(
 447     IN KIRQL Irql,
 448     IN ULONG Irq,
 449     OUT PKIRQL OldIrql
 450 );
 451
 452 BOOLEAN
 453 REGISTERCALL
 454 HalpDismissIrq15(
 455     IN KIRQL Irql,
 456     IN ULONG Irq,
 457     OUT PKIRQL OldIrql
 458 );
 459
 460 BOOLEAN
 461 REGISTERCALL
 462 HalpDismissIrq13(
 463     IN KIRQL Irql,
 464     IN ULONG Irq,
 465     OUT PKIRQL OldIrql
 466 );
 467
 468 BOOLEAN
 469 REGISTERCALL
 470 HalpDismissIrq07(
 471     IN KIRQL Irql,
 472     IN ULONG Irq,
 473     OUT PKIRQL OldIrql
 474 );
 475
 476 BOOLEAN
 477 REGISTERCALL
 478 HalpDismissIrqLevel(
 479     IN KIRQL Irql,
 480     IN ULONG Irq,
 481     OUT PKIRQL OldIrql
 482 );
 483
 484 BOOLEAN
 485 REGISTERCALL
 486 HalpDismissIrq15Level(
 487     IN KIRQL Irql,
 488     IN ULONG Irq,
 489     OUT PKIRQL OldIrql
 490 );
 491
 492 BOOLEAN
 493 REGISTERCALL
 494 HalpDismissIrq13Level(
 495     IN KIRQL Irql,
 496     IN ULONG Irq,
 497     OUT PKIRQL OldIrql
 498 );
 499
 500 BOOLEAN
 501 REGISTERCALL
 502 HalpDismissIrq07Level(
 503     IN KIRQL Irql,
 504     IN ULONG Irq,
 505     OUT PKIRQL OldIrql
 506 );
 507
 508 VOID
 509 HalpHardwareInterruptLevel(
 510     VOID
 511 );
 512
 513 //
 514 // Hack Flags
 515 //
 516 #define HALP_REVISION_FROM_HACK_FLAGS(x)    ((x) >> 24)
 517 #define HALP_REVISION_HACK_FLAGS(x)         ((x) >> 12)
 518 #define HALP_HACK_FLAGS(x)                  ((x) & 0xFFF)
 519
 520 //
 521 // Feature flags
 522 //
 523 #define HALP_CARD_FEATURE_FULL_DECODE   0x0001
 524
 525 //
 526 // Match Flags
 527 //
 528 #define HALP_CHECK_CARD_REVISION_ID     0x10000
 529 #define HALP_CHECK_CARD_SUBVENDOR_ID    0x20000
 530 #define HALP_CHECK_CARD_SUBSYSTEM_ID    0x40000
 531
 532 //
 533 // Mm PTE/PDE to Hal PTE/PDE
 534 //
 535 #define HalAddressToPde(x) (PHARDWARE_PTE)MiAddressToPde(x)
 536 #define HalAddressToPte(x) (PHARDWARE_PTE)MiAddressToPte(x)
 537
 538 typedef struct _IDTUsageFlags
 539 {
 540     UCHAR Flags;
 541 } IDTUsageFlags;
 542
 543 typedef struct
 544 {
 545     KIRQL Irql;
 546     UCHAR BusReleativeVector;
 547 } IDTUsage;
 548
 549 typedef struct _HalAddressUsage
 550 {
 551     struct _HalAddressUsage *Next;
 552     CM_RESOURCE_TYPE Type;
 553     UCHAR Flags;
 554     struct
 555     {
 556         ULONG Start;
 557         ULONG Length;
 558     } Element[];
 559 } ADDRESS_USAGE, *PADDRESS_USAGE;
 560
 561 /* adapter.c */
 562 PADAPTER_OBJECT NTAPI HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
 563
 564 /* sysinfo.c */
 565 VOID
 566 NTAPI
 567 HalpRegisterVector(IN UCHAR Flags,
 568                    IN ULONG BusVector,
 569                    IN ULONG SystemVector,
 570                    IN KIRQL Irql);
 571
 572 VOID
 573 NTAPI
 574 HalpEnableInterruptHandler(IN UCHAR Flags,
 575                            IN ULONG BusVector,
 576                            IN ULONG SystemVector,
 577                            IN KIRQL Irql,
 578                            IN PVOID Handler,
 579                            IN KINTERRUPT_MODE Mode);
 580
 581 /* pic.c */
 582 VOID NTAPI HalpInitializePICs(IN BOOLEAN EnableInterrupts);
 583 VOID HalpApcInterrupt(VOID);
 584 VOID HalpDispatchInterrupt(VOID);
 585 VOID HalpDispatchInterrupt2(VOID);
 586 DECLSPEC_NORETURN VOID FASTCALL HalpApcInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
 587 DECLSPEC_NORETURN VOID FASTCALL HalpDispatchInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
 588
 589 /* profil.c */
 590 extern BOOLEAN HalpProfilingStopped;
 591
 592 /* timer.c */
 593 VOID NTAPI HalpInitializeClock(VOID);
 594 VOID HalpClockInterrupt(VOID);
 595 VOID HalpProfileInterrupt(VOID);
 596
 597 VOID
 598 NTAPI
 599 HalpCalibrateStallExecution(VOID);
 600
 601 /* pci.c */
 602 VOID HalpInitPciBus (VOID);
 603
 604 /* dma.c */
 605 VOID HalpInitDma (VOID);
 606
 607 /* Non-generic initialization */
 608 VOID HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock);
 609 VOID HalpInitPhase1(VOID);
 610
 611 VOID
 612 NTAPI
 613 HalpFlushTLB(VOID);
 614
 615 //
 616 // KD Support
 617 //
 618 VOID
 619 NTAPI
 620 HalpCheckPowerButton(
 621     VOID
 622 );
 623
 624 VOID
 625 NTAPI
 626 HalpRegisterKdSupportFunctions(
 627     VOID
 628 );
 629
 630 NTSTATUS
 631 NTAPI
 632 HalpSetupPciDeviceForDebugging(
 633     IN PVOID LoaderBlock,
 634     IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
 635 );
 636
 637 NTSTATUS
 638 NTAPI
 639 HalpReleasePciDeviceForDebugging(
 640     IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
 641 );
 642
 643 //
 644 // Memory routines
 645 //
 646 ULONG_PTR
 647 NTAPI
 648 HalpAllocPhysicalMemory(
 649     IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 650     IN ULONG_PTR MaxAddress,
 651     IN PFN_NUMBER PageCount,
 652     IN BOOLEAN Aligned
 653 );
 654
 655 PVOID
 656 NTAPI
 657 HalpMapPhysicalMemory64(
 658     IN PHYSICAL_ADDRESS PhysicalAddress,
 659     IN PFN_COUNT PageCount
 660 );
 661
 662 VOID
 663 NTAPI
 664 HalpUnmapVirtualAddress(
 665     IN PVOID VirtualAddress,
 666     IN PFN_COUNT NumberPages
 667 );
 668
 669 /* sysinfo.c */
 670 NTSTATUS
 671 NTAPI
 672 HaliQuerySystemInformation(
 673     IN HAL_QUERY_INFORMATION_CLASS InformationClass,
 674     IN ULONG BufferSize,
 675     IN OUT PVOID Buffer,
 676     OUT PULONG ReturnedLength
 677 );
 678
 679 NTSTATUS
 680 NTAPI
 681 HaliSetSystemInformation(
 682     IN HAL_SET_INFORMATION_CLASS InformationClass,
 683     IN ULONG BufferSize,
 684     IN OUT PVOID Buffer
 685 );
 686
 687 //
 688 // BIOS Routines
 689 //
 690 BOOLEAN
 691 NTAPI
 692 HalpBiosDisplayReset(
 693     VOID
 694 );
 695
 696 VOID
 697 FASTCALL
 698 HalpExitToV86(
 699     PKTRAP_FRAME TrapFrame
 700 );
 701
 702 VOID
 703 DECLSPEC_NORETURN
 704 HalpRealModeStart(
 705     VOID
 706 );
 707
 708 //
 709 // Processor Halt Routine
 710 //
 711 VOID
 712 NTAPI
 713 HaliHaltSystem(
 714     VOID
 715 );
 716
 717 //
 718 // CMOS Routines
 719 //
 720 VOID
 721 NTAPI
 722 HalpInitializeCmos(
 723     VOID
 724 );
 725
 726 UCHAR
 727 NTAPI
 728 HalpReadCmos(
 729     IN UCHAR Reg
 730 );
 731
 732 VOID
 733 NTAPI
 734 HalpWriteCmos(
 735     IN UCHAR Reg,
 736     IN UCHAR Value
 737 );
 738
 739 //
 740 // Spinlock for protecting CMOS access
 741 //
 742 VOID
 743 NTAPI
 744 HalpAcquireCmosSpinLock(
 745     VOID
 746 );
 747
 748 VOID
 749 NTAPI
 750 HalpReleaseCmosSpinLock(
 751     VOID
 752 );
 753
 754 NTSTATUS
 755 NTAPI
 756 HalpOpenRegistryKey(
 757     IN PHANDLE KeyHandle,
 758     IN HANDLE RootKey,
 759     IN PUNICODE_STRING KeyName,
 760     IN ACCESS_MASK DesiredAccess,
 761     IN BOOLEAN Create
 762 );
 763
 764 VOID
 765 NTAPI
 766 HalpGetNMICrashFlag(
 767     VOID
 768 );
 769
 770 BOOLEAN
 771 NTAPI
 772 HalpGetDebugPortTable(
 773     VOID
 774 );
 775
 776 VOID
 777 NTAPI
 778 HalpReportSerialNumber(
 779     VOID
 780 );
 781
 782 NTSTATUS
 783 NTAPI
 784 HalpMarkAcpiHal(
 785     VOID
 786 );
 787
 788 VOID
 789 NTAPI
 790 HalpBuildAddressMap(
 791     VOID
 792 );
 793
 794 VOID
 795 NTAPI
 796 HalpReportResourceUsage(
 797     IN PUNICODE_STRING HalName,
 798     IN INTERFACE_TYPE InterfaceType
 799 );
 800
 801 ULONG
 802 NTAPI
 803 HalpIs16BitPortDecodeSupported(
 804     VOID
 805 );
 806
 807 NTSTATUS
 808 NTAPI
 809 HalpQueryAcpiResourceRequirements(
 810     OUT PIO_RESOURCE_REQUIREMENTS_LIST *Requirements
 811 );
 812
 813 VOID
 814 FASTCALL
 815 KeUpdateSystemTime(
 816     IN PKTRAP_FRAME TrapFrame,
 817     IN ULONG Increment,
 818     IN KIRQL OldIrql
 819 );
 820
 821 VOID
 822 NTAPI
 823 HalpInitBusHandlers(
 824     VOID
 825 );
 826
 827 NTSTATUS
 828 NTAPI
 829 HaliInitPnpDriver(
 830     VOID
 831 );
 832
 833 VOID
 834 NTAPI
 835 HalpDebugPciDumpBus(
 836     IN ULONG i,
 837     IN ULONG j,
 838     IN ULONG k,
 839     IN PPCI_COMMON_CONFIG PciData
 840 );
 841
 842 VOID
 843 NTAPI
 844 HalpInitProcessor(
 845     IN ULONG ProcessorNumber,
 846     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 847 );
 848
 849 #ifdef _M_AMD64
 850 #define KfLowerIrql KeLowerIrql
 851 #define KiEnterInterruptTrap(TrapFrame) /* We do all neccessary in asm code */
 852 #define KiEoiHelper(TrapFrame) return /* Just return to the caller */
 853 #define HalBeginSystemInterrupt(Irql, Vector, OldIrql) ((*(OldIrql) = PASSIVE_LEVEL), TRUE)
 854 #ifndef CONFIG_SMP
 855 /* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
 856 #define KiAcquireSpinLock(SpinLock)
 857 #define KiReleaseSpinLock(SpinLock)
 858 #define KfAcquireSpinLock(SpinLock) KfRaiseIrql(DISPATCH_LEVEL);
 859 #define KfReleaseSpinLock(SpinLock, OldIrql) KeLowerIrql(OldIrql);
 860 #endif // !CONFIG_SMP
 861 #endif // _M_AMD64
 862
 863 extern BOOLEAN HalpNMIInProgress;
 864
 865 extern ADDRESS_USAGE HalpDefaultIoSpace;
 866
 867 extern KSPIN_LOCK HalpSystemHardwareLock;
 868
 869 extern PADDRESS_USAGE HalpAddressUsageList;
 870
 871 extern LARGE_INTEGER HalpPerfCounter;
 872
 873 extern KAFFINITY HalpActiveProcessors;
 874
 875 extern BOOLEAN HalDisableFirmwareMapper;
 876 extern PWCHAR HalHardwareIdString;
 877 extern PWCHAR HalName;
 878
 879 extern KAFFINITY HalpDefaultInterruptAffinity;
 880
 881 extern IDTUsageFlags HalpIDTUsageFlags[MAXIMUM_IDTVECTOR+1];
 882
 883 extern const USHORT HalpBuildType;