5 #ifndef __INTERNAL_HAL_HAL_H
6 #define __INTERNAL_HAL_HAL_H
8 typedef struct _HAL_BIOS_FRAME
15 PKTRAP_FRAME TrapFrame
;
23 } HAL_BIOS_FRAME
, *PHAL_BIOS_FRAME
;
27 (*PHAL_SW_INTERRUPT_HANDLER
)(
35 (*PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY
)(
36 IN PKTRAP_FRAME TrapFrame
39 #define HAL_APC_REQUEST 0
40 #define HAL_DPC_REQUEST 1
42 /* CMOS Registers and Ports */
43 #define CMOS_CONTROL_PORT (PUCHAR)0x70
44 #define CMOS_DATA_PORT (PUCHAR)0x71
45 #define RTC_REGISTER_A 0x0A
46 #define RTC_REGISTER_B 0x0B
47 #define RTC_REG_A_UIP 0x80
48 #define RTC_REGISTER_CENTURY 0x32
51 #define IDT_REGISTERED 0x01
52 #define IDT_LATCHED 0x02
53 #define IDT_INTERNAL 0x11
54 #define IDT_DEVICE 0x21
56 /* Conversion functions */
57 #define BCD_INT(bcd) \
58 (((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F))
59 #define INT_BCD(int) \
60 (UCHAR)(((int / 10) << 4) + (int % 10))
65 #define VIDEO_SERVICES 0x10
68 // Operations for INT 10h (in AH)
70 #define SET_VIDEO_MODE 0x00
73 // Video Modes for INT10h AH=00 (in AL)
75 #define GRAPHICS_MODE_12 0x12 /* 80x30 8x16 640x480 16/256K */
78 // Generates a 16-bit (real-mode or Virtual 8086) BIOS interrupt with a given AX */
82 HalpCallBiosInterrupt(IN ULONG Interrupt
,
88 "movl $%c[v], %%eax\n"
97 // Constructs a stack of the given size and alignment in the real-mode .text region */
101 HalpRealModeStack(IN ULONG Alignment
,
108 ".globl _HalpRealModeEnd\n_HalpRealModeEnd:\n"
110 : [v
] "i"(Alignment
),
116 // Commonly stated as being 1.19318MHz
118 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
121 // However, the true value is closer to 1.19318181[...]81MHz since this is 1/3rd
122 // of the NTSC color subcarrier frequency which runs at 3.57954545[...]45MHz.
124 // Note that Windows uses 1.193167MHz which seems to have no basis. However, if
125 // one takes the NTSC color subcarrier frequency as being 3.579545 (trimming the
126 // infinite series) and divides it by three, one obtains 1.19318167.
128 // It may be that the original NT HAL source code introduced a typo and turned
129 // 119318167 into 1193167 by ommitting the "18". This is very plausible as the
130 // number is quite long.
132 #define PIT_FREQUENCY 1193182
135 // These ports are controlled by the i8254 Programmable Interrupt Timer (PIT)
137 #define TIMER_CHANNEL0_DATA_PORT 0x40
138 #define TIMER_CHANNEL1_DATA_PORT 0x41
139 #define TIMER_CHANNEL2_DATA_PORT 0x42
140 #define TIMER_CONTROL_PORT 0x43
143 // Mode 0 - Interrupt On Terminal Count
144 // Mode 1 - Hardware Re-triggerable One-Shot
145 // Mode 2 - Rate Generator
146 // Mode 3 - Square Wave Generator
147 // Mode 4 - Software Triggered Strobe
148 // Mode 5 - Hardware Triggered Strobe
150 typedef enum _TIMER_OPERATING_MODES
158 PitOperatingMode2Reserved
,
159 PitOperatingMode5Reserved
160 } TIMER_OPERATING_MODES
;
162 typedef enum _TIMER_ACCESS_MODES
164 PitAccessModeCounterLatch
,
168 } TIMER_ACCESS_MODES
;
170 typedef enum _TIMER_CHANNELS
178 typedef union _TIMER_CONTROL_PORT_REGISTER
183 TIMER_OPERATING_MODES OperatingMode
:3;
184 TIMER_ACCESS_MODES AccessMode
:2;
185 TIMER_CHANNELS Channel
:2;
188 } TIMER_CONTROL_PORT_REGISTER
, *PTIMER_CONTROL_PORT_REGISTER
;
191 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
194 // This port is controled by the i8255 Programmable Peripheral Interface (PPI)
196 #define SYSTEM_CONTROL_PORT_A 0x92
197 #define SYSTEM_CONTROL_PORT_B 0x61
198 typedef union _SYSTEM_CONTROL_PORT_B_REGISTER
202 UCHAR Timer2GateToSpeaker
:1;
203 UCHAR SpeakerDataEnable
:1;
204 UCHAR ParityCheckEnable
:1;
205 UCHAR ChannelCheckEnable
:1;
206 UCHAR RefreshRequest
:1;
207 UCHAR Timer2Output
:1;
208 UCHAR ChannelCheck
:1;
212 } SYSTEM_CONTROL_PORT_B_REGISTER
, *PSYSTEM_CONTROL_PORT_B_REGISTER
;
215 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
218 // These ports are controlled by the i8259 Programmable Interrupt Controller (PIC)
220 #define PIC1_CONTROL_PORT 0x20
221 #define PIC1_DATA_PORT 0x21
222 #define PIC2_CONTROL_PORT 0xA0
223 #define PIC2_DATA_PORT 0xA1
226 // Definitions for ICW/OCW Bits
228 typedef enum _I8259_ICW1_OPERATING_MODE
232 } I8259_ICW1_OPERATING_MODE
;
234 typedef enum _I8259_ICW1_INTERRUPT_MODE
238 } I8259_ICW1_INTERRUPT_MODE
;
240 typedef enum _I8259_ICW1_INTERVAL
244 } I8259_ICW1_INTERVAL
;
246 typedef enum _I8259_ICW4_SYSTEM_MODE
250 } I8259_ICW4_SYSTEM_MODE
;
252 typedef enum _I8259_ICW4_EOI_MODE
256 } I8259_ICW4_EOI_MODE
;
258 typedef enum _I8259_ICW4_BUFFERED_MODE
264 } I8259_ICW4_BUFFERED_MODE
;
266 typedef enum _I8259_READ_REQUEST
272 } I8259_READ_REQUEST
;
274 typedef enum _I8259_EOI_MODE
287 // Definitions for ICW Registers
289 typedef union _I8259_ICW1
294 I8259_ICW1_OPERATING_MODE OperatingMode
:1;
295 I8259_ICW1_INTERVAL Interval
:1;
296 I8259_ICW1_INTERRUPT_MODE InterruptMode
:1;
298 UCHAR InterruptVectorAddress
:3;
301 } I8259_ICW1
, *PI8259_ICW1
;
303 typedef union _I8259_ICW2
308 UCHAR InterruptVector
:5;
311 } I8259_ICW2
, *PI8259_ICW2
;
313 typedef union _I8259_ICW3
335 } I8259_ICW3
, *PI8259_ICW3
;
337 typedef union _I8259_ICW4
341 I8259_ICW4_SYSTEM_MODE SystemMode
:1;
342 I8259_ICW4_EOI_MODE EoiMode
:1;
343 I8259_ICW4_BUFFERED_MODE BufferedMode
:2;
344 UCHAR SpecialFullyNestedMode
:1;
348 } I8259_ICW4
, *PI8259_ICW4
;
350 typedef union _I8259_OCW2
356 I8259_EOI_MODE EoiMode
:3;
359 } I8259_OCW2
, *PI8259_OCW2
;
361 typedef union _I8259_OCW3
365 I8259_READ_REQUEST ReadRequest
:2;
369 UCHAR SpecialMaskMode
:2;
373 } I8259_OCW3
, *PI8259_OCW3
;
375 typedef union _I8259_ISR
392 } I8259_ISR
, *PI8259_ISR
;
394 typedef I8259_ISR I8259_IDR
, *PI8259_IDR
;
397 // See EISA System Architecture 2nd Edition (Tom Shanley, Don Anderson, John Swindle)
400 // These ports are controlled by the i8259A Programmable Interrupt Controller (PIC)
402 #define EISA_ELCR_MASTER 0x4D0
403 #define EISA_ELCR_SLAVE 0x4D1
405 typedef union _EISA_ELCR
433 } EISA_ELCR
, *PEISA_ELCR
;
435 typedef struct _PIC_MASK
446 } PIC_MASK
, *PPIC_MASK
;
450 __attribute__((regparm(3)))
451 (*PHAL_DISMISS_INTERRUPT
)(
458 __attribute__((regparm(3)))
459 HalpDismissIrqGeneric(
466 __attribute__((regparm(3)))
474 __attribute__((regparm(3)))
482 __attribute__((regparm(3)))
490 __attribute__((regparm(3)))
498 __attribute__((regparm(3)))
499 HalpDismissIrq15Level(
506 __attribute__((regparm(3)))
507 HalpDismissIrq13Level(
514 __attribute__((regparm(3)))
515 HalpDismissIrq07Level(
522 HalpHardwareInterruptLevel(
527 // Mm PTE/PDE to Hal PTE/PDE
529 #define HalAddressToPde(x) (PHARDWARE_PTE)MiAddressToPde(x)
530 #define HalAddressToPte(x) (PHARDWARE_PTE)MiAddressToPte(x)
532 typedef struct _IDTUsageFlags
540 UCHAR BusReleativeVector
;
543 typedef struct _HalAddressUsage
545 struct _HalAddressUsage
*Next
;
546 CM_RESOURCE_TYPE Type
;
553 } ADDRESS_USAGE
, *PADDRESS_USAGE
;
556 PADAPTER_OBJECT NTAPI
HalpAllocateAdapterEx(ULONG NumberOfMapRegisters
,BOOLEAN IsMaster
, BOOLEAN Dma32BitAddresses
);
561 HalpRegisterVector(IN UCHAR Flags
,
563 IN ULONG SystemVector
,
568 HalpEnableInterruptHandler(IN UCHAR Flags
,
570 IN ULONG SystemVector
,
573 IN KINTERRUPT_MODE Mode
);
576 VOID NTAPI
HalpInitializePICs(IN BOOLEAN EnableInterrupts
);
577 VOID
HalpApcInterrupt(VOID
);
578 VOID
HalpDispatchInterrupt(VOID
);
579 VOID
HalpDispatchInterrupt2(VOID
);
580 VOID FASTCALL DECLSPEC_NORETURN
HalpApcInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame
);
581 VOID FASTCALL DECLSPEC_NORETURN
HalpDispatchInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame
);
584 VOID NTAPI
HalpInitializeClock(VOID
);
585 VOID
HalpClockInterrupt(VOID
);
586 VOID
HalpProfileInterrupt(VOID
);
590 HalpCalibrateStallExecution(VOID
);
593 VOID
HalpInitPciBus (VOID
);
596 VOID
HalpInitDma (VOID
);
598 /* Non-generic initialization */
599 VOID
HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock
);
600 VOID
HalpInitPhase1(VOID
);
611 HalpCheckPowerButton(
617 HalpRegisterKdSupportFunctions(
623 HalpSetupPciDeviceForDebugging(
624 IN PVOID LoaderBlock
,
625 IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
630 HalpReleasePciDeviceForDebugging(
631 IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
639 HalpMapPhysicalMemory64(
640 IN PHYSICAL_ADDRESS PhysicalAddress
,
646 HalpUnmapVirtualAddress(
647 IN PVOID VirtualAddress
,
654 HaliQuerySystemInformation(
655 IN HAL_QUERY_INFORMATION_CLASS InformationClass
,
658 OUT PULONG ReturnedLength
663 HaliSetSystemInformation(
664 IN HAL_SET_INFORMATION_CLASS InformationClass
,
674 HalpBiosDisplayReset(
679 // Processor Halt Routine
688 // CMOS initialization
697 // Spinlock for protecting CMOS access
701 HalpAcquireSystemHardwareSpinLock(
707 HalpReleaseCmosSpinLock(
713 HalpSetInterruptGate(ULONG Index
, PVOID Address
);
716 #define KfLowerIrql KeLowerIrql
718 /* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
719 #define KiAcquireSpinLock(SpinLock)
720 #define KiReleaseSpinLock(SpinLock)
721 #define KfAcquireSpinLock(SpinLock) KfRaiseIrql(DISPATCH_LEVEL);
722 #define KfReleaseSpinLock(SpinLock, OldIrql) KeLowerIrql(OldIrql);
723 #endif // !CONFIG_SMP
726 extern BOOLEAN HalpNMIInProgress
;
728 extern ADDRESS_USAGE HalpDefaultIoSpace
;
730 extern KSPIN_LOCK HalpSystemHardwareLock
;
732 extern PADDRESS_USAGE HalpAddressUsageList
;
734 extern LARGE_INTEGER HalpPerfCounter
;
736 #endif /* __INTERNAL_HAL_HAL_H */