reactos/hal/halx86/include/halp.h

   1 /*
   2  *
   3  */
   4
   5 #ifndef __INTERNAL_HAL_HAL_H
   6 #define __INTERNAL_HAL_HAL_H
   7
   8 #define HAL_APC_REQUEST     0
   9 #define HAL_DPC_REQUEST     1
  10
  11 /* display.c */
  12 struct _LOADER_PARAMETER_BLOCK;
  13 VOID FASTCALL HalInitializeDisplay (struct _LOADER_PARAMETER_BLOCK *LoaderBlock);
  14 VOID FASTCALL HalClearDisplay (UCHAR CharAttribute);
  15
  16 /* adapter.c */
  17 PADAPTER_OBJECT STDCALL HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
  18
  19 /* bus.c */
  20 VOID HalpInitBusHandlers (VOID);
  21
  22 /* irql.c */
  23 VOID HalpInitPICs(VOID);
  24
  25 /* udelay.c */
  26 VOID HalpCalibrateStallExecution(VOID);
  27
  28 /* pci.c */
  29 VOID HalpInitPciBus (VOID);
  30
  31 /* enum.c */
  32 VOID HalpStartEnumerator (VOID);
  33
  34 /* dma.c */
  35 VOID HalpInitDma (VOID);
  36
  37 /* mem.c */
  38 PVOID HalpMapPhysMemory(ULONG PhysAddr, ULONG Size);
  39
  40 /* Non-generic initialization */
  41 VOID HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock);
  42
  43 /* DMA Page Register Structure
  44  080     DMA        RESERVED
  45  081     DMA        Page Register (channel 2)
  46  082     DMA        Page Register (channel 3)
  47  083     DMA        Page Register (channel 1)
  48  084     DMA        RESERVED
  49  085     DMA        RESERVED
  50  086     DMA        RESERVED
  51  087     DMA        Page Register (channel 0)
  52  088     DMA        RESERVED
  53  089     PS/2-DMA   Page Register (channel 6)
  54  08A     PS/2-DMA   Page Register (channel 7)
  55  08B     PS/2-DMA   Page Register (channel 5)
  56  08C     PS/2-DMA   RESERVED
  57  08D     PS/2-DMA   RESERVED
  58  08E     PS/2-DMA   RESERVED
  59  08F     PS/2-DMA   Page Register (channel 4)
  60 */
  61  typedef struct _DMA_PAGE{
  62   UCHAR Reserved1;
  63   UCHAR Channel2;
  64   UCHAR Channel3;
  65   UCHAR Channel1;
  66   UCHAR Reserved2[3];
  67   UCHAR Channel0;
  68   UCHAR Reserved3;
  69   UCHAR Channel6;
  70   UCHAR Channel7;
  71   UCHAR Channel5;
  72   UCHAR Reserved4[3];
  73   UCHAR Channel4;
  74 } DMA_PAGE, *PDMA_PAGE;
  75
  76 /* DMA Channel Mask Register Structure
  77
  78 MSB                             LSB
  79       x   x   x   x     x   x   x   x
  80       -------------------   -   -----
  81                |            |     |     00 - Select channel 0 mask bit
  82                |            |     \---- 01 - Select channel 1 mask bit
  83                |            |           10 - Select channel 2 mask bit
  84                |            |           11 - Select channel 3 mask bit
  85                |            |
  86                |            \----------  0 - Clear mask bit
  87                |                         1 - Set mask bit
  88                |
  89                \----------------------- xx - Reserved
  90 */
  91 typedef struct _DMA_CHANNEL_MASK {
  92   UCHAR Channel : 2;
  93   UCHAR SetMask : 1;
  94   UCHAR Reserved : 5;
  95 } DMA_CHANNEL_MASK, *PDMA_CHANNEL_MASK;
  96
  97 /* DMA Mask Register Structure
  98
  99    MSB                             LSB
 100       x   x   x   x     x   x   x   x
 101       \---/   -   -     -----   -----
 102         |     |   |       |       |     00 - Channel 0 select
 103         |     |   |       |       \---- 01 - Channel 1 select
 104         |     |   |       |             10 - Channel 2 select
 105         |     |   |       |             11 - Channel 3 select
 106         |     |   |       |
 107         |     |   |       |             00 - Verify transfer
 108         |     |   |       \------------ 01 - Write transfer
 109         |     |   |                     10 - Read transfer
 110         |     |   |
 111         |     |   \--------------------  0 - Autoinitialized
 112         |     |                          1 - Non-autoinitialized
 113         |     |
 114         |     \------------------------  0 - Address increment select
 115         |
 116         |                               00 - Demand mode
 117         \------------------------------ 01 - Single mode
 118                                         10 - Block mode
 119                                         11 - Cascade mode
 120 */
 121 typedef struct _DMA_MODE {
 122   UCHAR Channel : 2;
 123   UCHAR TransferType : 2;
 124   UCHAR AutoInitialize : 1;
 125   UCHAR AddressDecrement : 1;
 126   UCHAR RequestMode : 2;
 127 } DMA_MODE, *PDMA_MODE;
 128
 129
 130 /* DMA Extended Mode Register Structure
 131
 132    MSB                             LSB
 133       x   x   x   x     x   x   x   x
 134       -   -   -----     -----   -----
 135       |   |     |         |       |     00 - Channel 0 select
 136       |   |     |         |       \---- 01 - Channel 1 select
 137       |   |     |         |             10 - Channel 2 select
 138       |   |     |         |             11 - Channel 3 select
 139       |   |     |         |
 140       |   |     |         |             00 - 8-bit I/O, by bytes
 141       |   |     |         \------------ 01 - 16-bit I/O, by words, address shifted
 142       |   |     |                       10 - 32-bit I/O, by bytes
 143       |   |     |                       11 - 16-bit I/O, by bytes
 144       |   |     |
 145       |   |     \---------------------- 00 - Compatible
 146       |   |                             01 - Type A
 147       |   |                             10 - Type B
 148       |   |                             11 - Burst
 149       |   |
 150       |   \---------------------------- 0 - Terminal Count is Output
 151       |
 152       \---------------------------------0 - Disable Stop Register
 153                                         1 - Enable Stop Register
 154 */
 155 typedef struct _DMA_EXTENDED_MODE {
 156     UCHAR ChannelNumber : 2;
 157     UCHAR TransferSize : 2;
 158     UCHAR TimingMode : 2;
 159     UCHAR TerminalCountIsOutput : 1;
 160     UCHAR EnableStopRegister : 1;
 161 }DMA_EXTENDED_MODE, *PDMA_EXTENDED_MODE;
 162
 163 /* DMA Extended Mode Register Transfer Sizes */
 164 #define B_8BITS 0
 165 #define W_16BITS 1
 166 #define B_32BITS 2
 167 #define B_16BITS 3
 168
 169 /* DMA Extended Mode Register Timing */
 170 #define COMPATIBLE_TIMING 0
 171 #define TYPE_A_TIMING 1
 172 #define TYPE_B_TIMING 2
 173 #define BURST_TIMING 3
 174
 175 /* Channel Stop Registers for each Channel */
 176 typedef struct _DMA_CHANNEL_STOP {
 177   UCHAR ChannelLow;
 178   UCHAR ChannelMid;
 179   UCHAR ChannelHigh;
 180   UCHAR Reserved;
 181 } DMA_CHANNEL_STOP, *PDMA_CHANNEL_STOP;
 182
 183 /* Transfer Types */
 184 #define VERIFY_TRANSFER 0x00
 185 #define READ_TRANSFER 0x01
 186 #define WRITE_TRANSFER 0x02
 187
 188 /* Request Modes */
 189 #define DEMAND_REQUEST_MODE 0x00
 190 #define SINGLE_REQUEST_MODE 0x01
 191 #define BLOCK_REQUEST_MODE 0x02
 192 #define CASCADE_REQUEST_MODE 0x03
 193
 194 #define DMA_SETMASK 4
 195 #define DMA_CLEARMASK 0
 196 #define DMA_READ 4
 197 #define DMA_WRITE 8
 198 #define DMA_SINGLE_TRANSFER 0x40
 199 #define DMA_AUTO_INIT 0x10
 200
 201 typedef struct _DMA1_ADDRESS_COUNT {
 202    UCHAR DmaBaseAddress;
 203    UCHAR DmaBaseCount;
 204 } DMA1_ADDRESS_COUNT, *PDMA1_ADDRESS_COUNT;
 205
 206 typedef struct _DMA2_ADDRESS_COUNT {
 207    UCHAR DmaBaseAddress;
 208    UCHAR Reserved1;
 209    UCHAR DmaBaseCount;
 210    UCHAR Reserved2;
 211 } DMA2_ADDRESS_COUNT, *PDMA2_ADDRESS_COUNT;
 212
 213 typedef struct _DMA1_CONTROL {
 214    DMA1_ADDRESS_COUNT DmaAddressCount[4];
 215    UCHAR DmaStatus;
 216    UCHAR DmaRequest;
 217    UCHAR SingleMask;
 218    UCHAR Mode;
 219    UCHAR ClearBytePointer;
 220    UCHAR MasterClear;
 221    UCHAR ClearMask;
 222    UCHAR AllMask;
 223 } DMA1_CONTROL, *PDMA1_CONTROL;
 224
 225 typedef struct _DMA2_CONTROL {
 226    DMA2_ADDRESS_COUNT DmaAddressCount[4];
 227    UCHAR DmaStatus;
 228    UCHAR Reserved1;
 229    UCHAR DmaRequest;
 230    UCHAR Reserved2;
 231    UCHAR SingleMask;
 232    UCHAR Reserved3;
 233    UCHAR Mode;
 234    UCHAR Reserved4;
 235    UCHAR ClearBytePointer;
 236    UCHAR Reserved5;
 237    UCHAR MasterClear;
 238    UCHAR Reserved6;
 239    UCHAR ClearMask;
 240    UCHAR Reserved7;
 241    UCHAR AllMask;
 242    UCHAR Reserved8;
 243 } DMA2_CONTROL, *PDMA2_CONTROL;
 244
 245 /* This Structure Defines the I/O Map of the 82537 Controller
 246    I've only defined the registers which are likely to be useful to us */
 247 typedef struct _EISA_CONTROL {
 248    /* DMA Controller 1 */
 249    DMA1_CONTROL DmaController1;         /* 00h-0Fh */
 250    UCHAR Reserved1[16];                 /* 0Fh-1Fh */
 251
 252    /* Interrupt Controller 1 (PIC) */
 253    UCHAR Pic1Operation;                 /* 20h     */
 254    UCHAR Pic1Interrupt;                 /* 21h     */
 255    UCHAR Reserved2[30];                 /* 22h-3Fh */
 256
 257    /* Timer */
 258    UCHAR TimerCounter;                  /* 40h     */
 259    UCHAR TimerMemoryRefresh;            /* 41h     */
 260    UCHAR Speaker;                       /* 42h     */
 261    UCHAR TimerOperation;                /* 43h     */
 262    UCHAR TimerMisc;                     /* 44h     */
 263    UCHAR Reserved3[2];                  /* 45-46h  */
 264    UCHAR TimerCounterControl;           /* 47h     */
 265    UCHAR TimerFailSafeCounter;          /* 48h     */
 266    UCHAR Reserved4;                     /* 49h     */
 267    UCHAR TimerCounter2;                 /* 4Ah     */
 268    UCHAR TimerOperation2;               /* 4Bh     */
 269    UCHAR Reserved5[20];                 /* 4Ch-5Fh */
 270
 271    /* NMI / Keyboard / RTC */
 272    UCHAR Keyboard;                      /* 60h     */
 273    UCHAR NmiStatus;                     /* 61h     */
 274    UCHAR Reserved6[14];                 /* 62h-6Fh */
 275    UCHAR NmiEnable;                     /* 70h     */
 276    UCHAR Reserved7[15];                 /* 71h-7Fh */
 277
 278    /* DMA Page Registers Controller 1 */
 279    DMA_PAGE DmaController1Pages;        /* 80h-8Fh */
 280    UCHAR Reserved8[16];                 /* 90h-9Fh */
 281
 282     /* Interrupt Controller 2 (PIC) */
 283    UCHAR Pic2Operation;                 /* 0A0h      */
 284    UCHAR Pic2Interrupt;                 /* 0A1h      */
 285    UCHAR Reserved9[30];                 /* 0A2h-0BFh */
 286
 287    /* DMA Controller 2 */
 288    DMA1_CONTROL DmaController2;         /* 0C0h-0CFh */
 289
 290    /* System Reserved Ports */
 291    UCHAR SystemReserved[816];           /* 0D0h-3FFh */
 292
 293    /* Extended DMA Registers, Controller 1 */
 294    UCHAR DmaHighByteCount1[8];          /* 400h-407h */
 295    UCHAR Reserved10[2];                 /* 408h-409h */
 296    UCHAR DmaChainMode1;                 /* 40Ah      */
 297    UCHAR DmaExtendedMode1;              /* 40Bh      */
 298    UCHAR DmaBufferControl;              /* 40Ch      */
 299    UCHAR Reserved11[84];                /* 40Dh-460h */
 300    UCHAR ExtendedNmiControl;            /* 461h      */
 301    UCHAR NmiCommand;                    /* 462h      */
 302    UCHAR Reserved12;                    /* 463h      */
 303    UCHAR BusMaster;                     /* 464h      */
 304    UCHAR Reserved13[27];                /* 465h-47Fh */
 305
 306    /* DMA Page Registers Controller 2 */
 307    DMA_PAGE DmaController2Pages;        /* 480h-48Fh */
 308    UCHAR Reserved14[48];                /* 490h-4BFh */
 309
 310    /* Extended DMA Registers, Controller 2 */
 311    UCHAR DmaHighByteCount2[16];         /* 4C0h-4CFh */
 312
 313    /* Edge/Level Control Registers */
 314    UCHAR Pic1EdgeLevel;                 /* 4D0h      */
 315    UCHAR Pic2EdgeLevel;                 /* 4D1h      */
 316    UCHAR Reserved15[2];                 /* 4D2h-4D3h */
 317
 318    /* Extended DMA Registers, Controller 2 */
 319    UCHAR DmaChainMode2;                 /* 4D4h      */
 320    UCHAR Reserved16;                    /* 4D5h      */
 321    UCHAR DmaExtendedMode2;              /* 4D6h      */
 322    UCHAR Reserved17[9];                 /* 4D7h-4DFh */
 323
 324    /* DMA Stop Registers */
 325    DMA_CHANNEL_STOP DmaChannelStop[8];  /* 4E0h-4FFh */
 326 } EISA_CONTROL, *PEISA_CONTROL;
 327
 328 extern ULONG HalpEisaDma;
 329 extern PADAPTER_OBJECT MasterAdapter;
 330
 331 ULONG HalpEisaDma;
 332 PADAPTER_OBJECT MasterAdapter;
 333
 334 /*
 335  * ADAPTER_OBJECT - Track a busmaster DMA adapter and its associated resources
 336  *
 337  * NOTES:
 338  *     - I've updated this to the Windows Object Defintion.
 339  */
 340 struct _ADAPTER_OBJECT {
 341   DMA_ADAPTER DmaHeader;
 342   struct _ADAPTER_OBJECT *MasterAdapter;
 343   ULONG MapRegistersPerChannel;
 344   PVOID AdapterBaseVa;
 345   PVOID MapRegisterBase;
 346   ULONG NumberOfMapRegisters;
 347   ULONG CommittedMapRegisters;
 348   PWAIT_CONTEXT_BLOCK CurrentWcb;
 349   KDEVICE_QUEUE ChannelWaitQueue;
 350   PKDEVICE_QUEUE RegisterWaitQueue;
 351   LIST_ENTRY AdapterQueue;
 352   ULONG SpinLock;
 353   PRTL_BITMAP MapRegisters;
 354   PUCHAR PagePort;
 355   UCHAR ChannelNumber;
 356   UCHAR AdapterNumber;
 357   USHORT DmaPortAddress;
 358   union {
 359     DMA_MODE AdapterMode;
 360     UCHAR AdapterModeByte;
 361   };
 362   BOOLEAN NeedsMapRegisters;
 363   BOOLEAN MasterDevice;
 364   UCHAR Width16Bits;
 365   UCHAR ScatterGather;
 366   UCHAR IgnoreCount;
 367   UCHAR Dma32BitAddresses;
 368   UCHAR Dma64BitAddresses;
 369   BOOLEAN LegacyAdapter;
 370   LIST_ENTRY AdapterList;
 371 } ADAPTER_OBJECT;
 372
 373 /*
 374 struct _ADAPTER_OBJECT {
 375   INTERFACE_TYPE InterfaceType;
 376   BOOLEAN Master;
 377   int Channel;
 378   PVOID PagePort;
 379   PVOID CountPort;
 380   PVOID OffsetPort;
 381   KSPIN_LOCK SpinLock;
 382   PVOID Buffer;
 383   BOOLEAN Inuse;
 384   ULONG AvailableMapRegisters;
 385   PVOID MapRegisterBase;
 386   ULONG AllocatedMapRegisters;
 387   PWAIT_CONTEXT_BLOCK WaitContextBlock;
 388   KDEVICE_QUEUE DeviceQueue;
 389   BOOLEAN ScatterGather;
 390   BOOLEAN DemandMode;
 391   BOOLEAN AutoInitialize;
 392 };
 393 */
 394
 395 /* sysinfo.c */
 396 NTSTATUS STDCALL
 397 HalpQuerySystemInformation(IN HAL_QUERY_INFORMATION_CLASS InformationClass,
 398                            IN ULONG BufferSize,
 399                            IN OUT PVOID Buffer,
 400                            OUT PULONG ReturnedLength);
 401
 402
 403 /* Non-standard functions */
 404 VOID STDCALL
 405 HalReleaseDisplayOwnership();
 406
 407 BOOLEAN STDCALL
 408 HalQueryDisplayOwnership();
 409
 410 #if defined(__GNUC__)
 411 #define Ki386SaveFlags(x)           __asm__ __volatile__("pushfl ; popl %0":"=g" (x): /* no input */)
 412 #define Ki386RestoreFlags(x)        __asm__ __volatile__("pushl %0 ; popfl": /* no output */ :"g" (x):"memory")
 413 #define Ki386DisableInterrupts()    __asm__ __volatile__("cli\n\t")
 414 #define Ki386EnableInterrupts()     __asm__ __volatile__("sti\n\t")
 415 #define Ki386HaltProcessor()        __asm__ __volatile__("hlt\n\t")
 416 #define Ki386RdTSC(x)               __asm__ __volatile__("rdtsc\n\t" : "=A" (x.u.LowPart), "=d" (x.u.HighPart));
 417 #define Ki386Rdmsr(msr,val1,val2)   __asm__ __volatile__("rdmsr" : "=a" (val1), "=d" (val2) : "c" (msr))
 418 #define Ki386Wrmsr(msr,val1,val2)   __asm__ __volatile__("wrmsr" : /* no outputs */ : "c" (msr), "a" (val1), "d" (val2))
 419
 420 static inline BYTE Ki386ReadFsByte(ULONG offset)
 421 {
 422    BYTE b;
 423    __asm__ __volatile__("movb %%fs:(%1),%0":"=q" (b):"r" (offset));
 424    return b;
 425 }
 426
 427 static inline VOID Ki386WriteFsByte(ULONG offset, BYTE value)
 428 {
 429    __asm__ __volatile__("movb %0,%%fs:(%1)"::"r" (value), "r" (offset));
 430 }
 431
 432 #elif defined(_MSC_VER)
 433 #define Ki386SaveFlags(x)           __asm pushfd  __asm pop x;
 434 #define Ki386RestoreFlags(x)        __asm push x  __asm popfd;
 435 #define Ki386DisableInterrupts()    __asm cli
 436 #define Ki386EnableInterrupts()     __asm sti
 437 #define Ki386HaltProcessor()        __asm hlt
 438 #else
 439 #error Unknown compiler for inline assembler
 440 #endif
 441
 442 typedef struct tagHALP_HOOKS
 443 {
 444   void (*InitPciBus)(ULONG BusNumber, PBUS_HANDLER BusHandler);
 445 } HALP_HOOKS, *PHALP_HOOKS;
 446
 447 extern HALP_HOOKS HalpHooks;
 448
 449 #endif /* __INTERNAL_HAL_HAL_H */