[USB]
[reactos.git] / reactos / hal / halx86 / legacy / bussupp.c
1 /*
2 * PROJECT: ReactOS HAL
3 * LICENSE: BSD - See COPYING.ARM in the top level directory
4 * FILE: hal/halx86/generic/legacy/bussupp.c
5 * PURPOSE: HAL Legacy Bus Support Code
6 * PROGRAMMERS: ReactOS Portable Systems Group
7 */
8
9 /* INCLUDES *******************************************************************/
10
11 #include <hal.h>
12 #define NDEBUG
13 #include <debug.h>
14
15 /* GLOBALS ********************************************************************/
16
17 extern KSPIN_LOCK HalpPCIConfigLock;
18 ULONG HalpPciIrqMask;
19
20 /* PRIVATE FUNCTIONS **********************************************************/
21
22 PBUS_HANDLER
23 NTAPI
24 HalpAllocateBusHandler(IN INTERFACE_TYPE InterfaceType,
25 IN BUS_DATA_TYPE BusDataType,
26 IN ULONG BusNumber,
27 IN INTERFACE_TYPE ParentBusInterfaceType,
28 IN ULONG ParentBusNumber,
29 IN ULONG BusSpecificData)
30 {
31 PBUS_HANDLER Bus;
32
33 /* Register the bus handler */
34 HalRegisterBusHandler(InterfaceType,
35 BusDataType,
36 BusNumber,
37 ParentBusInterfaceType,
38 ParentBusNumber,
39 BusSpecificData,
40 NULL,
41 &Bus);
42 if (!Bus) return NULL;
43
44 /* Check for a valid interface */
45 if (InterfaceType != InterfaceTypeUndefined)
46 {
47 /* Allocate address ranges and zero them out */
48 Bus->BusAddresses = ExAllocatePoolWithTag(NonPagedPool,
49 sizeof(SUPPORTED_RANGES),
50 ' laH');
51 RtlZeroMemory(Bus->BusAddresses, sizeof(SUPPORTED_RANGES));
52
53 /* Build the data structure */
54 Bus->BusAddresses->Version = HAL_SUPPORTED_RANGE_VERSION;
55 Bus->BusAddresses->Dma.Limit = 7;
56 Bus->BusAddresses->Memory.Limit = 0xFFFFFFFF;
57 Bus->BusAddresses->IO.Limit = 0xFFFF;
58 Bus->BusAddresses->IO.SystemAddressSpace = 1;
59 Bus->BusAddresses->PrefetchMemory.Base = 1;
60 }
61
62 /* Return the bus address */
63 return Bus;
64 }
65
66 VOID
67 NTAPI
68 INIT_FUNCTION
69 HalpRegisterInternalBusHandlers(VOID)
70 {
71 PBUS_HANDLER Bus;
72
73 /* Only do processor 1 */
74 if (KeGetCurrentPrcb()->Number) return;
75
76 /* Register root support */
77 HalpInitBusHandler();
78
79 /* Allocate the system bus */
80 Bus = HalpAllocateBusHandler(Internal,
81 ConfigurationSpaceUndefined,
82 0,
83 InterfaceTypeUndefined,
84 0,
85 0);
86 if (Bus)
87 {
88 /* Set it up */
89 Bus->GetInterruptVector = HalpGetSystemInterruptVector;
90 Bus->TranslateBusAddress = HalpTranslateSystemBusAddress;
91 }
92
93 /* Allocate the CMOS bus */
94 Bus = HalpAllocateBusHandler(InterfaceTypeUndefined,
95 Cmos,
96 0,
97 InterfaceTypeUndefined,
98 0,
99 0);
100 if (Bus)
101 {
102 /* Set it up */
103 Bus->GetBusData = HalpcGetCmosData;
104 Bus->SetBusData = HalpcSetCmosData;
105 }
106
107 /* Allocate the CMOS bus */
108 Bus = HalpAllocateBusHandler(InterfaceTypeUndefined,
109 Cmos,
110 1,
111 InterfaceTypeUndefined,
112 0,
113 0);
114 if (Bus)
115 {
116 /* Set it up */
117 Bus->GetBusData = HalpcGetCmosData;
118 Bus->SetBusData = HalpcSetCmosData;
119 }
120
121 /* Allocate ISA bus */
122 Bus = HalpAllocateBusHandler(Isa,
123 ConfigurationSpaceUndefined,
124 0,
125 Internal,
126 0,
127 0);
128 if (Bus)
129 {
130 /* Set it up */
131 Bus->GetBusData = HalpNoBusData;
132 Bus->BusAddresses->Memory.Limit = 0xFFFFFF;
133 Bus->TranslateBusAddress = HalpTranslateIsaBusAddress;
134 }
135
136 /* No support for EISA or MCA */
137 ASSERT(HalpBusType == MACHINE_TYPE_ISA);
138 }
139
140 #ifndef _MINIHAL_
141 NTSTATUS
142 NTAPI
143 INIT_FUNCTION
144 HalpMarkChipsetDecode(BOOLEAN OverrideEnable)
145 {
146 NTSTATUS Status;
147 UNICODE_STRING KeyString;
148 ULONG Data = OverrideEnable;
149 HANDLE KeyHandle, Handle;
150
151 /* Open CCS key */
152 RtlInitUnicodeString(&KeyString,
153 L"\\REGISTRY\\MACHINE\\SYSTEM\\CURRENTCONTROLSET");
154 Status = HalpOpenRegistryKey(&Handle, 0, &KeyString, KEY_ALL_ACCESS, FALSE);
155 if (NT_SUCCESS(Status))
156 {
157 /* Open PNP Bios key */
158 RtlInitUnicodeString(&KeyString, L"Control\\Biosinfo\\PNPBios");
159 Status = HalpOpenRegistryKey(&KeyHandle,
160 Handle,
161 &KeyString,
162 KEY_ALL_ACCESS,
163 TRUE);
164
165 /* Close root key */
166 ZwClose(Handle);
167
168 /* Check if PNP BIOS key exists */
169 if (NT_SUCCESS(Status))
170 {
171 /* Set the override value */
172 RtlInitUnicodeString(&KeyString, L"FullDecodeChipsetOverride");
173 Status = ZwSetValueKey(KeyHandle,
174 &KeyString,
175 0,
176 REG_DWORD,
177 &Data,
178 sizeof(Data));
179
180 /* Close subkey */
181 ZwClose(KeyHandle);
182 }
183 }
184
185 /* Return status */
186 return Status;
187 }
188
189 PBUS_HANDLER
190 NTAPI
191 INIT_FUNCTION
192 HalpAllocateAndInitPciBusHandler(IN ULONG PciType,
193 IN ULONG BusNo,
194 IN BOOLEAN TestAllocation)
195 {
196 PBUS_HANDLER Bus;
197 PPCIPBUSDATA BusData;
198
199 /* Allocate the bus handler */
200 Bus = HalpAllocateBusHandler(PCIBus,
201 PCIConfiguration,
202 BusNo,
203 Internal,
204 0,
205 sizeof(PCIPBUSDATA));
206
207 /* Set it up */
208 Bus->GetBusData = (PGETSETBUSDATA)HalpGetPCIData;
209 Bus->SetBusData = (PGETSETBUSDATA)HalpSetPCIData;
210 Bus->GetInterruptVector = (PGETINTERRUPTVECTOR)HalpGetPCIIntOnISABus;
211 Bus->AdjustResourceList = (PADJUSTRESOURCELIST)HalpAdjustPCIResourceList;
212 Bus->AssignSlotResources = (PASSIGNSLOTRESOURCES)HalpAssignPCISlotResources;
213 Bus->BusAddresses->Dma.Limit = 0;
214
215 /* Get our custom bus data */
216 BusData = (PPCIPBUSDATA)Bus->BusData;
217
218 /* Setup custom bus data */
219 BusData->CommonData.Tag = PCI_DATA_TAG;
220 BusData->CommonData.Version = PCI_DATA_VERSION;
221 BusData->CommonData.ReadConfig = (PciReadWriteConfig)HalpReadPCIConfig;
222 BusData->CommonData.WriteConfig = (PciReadWriteConfig)HalpWritePCIConfig;
223 BusData->CommonData.Pin2Line = (PciPin2Line)HalpPCIPin2ISALine;
224 BusData->CommonData.Line2Pin = (PciLine2Pin)HalpPCIISALine2Pin;
225 BusData->MaxDevice = PCI_MAX_DEVICES;
226 BusData->GetIrqRange = (PciIrqRange)HalpGetISAFixedPCIIrq;
227
228 /* Initialize the bitmap */
229 RtlInitializeBitMap(&BusData->DeviceConfigured, BusData->ConfiguredBits, 256);
230
231 /* Check the type of PCI bus */
232 switch (PciType)
233 {
234 /* Type 1 PCI Bus */
235 case 1:
236
237 /* Copy the Type 1 handler data */
238 RtlCopyMemory(&PCIConfigHandler,
239 &PCIConfigHandlerType1,
240 sizeof(PCIConfigHandler));
241
242 /* Set correct I/O Ports */
243 BusData->Config.Type1.Address = PCI_TYPE1_ADDRESS_PORT;
244 BusData->Config.Type1.Data = PCI_TYPE1_DATA_PORT;
245 break;
246
247 /* Type 2 PCI Bus */
248 case 2:
249
250 /* Copy the Type 1 handler data */
251 RtlCopyMemory(&PCIConfigHandler,
252 &PCIConfigHandlerType2,
253 sizeof (PCIConfigHandler));
254
255 /* Set correct I/O Ports */
256 BusData->Config.Type2.CSE = PCI_TYPE2_CSE_PORT;
257 BusData->Config.Type2.Forward = PCI_TYPE2_FORWARD_PORT;
258 BusData->Config.Type2.Base = PCI_TYPE2_ADDRESS_BASE;
259
260 /* Only 16 devices supported, not 32 */
261 BusData->MaxDevice = 16;
262 break;
263
264 default:
265
266 /* Invalid type */
267 DbgPrint("HAL: Unnkown PCI type\n");
268 }
269
270 /* Return the bus handler */
271 return Bus;
272 }
273
274 BOOLEAN
275 NTAPI
276 INIT_FUNCTION
277 HalpIsValidPCIDevice(IN PBUS_HANDLER BusHandler,
278 IN PCI_SLOT_NUMBER Slot)
279 {
280 UCHAR DataBuffer[PCI_COMMON_HDR_LENGTH];
281 PPCI_COMMON_CONFIG PciHeader = (PVOID)DataBuffer;
282 ULONG i;
283 ULONG_PTR Address;
284
285 /* Read the PCI header */
286 HalpReadPCIConfig(BusHandler, Slot, PciHeader, 0, PCI_COMMON_HDR_LENGTH);
287
288 /* Make sure it's a valid device */
289 if ((PciHeader->VendorID == PCI_INVALID_VENDORID) ||
290 (PCI_CONFIGURATION_TYPE(PciHeader) != PCI_DEVICE_TYPE))
291 {
292 /* Bail out */
293 return FALSE;
294 }
295
296 /* Make sure interrupt numbers make sense */
297 if (((PciHeader->u.type0.InterruptPin) &&
298 (PciHeader->u.type0.InterruptPin > 4)) ||
299 (PciHeader->u.type0.InterruptLine & 0x70))
300 {
301 /* Bail out */
302 return FALSE;
303 }
304
305 /* Now scan PCI BARs */
306 for (i = 0; i < PCI_TYPE0_ADDRESSES; i++)
307 {
308 /* Check what kind of address it is */
309 Address = PciHeader->u.type0.BaseAddresses[i];
310 if (Address & PCI_ADDRESS_IO_SPACE)
311 {
312 /* Highest I/O port is 65535 */
313 if (Address > 0xFFFF) return FALSE;
314 }
315 else
316 {
317 /* MMIO should be higher than 0x80000 */
318 if ((Address > 0xF) && (Address < 0x80000)) return FALSE;
319 }
320
321 /* Is this a 64-bit address? */
322 if (!(Address & PCI_ADDRESS_IO_SPACE) &&
323 ((Address & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_64BIT))
324 {
325 /* Check the next-next entry, since this one 64-bits wide */
326 i++;
327 }
328 }
329
330 /* Header, interrupt and address data all make sense */
331 return TRUE;
332 }
333
334 static BOOLEAN WarningsGiven[5];
335
336 NTSTATUS
337 NTAPI
338 INIT_FUNCTION
339 HalpGetChipHacks(IN USHORT VendorId,
340 IN USHORT DeviceId,
341 IN UCHAR RevisionId,
342 IN PULONG HackFlags)
343 {
344 UNICODE_STRING KeyName, ValueName;
345 NTSTATUS Status;
346 OBJECT_ATTRIBUTES ObjectAttributes;
347 HANDLE KeyHandle;
348 WCHAR Buffer[32];
349 KEY_VALUE_PARTIAL_INFORMATION PartialInfo;
350 ULONG ResultLength;
351
352 /* Setup the object attributes for the key */
353 RtlInitUnicodeString(&KeyName,
354 L"\\REGISTRY\\MACHINE\\SYSTEM\\CURRENTCONTROLSET\\"
355 L"Control\\HAL");
356 InitializeObjectAttributes(&ObjectAttributes,
357 &KeyName,
358 OBJ_CASE_INSENSITIVE,
359 NULL,
360 NULL);
361
362 /* Open the key */
363 Status = ZwOpenKey(&KeyHandle, KEY_READ, &ObjectAttributes);
364 if (!NT_SUCCESS(Status)) return Status;
365
366 /* Query value */
367 swprintf(Buffer, L"%04X%04X", VendorId, DeviceId);
368 RtlInitUnicodeString(&ValueName, Buffer);
369 Status = ZwQueryValueKey(KeyHandle,
370 &ValueName,
371 KeyValuePartialInformation,
372 &PartialInfo,
373 sizeof(PartialInfo),
374 &ResultLength);
375 if (NT_SUCCESS(Status))
376 {
377 /* Return the flags */
378 DbgPrint("\tFound HackFlags for your chipset\n");
379 *HackFlags = *(PULONG)PartialInfo.Data;
380 DbgPrint("\t\tHack Flags: %lx (Hack Revision: %lx-Your Revision: %lx)\n",
381 *HackFlags, HALP_REVISION_FROM_HACK_FLAGS(*HackFlags), RevisionId);
382
383 /* Does it apply to this revision? */
384 if ((RevisionId) && (RevisionId >= (HALP_REVISION_FROM_HACK_FLAGS(*HackFlags))))
385 {
386 /* Read the revision flags */
387 *HackFlags = HALP_REVISION_HACK_FLAGS(*HackFlags);
388 }
389
390 /* Throw out revision data */
391 *HackFlags = HALP_HACK_FLAGS(*HackFlags);
392 if (!*HackFlags) DbgPrint("\tNo HackFlags for your chipset's revision!\n");
393 }
394
395 /* Close the handle and return */
396 ZwClose(KeyHandle);
397 return Status;
398 }
399
400 BOOLEAN
401 NTAPI
402 INIT_FUNCTION
403 HalpIsRecognizedCard(IN PPCI_REGISTRY_INFO_INTERNAL PciRegistryInfo,
404 IN PPCI_COMMON_CONFIG PciData,
405 IN ULONG Flags)
406 {
407 ULONG ElementCount, i;
408 PPCI_CARD_DESCRIPTOR CardDescriptor;
409
410 /* How many PCI Cards that we know about? */
411 ElementCount = PciRegistryInfo->ElementCount;
412 if (!ElementCount) return FALSE;
413
414 /* Loop all descriptors */
415 CardDescriptor = &PciRegistryInfo->CardList[0];
416 for (i = 0; i < ElementCount; i++, CardDescriptor++)
417 {
418 /* Check for flag match */
419 if (CardDescriptor->Flags != Flags) continue;
420
421 /* Check for VID-PID match */
422 if ((CardDescriptor->VendorID != PciData->VendorID) ||
423 (CardDescriptor->DeviceID != PciData->DeviceID))
424 {
425 /* Skip */
426 continue;
427 }
428
429 /* Check for revision match, if requested */
430 if ((CardDescriptor->Flags & HALP_CHECK_CARD_REVISION_ID) &&
431 (CardDescriptor->RevisionID != PciData->RevisionID))
432 {
433 /* Skip */
434 continue;
435 }
436
437 /* Check what kind of device this is */
438 switch (PCI_CONFIGURATION_TYPE(PciData))
439 {
440 /* CardBUS Bridge */
441 case PCI_CARDBUS_BRIDGE_TYPE:
442
443 /* This means the real device header is in the device-specific data */
444 PciData = (PPCI_COMMON_CONFIG)PciData->DeviceSpecific;
445
446 /* Normal PCI device */
447 case PCI_DEVICE_TYPE:
448
449 /* Check for subvendor match, if requested */
450 if ((CardDescriptor->Flags & HALP_CHECK_CARD_SUBVENDOR_ID) &&
451 (CardDescriptor->SubsystemVendorID != PciData->u.type0.SubVendorID))
452 {
453 /* Skip */
454 continue;
455 }
456
457 /* Check for subsystem match, if requested */
458 if ((CardDescriptor->Flags & HALP_CHECK_CARD_SUBSYSTEM_ID) &&
459 (CardDescriptor->SubsystemID != PciData->u.type0.SubSystemID))
460 {
461 /* Skip */
462 continue;
463 }
464
465 /* You made it! */
466 return TRUE;
467
468 /* PCI Bridge -- don't bother */
469 case PCI_BRIDGE_TYPE:
470 default:
471
472 /* Recognize it */
473 return TRUE;
474 }
475 }
476
477 /* This means the card isn't recognized */
478 return FALSE;
479 }
480
481 BOOLEAN
482 NTAPI
483 INIT_FUNCTION
484 HalpIsIdeDevice(IN PPCI_COMMON_CONFIG PciData)
485 {
486 /* Simple test first */
487 if ((PciData->BaseClass == PCI_CLASS_MASS_STORAGE_CTLR) &&
488 (PciData->SubClass == PCI_SUBCLASS_MSC_IDE_CTLR))
489 {
490 /* The device is nice enough to admit it */
491 return TRUE;
492 }
493
494 /* Symphony 82C101 */
495 if (PciData->VendorID == 0x1C1C) return TRUE;
496
497 /* ALi MS4803 or M5219 */
498 if ((PciData->VendorID == 0x10B9) &&
499 ((PciData->DeviceID == 0x5215) || (PciData->DeviceID == 0x5219)))
500 {
501 return TRUE;
502 }
503
504 /* Appian Technology */
505 if ((PciData->VendorID == 0x1097) && (PciData->DeviceID == 0x38)) return TRUE;
506
507 /* Compaq Triflex Dual EIDE Controller */
508 if ((PciData->VendorID == 0xE11) && (PciData->DeviceID == 0xAE33)) return TRUE;
509
510 /* Micron PC Tech RZ1000 */
511 if ((PciData->VendorID == 0x1042) && (PciData->DeviceID == 0x1000)) return TRUE;
512
513 /* SiS 85C601 or 5513 [IDE] */
514 if ((PciData->VendorID == 0x1039) &&
515 ((PciData->DeviceID == 0x601) || (PciData->DeviceID == 0x5513)))
516 {
517 return TRUE;
518 }
519
520 /* Symphony Labs W83769F */
521 if ((PciData->VendorID == 0x10AD) &&
522 ((PciData->DeviceID == 0x1) || (PciData->DeviceID == 0x150)))
523 {
524 return TRUE;
525 }
526
527 /* UMC UM8673F */
528 if ((PciData->VendorID == 0x1060) && (PciData->DeviceID == 0x101)) return TRUE;
529
530 /* You've survived */
531 return FALSE;
532 }
533
534 BOOLEAN
535 NTAPI
536 INIT_FUNCTION
537 HalpIsBridgeDevice(IN PPCI_COMMON_CONFIG PciData)
538 {
539 /* Either this is a PCI-to-PCI Bridge, or a CardBUS Bridge */
540 return (((PCI_CONFIGURATION_TYPE(PciData) == PCI_BRIDGE_TYPE) &&
541 (PciData->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
542 (PciData->SubClass == PCI_SUBCLASS_BR_PCI_TO_PCI)) ||
543 ((PCI_CONFIGURATION_TYPE(PciData) == PCI_CARDBUS_BRIDGE_TYPE) &&
544 (PciData->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
545 (PciData->SubClass == PCI_SUBCLASS_BR_CARDBUS)));
546 }
547
548 BOOLEAN
549 NTAPI
550 INIT_FUNCTION
551 HalpGetPciBridgeConfig(IN ULONG PciType,
552 IN PUCHAR BusCount)
553 {
554 PCI_SLOT_NUMBER PciSlot;
555 ULONG i, j, k;
556 UCHAR DataBuffer[PCI_COMMON_HDR_LENGTH];
557 PPCI_COMMON_CONFIG PciData = (PPCI_COMMON_CONFIG)DataBuffer;
558 PBUS_HANDLER BusHandler;
559
560 /* Loop PCI buses */
561 PciSlot.u.bits.Reserved = 0;
562 for (i = 0; i < *BusCount; i++)
563 {
564 /* Get the bus handler */
565 BusHandler = HalHandlerForBus(PCIBus, i);
566
567 /* Loop every device */
568 for (j = 0; j < PCI_MAX_DEVICES; j++)
569 {
570 /* Loop every function */
571 PciSlot.u.bits.DeviceNumber = j;
572 for (k = 0; k < PCI_MAX_FUNCTION; k++)
573 {
574 /* Build the final slot structure */
575 PciSlot.u.bits.FunctionNumber = k;
576
577 /* Read the configuration information */
578 HalpReadPCIConfig(BusHandler,
579 PciSlot,
580 PciData,
581 0,
582 PCI_COMMON_HDR_LENGTH);
583
584 /* Skip if this is an invalid function */
585 if (PciData->VendorID == PCI_INVALID_VENDORID) continue;
586
587 /* Make sure that this is a PCI bridge or a cardbus bridge */
588 if (!HalpIsBridgeDevice(PciData)) continue;
589
590 /* Not supported */
591 if (!WarningsGiven[2]++) DPRINT1("Your machine has a PCI-to-PCI or CardBUS Bridge. PCI devices may fail!\n");
592 continue;
593 }
594 }
595 }
596
597 /* If we exited the loop, then there's no bridge to worry about */
598 return FALSE;
599 }
600
601 VOID
602 NTAPI
603 INIT_FUNCTION
604 HalpFixupPciSupportedRanges(IN ULONG BusCount)
605 {
606 ULONG i;
607 PBUS_HANDLER Bus, ParentBus;
608
609 /* Loop all buses */
610 for (i = 0; i < BusCount; i++)
611 {
612 /* Get PCI bus handler */
613 Bus = HalHandlerForBus(PCIBus, i);
614
615 /* Loop all parent buses */
616 ParentBus = Bus->ParentHandler;
617 while (ParentBus)
618 {
619 /* Should merge addresses */
620 if (!WarningsGiven[0]++) DPRINT1("Found parent bus (indicating PCI Bridge). PCI devices may fail!\n");
621
622 /* Check the next parent */
623 ParentBus = ParentBus->ParentHandler;
624 }
625 }
626
627 /* Loop all buses again */
628 for (i = 0; i < BusCount; i++)
629 {
630 /* Get PCI bus handler */
631 Bus = HalHandlerForBus(PCIBus, i);
632
633 /* Check if this is a PCI 2.2 Bus with Subtractive Decode */
634 if (!((PPCIPBUSDATA)Bus->BusData)->Subtractive)
635 {
636 /* Loop all parent buses */
637 ParentBus = Bus->ParentHandler;
638 while (ParentBus)
639 {
640 /* But check only PCI parent buses specifically */
641 if (ParentBus->InterfaceType == PCIBus)
642 {
643 /* Should trim addresses */
644 if (!WarningsGiven[1]++) DPRINT1("Found parent PCI Bus (indicating PCI-to-PCI Bridge). PCI devices may fail!\n");
645 }
646
647 /* Check the next parent */
648 ParentBus = ParentBus->ParentHandler;
649 }
650 }
651 }
652
653 /* Loop buses one last time */
654 for (i = 0; i < BusCount; i++)
655 {
656 /* Get the PCI bus handler */
657 Bus = HalHandlerForBus(PCIBus, i);
658
659 /* Sort and combine (trim) bus address range information */
660 DPRINT("Warning: Bus addresses not being optimized!\n");
661 }
662 }
663
664 VOID
665 NTAPI
666 INIT_FUNCTION
667 ShowSize(ULONG x)
668 {
669 if (!x) return;
670 DbgPrint(" [size=");
671 if (x < 1024)
672 {
673 DbgPrint("%d", (int) x);
674 }
675 else if (x < 1048576)
676 {
677 DbgPrint("%dK", (int)(x / 1024));
678 }
679 else if (x < 0x80000000)
680 {
681 DbgPrint("%dM", (int)(x / 1048576));
682 }
683 else
684 {
685 DbgPrint("%d", x);
686 }
687 DbgPrint("]\n");
688 }
689
690 VOID
691 NTAPI
692 INIT_FUNCTION
693 HalpDebugPciDumpBus(IN ULONG i,
694 IN ULONG j,
695 IN ULONG k,
696 IN PPCI_COMMON_CONFIG PciData)
697 {
698 extern CHAR ClassTable[3922];
699 extern CHAR VendorTable[642355];
700 PCHAR p, ClassName, SubClassName, VendorName, ProductName, SubVendorName;
701 ULONG Length;
702 CHAR LookupString[16] = "";
703 CHAR bSubClassName[64] = "";
704 CHAR bVendorName[64] = "";
705 CHAR bProductName[128] = "Unknown device";
706 CHAR bSubVendorName[128] = "Unknown";
707 ULONG Size, Mem, b;
708
709 /* Isolate the class name */
710 sprintf(LookupString, "C %02x", PciData->BaseClass);
711 ClassName = strstr(ClassTable, LookupString);
712 if (ClassName)
713 {
714 /* Isolate the subclass name */
715 ClassName += 6;
716 sprintf(LookupString, "\t%02x", PciData->SubClass);
717 SubClassName = strstr(ClassName, LookupString);
718 if (SubClassName)
719 {
720 /* Copy the subclass into our buffer */
721 SubClassName += 5;
722 p = strchr(SubClassName, '\r');
723 Length = p - SubClassName;
724 if (Length >= sizeof(bSubClassName)) Length = sizeof(bSubClassName) - 1;
725 strncpy(bSubClassName, SubClassName, Length);
726 bSubClassName[Length] = '\0';
727 }
728 }
729
730 /* Isolate the vendor name */
731 sprintf(LookupString, "\n%04x ", PciData->VendorID);
732 VendorName = strstr(VendorTable, LookupString);
733 if (VendorName)
734 {
735 /* Copy the vendor name into our buffer */
736 VendorName += 7;
737 p = strchr(VendorName, '\r');
738 Length = p - VendorName;
739 if (Length >= sizeof(bVendorName)) Length = sizeof(bVendorName) - 1;
740 strncpy(bVendorName, VendorName, Length);
741 bVendorName[Length] = '\0';
742
743 /* Isolate the product name */
744 sprintf(LookupString, "\t%04x", PciData->DeviceID);
745 ProductName = strstr(VendorName, LookupString);
746 if (ProductName)
747 {
748 /* Copy the product name into our buffer */
749 ProductName += 7;
750 p = strchr(ProductName, '\r');
751 Length = p - ProductName;
752 if (Length >= sizeof(bProductName)) Length = sizeof(bProductName) - 1;
753 strncpy(bProductName, ProductName, Length);
754 bProductName[Length] = '\0';
755
756 /* Isolate the subvendor and subsystem name */
757 sprintf(LookupString,
758 "\t\t%04x %04x ",
759 PciData->u.type0.SubVendorID,
760 PciData->u.type0.SubSystemID);
761 SubVendorName = strstr(ProductName, LookupString);
762 if (SubVendorName)
763 {
764 /* Copy the subvendor name into our buffer */
765 SubVendorName += 13;
766 p = strchr(SubVendorName, '\r');
767 Length = p - SubVendorName;
768 if (Length >= sizeof(bSubVendorName)) Length = sizeof(bSubVendorName) - 1;
769 strncpy(bSubVendorName, SubVendorName, Length);
770 bSubVendorName[Length] = '\0';
771 }
772 }
773 }
774
775 /* Print out the data */
776 DbgPrint("%02x:%02x.%x %s [%02x%02x]: %s %s [%04x:%04x] (rev %02x)\n"
777 "\tSubsystem: %s [%04x:%04x]\n",
778 i,
779 j,
780 k,
781 bSubClassName,
782 PciData->BaseClass,
783 PciData->SubClass,
784 bVendorName,
785 bProductName,
786 PciData->VendorID,
787 PciData->DeviceID,
788 PciData->RevisionID,
789 bSubVendorName,
790 PciData->u.type0.SubVendorID,
791 PciData->u.type0.SubSystemID);
792
793 /* Print out and decode flags */
794 DbgPrint("\tFlags:");
795 if (PciData->Command & PCI_ENABLE_BUS_MASTER) DbgPrint(" bus master,");
796 if (PciData->Status & PCI_STATUS_66MHZ_CAPABLE) DbgPrint(" 66MHz,");
797 if ((PciData->Status & PCI_STATUS_DEVSEL) == 0x000) DbgPrint(" fast devsel,");
798 if ((PciData->Status & PCI_STATUS_DEVSEL) == 0x200) DbgPrint(" medium devsel,");
799 if ((PciData->Status & PCI_STATUS_DEVSEL) == 0x400) DbgPrint(" slow devsel,");
800 if ((PciData->Status & PCI_STATUS_DEVSEL) == 0x600) DbgPrint(" unknown devsel,");
801 DbgPrint(" latency %d", PciData->LatencyTimer);
802 if (PciData->u.type0.InterruptPin != 0 &&
803 PciData->u.type0.InterruptLine != 0 &&
804 PciData->u.type0.InterruptLine != 0xFF) DbgPrint(", IRQ %02d", PciData->u.type0.InterruptLine);
805 else if (PciData->u.type0.InterruptPin != 0) DbgPrint(", IRQ assignment required");
806 DbgPrint("\n");
807
808 /* Scan addresses */
809 Size = 0;
810 for (b = 0; b < PCI_TYPE0_ADDRESSES; b++)
811 {
812 /* Check for a BAR */
813 Mem = PciData->u.type0.BaseAddresses[b];
814 if (Mem)
815 {
816 /* Decode the address type */
817 if (Mem & PCI_ADDRESS_IO_SPACE)
818 {
819 /* Guess the size */
820 Size = 1 << 2;
821 while (!(Mem & Size) && (Size)) Size <<= 1;
822
823 /* Print it out */
824 DbgPrint("\tI/O ports at %04lx", Mem & PCI_ADDRESS_IO_ADDRESS_MASK);
825 ShowSize(Size);
826 }
827 else
828 {
829 /* Guess the size */
830 Size = 1 << 8;
831 while (!(Mem & Size) && (Size)) Size <<= 1;
832
833 /* Print it out */
834 DbgPrint("\tMemory at %08lx (%d-bit, %sprefetchable)",
835 Mem & PCI_ADDRESS_MEMORY_ADDRESS_MASK,
836 (Mem & PCI_ADDRESS_MEMORY_TYPE_MASK) == PCI_TYPE_32BIT ? 32 : 64,
837 (Mem & PCI_ADDRESS_MEMORY_PREFETCHABLE) ? "" : "non-");
838 ShowSize(Size);
839 }
840 }
841 }
842 }
843 #endif
844
845 VOID
846 NTAPI
847 INIT_FUNCTION
848 HalpInitializePciBus(VOID)
849 {
850 #ifndef _MINIHAL_
851 PPCI_REGISTRY_INFO_INTERNAL PciRegistryInfo;
852 UCHAR PciType;
853 PCI_SLOT_NUMBER PciSlot;
854 ULONG i, j, k;
855 UCHAR DataBuffer[PCI_COMMON_HDR_LENGTH];
856 PPCI_COMMON_CONFIG PciData = (PPCI_COMMON_CONFIG)DataBuffer;
857 PBUS_HANDLER BusHandler;
858 ULONG HackFlags;
859 BOOLEAN ExtendedAddressDecoding = FALSE;
860 NTSTATUS Status;
861
862 /* Query registry information */
863 PciRegistryInfo = HalpQueryPciRegistryInfo();
864 if (!PciRegistryInfo) return;
865
866 /* Initialize the PCI configuration lock */
867 KeInitializeSpinLock(&HalpPCIConfigLock);
868
869 /* Get the type and free the info structure */
870 PciType = PciRegistryInfo->HardwareMechanism & 0xF;
871
872 /* Check if this is a type 2 PCI bus with at least one bus */
873 if ((PciRegistryInfo->NoBuses) && (PciType == 2))
874 {
875 /* Setup the PCI slot */
876 PciSlot.u.bits.Reserved = 0;
877 PciSlot.u.bits.FunctionNumber = 0;
878
879 /* Loop all slots */
880 for (i = 0; i < 32; i++)
881 {
882 /* Try to setup a Type 2 PCI slot */
883 PciType = 2;
884 BusHandler = HalpAllocateAndInitPciBusHandler(2, 0, TRUE);
885 if (!BusHandler) break;
886
887 /* Now check if it's valid */
888 if (HalpIsValidPCIDevice(BusHandler, PciSlot)) break;
889
890 /* Heh, the BIOS lied... try Type 1 */
891 PciType = 1;
892 BusHandler = HalpAllocateAndInitPciBusHandler(1, 0, TRUE);
893 if (!BusHandler) break;
894
895 /* Now check if it's valid */
896 if (HalpIsValidPCIDevice(BusHandler, PciSlot)) break;
897
898 /* Keep trying */
899 PciType = 2;
900 }
901
902 /* Now allocate the correct kind of handler */
903 HalpAllocateAndInitPciBusHandler(PciType, 0, FALSE);
904 }
905
906 /* Okay, now loop all PCI bridges */
907 do
908 {
909 /* Loop all PCI buses */
910 for (i = 0; i < PciRegistryInfo->NoBuses; i++)
911 {
912 /* Check if we have a handler for it */
913 if (!HalHandlerForBus(PCIBus, i))
914 {
915 /* Allocate it */
916 HalpAllocateAndInitPciBusHandler(PciType, i, FALSE);
917 }
918 }
919 /* Go to the next bridge */
920 } while (HalpGetPciBridgeConfig(PciType, &PciRegistryInfo->NoBuses));
921
922 /* Now build correct address range informaiton */
923 HalpFixupPciSupportedRanges(PciRegistryInfo->NoBuses);
924
925 /* Loop every bus */
926 DbgPrint("\n====== PCI BUS HARDWARE DETECTION =======\n\n");
927 PciSlot.u.bits.Reserved = 0;
928 for (i = 0; i < PciRegistryInfo->NoBuses; i++)
929 {
930 /* Get the bus handler */
931 BusHandler = HalHandlerForBus(PCIBus, i);
932
933 /* Loop every device */
934 for (j = 0; j < 32; j++)
935 {
936 /* Loop every function */
937 PciSlot.u.bits.DeviceNumber = j;
938 for (k = 0; k < 8; k++)
939 {
940 /* Build the final slot structure */
941 PciSlot.u.bits.FunctionNumber = k;
942
943 /* Read the configuration information */
944 HalpReadPCIConfig(BusHandler,
945 PciSlot,
946 PciData,
947 0,
948 PCI_COMMON_HDR_LENGTH);
949
950 /* Skip if this is an invalid function */
951 if (PciData->VendorID == PCI_INVALID_VENDORID) continue;
952
953 /* Print out the entry */
954 HalpDebugPciDumpBus(i, j, k, PciData);
955
956 /* Check if this is a Cardbus bridge */
957 if (PCI_CONFIGURATION_TYPE(PciData) == PCI_CARDBUS_BRIDGE_TYPE)
958 {
959 /* Not supported */
960 DbgPrint("\tDevice is a PCI Cardbus Bridge. It will not work!\n");
961 continue;
962 }
963
964 /* Check if this is a PCI device */
965 if (PCI_CONFIGURATION_TYPE(PciData) != PCI_BRIDGE_TYPE)
966 {
967 /* Check if it has an interrupt pin and line registered */
968 if ((PciData->u.type1.InterruptPin) &&
969 (PciData->u.type1.InterruptLine))
970 {
971 /* Check if this interrupt line is connected to the bus */
972 if (PciData->u.type1.InterruptLine < 16)
973 {
974 /* Is this an IDE device? */
975 if (!HalpIsIdeDevice(PciData))
976 {
977 /* We'll mask out this interrupt then */
978 DbgPrint("\tDevice is using IRQ %d! ISA Cards using that IRQ may fail!\n",
979 PciData->u.type1.InterruptLine);
980 HalpPciIrqMask |= (1 << PciData->u.type1.InterruptLine);
981 }
982 }
983 }
984 }
985
986 /* Check for broken Intel chips */
987 if (PciData->VendorID == 0x8086)
988 {
989 /* Check for broken 82830 PCI controller */
990 if ((PciData->DeviceID == 0x04A3) &&
991 (PciData->RevisionID < 0x11))
992 {
993 /* Skip */
994 DbgPrint("\tDevice is a broken Intel 82430 PCI Controller. It will not work!\n\n");
995 continue;
996 }
997
998 /* Check for broken 82378 PCI-to-ISA Bridge */
999 if ((PciData->DeviceID == 0x0484) &&
1000 (PciData->RevisionID <= 3))
1001 {
1002 /* Skip */
1003 DbgPrint("\tDevice is a broken Intel 82378 PCI-to-ISA Bridge. It will not work!\n\n");
1004 continue;
1005 }
1006
1007 /* Check for broken 82450 PCI Bridge */
1008 if ((PciData->DeviceID == 0x84C4) &&
1009 (PciData->RevisionID <= 4))
1010 {
1011 DbgPrint("\tDevice is a Intel Orion 82450 PCI Bridge. It will not work!\n\n");
1012 continue;
1013 }
1014 }
1015
1016 /* Do we know this card? */
1017 if (!ExtendedAddressDecoding)
1018 {
1019 /* Check for it */
1020 if (HalpIsRecognizedCard(PciRegistryInfo,
1021 PciData,
1022 HALP_CARD_FEATURE_FULL_DECODE))
1023 {
1024 /* We'll do chipset checks later */
1025 DbgPrint("\tDevice has Extended Address Decoding. It may fail to work on older BIOSes!\n");
1026 ExtendedAddressDecoding = TRUE;
1027 }
1028 }
1029
1030 /* Check if this is a USB controller */
1031 if ((PciData->BaseClass == PCI_CLASS_SERIAL_BUS_CTLR) &&
1032 (PciData->SubClass == PCI_SUBCLASS_SB_USB))
1033 {
1034 /* Check if this is an OHCI controller */
1035 if (PciData->ProgIf == 0x10)
1036 {
1037 DbgPrint("\tDevice is an OHCI (USB) PCI Expansion Card. Turn off Legacy USB in your BIOS!\n\n");
1038 continue;
1039 }
1040
1041 /* Check for Intel UHCI controller */
1042 if (PciData->VendorID == 0x8086)
1043 {
1044 DbgPrint("\tDevice is an Intel UHCI (USB) Controller. Turn off Legacy USB in your BIOS!\n\n");
1045 continue;
1046 }
1047
1048 /* Check for VIA UHCI controller */
1049 if (PciData->VendorID == 0x1106)
1050 {
1051 DbgPrint("\tDevice is a VIA UHCI (USB) Controller. Turn off Legacy USB in your BIOS!\n\n");
1052 continue;
1053 }
1054 }
1055
1056 /* Now check the registry for chipset hacks */
1057 Status = HalpGetChipHacks(PciData->VendorID,
1058 PciData->DeviceID,
1059 PciData->RevisionID,
1060 &HackFlags);
1061 if (NT_SUCCESS(Status))
1062 {
1063 /* Check for broken ACPI routing */
1064 if (HackFlags & HAL_PCI_CHIP_HACK_DISABLE_ACPI_IRQ_ROUTING)
1065 {
1066 DbgPrint("This chipset has broken ACPI IRQ Routing! Be aware!\n\n");
1067 continue;
1068 }
1069
1070 /* Check for broken ACPI timer */
1071 if (HackFlags & HAL_PCI_CHIP_HACK_BROKEN_ACPI_TIMER)
1072 {
1073 DbgPrint("This chipset has a broken ACPI timer! Be aware!\n\n");
1074 continue;
1075 }
1076
1077 /* Check for hibernate-disable */
1078 if (HackFlags & HAL_PCI_CHIP_HACK_DISABLE_HIBERNATE)
1079 {
1080 DbgPrint("This chipset has a broken PCI device which is incompatible with hibernation. Be aware!\n\n");
1081 continue;
1082 }
1083
1084 /* Check for USB controllers that generate SMIs */
1085 if (HackFlags & HAL_PCI_CHIP_HACK_USB_SMI_DISABLE)
1086 {
1087 DbgPrint("This chipset has a USB controller which generates SMIs. ReactOS will likely fail to boot!\n\n");
1088 continue;
1089 }
1090 }
1091
1092 /* Terminate the entry */
1093 DbgPrint("\n");
1094 }
1095 }
1096 }
1097
1098 /* Initialize NMI Crash Flag */
1099 HalpGetNMICrashFlag();
1100
1101 /* Free the registry data */
1102 ExFreePoolWithTag(PciRegistryInfo, TAG_HAL);
1103
1104 /* Tell PnP if this hard supports correct decoding */
1105 HalpMarkChipsetDecode(ExtendedAddressDecoding);
1106 DbgPrint("====== PCI BUS DETECTION COMPLETE =======\n\n");
1107 #endif
1108 }
1109
1110 VOID
1111 NTAPI
1112 INIT_FUNCTION
1113 HalpInitBusHandlers(VOID)
1114 {
1115 /* Register the HAL Bus Handler support */
1116 HalpRegisterInternalBusHandlers();
1117 }
1118
1119 VOID
1120 NTAPI
1121 INIT_FUNCTION
1122 HalpRegisterKdSupportFunctions(VOID)
1123 {
1124 /* Register PCI Device Functions */
1125 KdSetupPciDeviceForDebugging = HalpSetupPciDeviceForDebugging;
1126 KdReleasePciDeviceforDebugging = HalpReleasePciDeviceForDebugging;
1127
1128 /* Register memory functions */
1129 #ifndef _MINIHAL_
1130 KdMapPhysicalMemory64 = HalpMapPhysicalMemory64;
1131 KdUnmapVirtualAddress = HalpUnmapVirtualAddress;
1132 #endif
1133
1134 /* Register ACPI stub */
1135 KdCheckPowerButton = HalpCheckPowerButton;
1136 }
1137
1138 NTSTATUS
1139 NTAPI
1140 HalpAssignSlotResources(IN PUNICODE_STRING RegistryPath,
1141 IN PUNICODE_STRING DriverClassName,
1142 IN PDRIVER_OBJECT DriverObject,
1143 IN PDEVICE_OBJECT DeviceObject,
1144 IN INTERFACE_TYPE BusType,
1145 IN ULONG BusNumber,
1146 IN ULONG SlotNumber,
1147 IN OUT PCM_RESOURCE_LIST *AllocatedResources)
1148 {
1149 PBUS_HANDLER Handler;
1150 NTSTATUS Status;
1151 PAGED_CODE();
1152 DPRINT1("Slot assignment for %d on bus %d\n", BusType, BusNumber);
1153
1154 /* Find the handler */
1155 Handler = HalReferenceHandlerForBus(BusType, BusNumber);
1156 if (!Handler) return STATUS_NOT_FOUND;
1157
1158 /* Do the assignment */
1159 Status = Handler->AssignSlotResources(Handler,
1160 Handler,
1161 RegistryPath,
1162 DriverClassName,
1163 DriverObject,
1164 DeviceObject,
1165 SlotNumber,
1166 AllocatedResources);
1167
1168 /* Dereference the handler and return */
1169 HalDereferenceBusHandler(Handler);
1170 return Status;
1171 }
1172
1173 BOOLEAN
1174 NTAPI
1175 HaliFindBusAddressTranslation(IN PHYSICAL_ADDRESS BusAddress,
1176 IN OUT PULONG AddressSpace,
1177 OUT PPHYSICAL_ADDRESS TranslatedAddress,
1178 IN OUT PULONG_PTR Context,
1179 IN BOOLEAN NextBus)
1180 {
1181 PHAL_BUS_HANDLER BusHandler;
1182 PBUS_HANDLER Handler;
1183 PLIST_ENTRY NextEntry;
1184 ULONG ContextValue;
1185
1186 /* Make sure we have a context */
1187 if (!Context) return FALSE;
1188 ASSERT((*Context) || (NextBus == TRUE));
1189
1190 /* Read the context */
1191 ContextValue = *Context;
1192
1193 /* Find the bus handler */
1194 Handler = HalpContextToBusHandler(ContextValue);
1195 if (!Handler) return FALSE;
1196
1197 /* Check if this is an ongoing lookup */
1198 if (NextBus)
1199 {
1200 /* Get the HAL bus handler */
1201 BusHandler = CONTAINING_RECORD(Handler, HAL_BUS_HANDLER, Handler);
1202 NextEntry = &BusHandler->AllHandlers;
1203
1204 /* Get the next one if we were already with one */
1205 if (ContextValue) NextEntry = NextEntry->Flink;
1206
1207 /* Start scanning */
1208 while (TRUE)
1209 {
1210 /* Check if this is the last one */
1211 if (NextEntry == &HalpAllBusHandlers)
1212 {
1213 /* Quit */
1214 *Context = 1;
1215 return FALSE;
1216 }
1217
1218 /* Call this translator */
1219 BusHandler = CONTAINING_RECORD(NextEntry, HAL_BUS_HANDLER, AllHandlers);
1220 if (HalTranslateBusAddress(BusHandler->Handler.InterfaceType,
1221 BusHandler->Handler.BusNumber,
1222 BusAddress,
1223 AddressSpace,
1224 TranslatedAddress)) break;
1225
1226 /* Try the next one */
1227 NextEntry = NextEntry->Flink;
1228 }
1229
1230 /* If we made it, we're done */
1231 *Context = (ULONG_PTR)Handler;
1232 return TRUE;
1233 }
1234
1235 /* Try the first one through */
1236 if (!HalTranslateBusAddress(Handler->InterfaceType,
1237 Handler->BusNumber,
1238 BusAddress,
1239 AddressSpace,
1240 TranslatedAddress)) return FALSE;
1241
1242 /* Remember for next time */
1243 *Context = (ULONG_PTR)Handler;
1244 return TRUE;
1245 }
1246
1247 BOOLEAN
1248 NTAPI
1249 HaliTranslateBusAddress(IN INTERFACE_TYPE InterfaceType,
1250 IN ULONG BusNumber,
1251 IN PHYSICAL_ADDRESS BusAddress,
1252 IN OUT PULONG AddressSpace,
1253 OUT PPHYSICAL_ADDRESS TranslatedAddress)
1254 {
1255 PBUS_HANDLER Handler;
1256 BOOLEAN Status;
1257
1258 /* Find the handler */
1259 Handler = HalReferenceHandlerForBus(InterfaceType, BusNumber);
1260 if (!(Handler) || !(Handler->TranslateBusAddress))
1261 {
1262 DPRINT1("No translator Interface: %x, Bus: %x, Handler: %x!\n", InterfaceType, BusNumber, Handler);
1263 return FALSE;
1264 }
1265
1266 /* Do the assignment */
1267 Status = Handler->TranslateBusAddress(Handler,
1268 Handler,
1269 BusAddress,
1270 AddressSpace,
1271 TranslatedAddress);
1272
1273 /* Dereference the handler and return */
1274 HalDereferenceBusHandler(Handler);
1275 return Status;
1276 }
1277
1278 /* PUBLIC FUNCTIONS **********************************************************/
1279
1280 /*
1281 * @implemented
1282 */
1283 NTSTATUS
1284 NTAPI
1285 HalAdjustResourceList(IN PIO_RESOURCE_REQUIREMENTS_LIST *ResourceList)
1286 {
1287 PBUS_HANDLER Handler;
1288 ULONG Status;
1289 PAGED_CODE();
1290
1291 /* Find the handler */
1292 Handler = HalReferenceHandlerForBus((*ResourceList)->InterfaceType,
1293 (*ResourceList)->BusNumber);
1294 if (!Handler) return STATUS_SUCCESS;
1295
1296 /* Do the assignment */
1297 Status = Handler->AdjustResourceList(Handler,
1298 Handler,
1299 ResourceList);
1300
1301 /* Dereference the handler and return */
1302 HalDereferenceBusHandler(Handler);
1303 return Status;
1304 }
1305
1306 /*
1307 * @implemented
1308 */
1309 NTSTATUS
1310 NTAPI
1311 HalAssignSlotResources(IN PUNICODE_STRING RegistryPath,
1312 IN PUNICODE_STRING DriverClassName,
1313 IN PDRIVER_OBJECT DriverObject,
1314 IN PDEVICE_OBJECT DeviceObject,
1315 IN INTERFACE_TYPE BusType,
1316 IN ULONG BusNumber,
1317 IN ULONG SlotNumber,
1318 IN OUT PCM_RESOURCE_LIST *AllocatedResources)
1319 {
1320 PAGED_CODE();
1321
1322 /* Check the bus type */
1323 if (BusType != PCIBus)
1324 {
1325 /* Call our internal handler */
1326 return HalpAssignSlotResources(RegistryPath,
1327 DriverClassName,
1328 DriverObject,
1329 DeviceObject,
1330 BusType,
1331 BusNumber,
1332 SlotNumber,
1333 AllocatedResources);
1334 }
1335 else
1336 {
1337 /* Call the PCI registered function */
1338 return HalPciAssignSlotResources(RegistryPath,
1339 DriverClassName,
1340 DriverObject,
1341 DeviceObject,
1342 PCIBus,
1343 BusNumber,
1344 SlotNumber,
1345 AllocatedResources);
1346 }
1347 }
1348
1349 /*
1350 * @implemented
1351 */
1352 ULONG
1353 NTAPI
1354 HalGetBusData(IN BUS_DATA_TYPE BusDataType,
1355 IN ULONG BusNumber,
1356 IN ULONG SlotNumber,
1357 IN PVOID Buffer,
1358 IN ULONG Length)
1359 {
1360 /* Call the extended function */
1361 return HalGetBusDataByOffset(BusDataType,
1362 BusNumber,
1363 SlotNumber,
1364 Buffer,
1365 0,
1366 Length);
1367 }
1368
1369 /*
1370 * @implemented
1371 */
1372 ULONG
1373 NTAPI
1374 HalGetBusDataByOffset(IN BUS_DATA_TYPE BusDataType,
1375 IN ULONG BusNumber,
1376 IN ULONG SlotNumber,
1377 IN PVOID Buffer,
1378 IN ULONG Offset,
1379 IN ULONG Length)
1380 {
1381 PBUS_HANDLER Handler;
1382 ULONG Status;
1383
1384 /* Find the handler */
1385 Handler = HaliReferenceHandlerForConfigSpace(BusDataType, BusNumber);
1386 if (!Handler) return 0;
1387
1388 /* Do the assignment */
1389 Status = Handler->GetBusData(Handler,
1390 Handler,
1391 SlotNumber,
1392 Buffer,
1393 Offset,
1394 Length);
1395
1396 /* Dereference the handler and return */
1397 HalDereferenceBusHandler(Handler);
1398 return Status;
1399 }
1400
1401 /*
1402 * @implemented
1403 */
1404 ULONG
1405 NTAPI
1406 HalGetInterruptVector(IN INTERFACE_TYPE InterfaceType,
1407 IN ULONG BusNumber,
1408 IN ULONG BusInterruptLevel,
1409 IN ULONG BusInterruptVector,
1410 OUT PKIRQL Irql,
1411 OUT PKAFFINITY Affinity)
1412 {
1413 PBUS_HANDLER Handler;
1414 ULONG Vector;
1415 PAGED_CODE();
1416
1417 /* Defaults */
1418 *Irql = 0;
1419 *Affinity = 0;
1420
1421 /* Find the handler */
1422 Handler = HalReferenceHandlerForBus(InterfaceType, BusNumber);
1423 if (!Handler) return 0;
1424
1425 /* Do the assignment */
1426 Vector = Handler->GetInterruptVector(Handler,
1427 Handler,
1428 BusInterruptLevel,
1429 BusInterruptVector,
1430 Irql,
1431 Affinity);
1432 if ((Vector != IRQ2VECTOR(BusInterruptLevel)) ||
1433 (*Irql != VECTOR2IRQL(IRQ2VECTOR(BusInterruptLevel))))
1434 {
1435 DPRINT1("Returning IRQL %lx, Vector %lx for Level/Vector: %lx/%lx\n",
1436 *Irql, Vector, BusInterruptLevel, BusInterruptVector);
1437 DPRINT1("Old HAL would've returned IRQL %lx and Vector %lx\n",
1438 VECTOR2IRQL(IRQ2VECTOR(BusInterruptLevel)),
1439 IRQ2VECTOR(BusInterruptLevel));
1440 }
1441
1442 /* Dereference the handler and return */
1443 HalDereferenceBusHandler(Handler);
1444 return Vector;
1445 }
1446
1447 /*
1448 * @implemented
1449 */
1450 ULONG
1451 NTAPI
1452 HalSetBusData(IN BUS_DATA_TYPE BusDataType,
1453 IN ULONG BusNumber,
1454 IN ULONG SlotNumber,
1455 IN PVOID Buffer,
1456 IN ULONG Length)
1457 {
1458 /* Call the extended function */
1459 return HalSetBusDataByOffset(BusDataType,
1460 BusNumber,
1461 SlotNumber,
1462 Buffer,
1463 0,
1464 Length);
1465 }
1466
1467 /*
1468 * @implemented
1469 */
1470 ULONG
1471 NTAPI
1472 HalSetBusDataByOffset(IN BUS_DATA_TYPE BusDataType,
1473 IN ULONG BusNumber,
1474 IN ULONG SlotNumber,
1475 IN PVOID Buffer,
1476 IN ULONG Offset,
1477 IN ULONG Length)
1478 {
1479 PBUS_HANDLER Handler;
1480 ULONG Status;
1481
1482 /* Find the handler */
1483 Handler = HaliReferenceHandlerForConfigSpace(BusDataType, BusNumber);
1484 if (!Handler) return 0;
1485
1486 /* Do the assignment */
1487 Status = Handler->SetBusData(Handler,
1488 Handler,
1489 SlotNumber,
1490 Buffer,
1491 Offset,
1492 Length);
1493
1494 /* Dereference the handler and return */
1495 HalDereferenceBusHandler(Handler);
1496 return Status;
1497 }
1498
1499 /*
1500 * @implemented
1501 */
1502 BOOLEAN
1503 NTAPI
1504 HalTranslateBusAddress(IN INTERFACE_TYPE InterfaceType,
1505 IN ULONG BusNumber,
1506 IN PHYSICAL_ADDRESS BusAddress,
1507 IN OUT PULONG AddressSpace,
1508 OUT PPHYSICAL_ADDRESS TranslatedAddress)
1509 {
1510 /* Look as the bus type */
1511 if (InterfaceType == PCIBus)
1512 {
1513 /* Call the PCI registered function */
1514 return HalPciTranslateBusAddress(PCIBus,
1515 BusNumber,
1516 BusAddress,
1517 AddressSpace,
1518 TranslatedAddress);
1519 }
1520 else
1521 {
1522 /* Call the bus handler */
1523 return HaliTranslateBusAddress(InterfaceType,
1524 BusNumber,
1525 BusAddress,
1526 AddressSpace,
1527 TranslatedAddress);
1528 }
1529 }
1530
1531 /* EOF */