Some more NDK fixes
[reactos.git] / reactos / include / ntos / haltypes.h
1 /* $Id$
2 *
3 * COPYRIGHT: See COPYING in the top level directory
4 * PROJECT: ReactOS kernel
5 * FILE: include/ddk/haltypes.h
6 * PURPOSE: HAL provided defintions for device drivers
7 * PROGRAMMER: David Welch (welch@mcmail.com)
8 * REVISION HISTORY:
9 * 23/06/98: Taken from linux system.h
10 */
11
12
13 #ifndef __INCLUDE_NTOS_HALTYPES_H
14 #define __INCLUDE_NTOS_HALTYPES_H
15
16 #ifndef STDCALL_FUNC
17 #define STDCALL_FUNC(a) (STDCALL a)
18 #endif
19 #ifndef FASTCALL_FUNC
20 #define FASTCALL_FUNC(a) (FASTCALL a)
21 #endif
22
23 #include "types.h"
24
25
26 /* HalReturnToFirmware */
27 typedef enum _FIRMWARE_ENTRY
28 {
29 HalHaltRoutine,
30 HalPowerDownRoutine,
31 HalRestartRoutine,
32 HalRebootRoutine,
33 HalInteractiveModeRoutine,
34 HalMaximumRoutine
35 } FIRMWARE_REENTRY, *PFIRMWARE_REENTRY;
36
37 #ifndef __USE_W32API
38
39 enum
40 {
41 DEVICE_DESCRIPTION_VERSION,
42 DEVICE_DESCRIPTION_VERSION1,
43 };
44
45 /*
46 * DMA speed specifiers
47 */
48 typedef enum _DMA_SPEED
49 {
50 Compatible,
51 TypeA,
52 TypeB,
53 TypeC,
54 TypeF,
55 MaximumDmaSpeed
56 } DMA_SPEED, *PDMA_SPEED;
57
58 /*
59 * DMA width specifiers
60 */
61 typedef enum _DMA_WIDTH
62 {
63 Width8Bits,
64 Width16Bits,
65 Width32Bits,
66 MaximumDmaWidth
67 } DMA_WIDTH, *PDMA_WIDTH;
68
69 /*
70 * PURPOSE: Types for HalGetBusData
71 */
72 typedef enum _BUS_DATA_TYPE
73 {
74 ConfigurationSpaceUndefined = -1,
75 Cmos,
76 EisaConfiguration,
77 Pos,
78 CbusConfiguration,
79 PCIConfiguration,
80 VMEConfiguration,
81 NuBusConfiguration,
82 PCMCIAConfiguration,
83 MPIConfiguration,
84 MPSAConfiguration,
85 PNPISAConfiguration,
86 MaximumBusDataType,
87 } BUS_DATA_TYPE, *PBUS_DATA_TYPE;
88
89 typedef struct _DEVICE_DESCRIPTION
90 {
91 ULONG Version;
92 BOOLEAN Master;
93 BOOLEAN ScatterGather;
94 BOOLEAN DemandMode;
95 BOOLEAN AutoInitialize;
96 BOOLEAN Dma32BitAddresses;
97 BOOLEAN IgnoreCount;
98 BOOLEAN Reserved1; /* Must be false */
99 BOOLEAN Dma64BitAddresses;
100 ULONG BusNumber;
101 ULONG DmaChannel;
102 INTERFACE_TYPE InterfaceType;
103 DMA_WIDTH DmaWidth;
104 DMA_SPEED DmaSpeed;
105 ULONG MaximumLength;
106 ULONG DmaPort;
107 } DEVICE_DESCRIPTION, *PDEVICE_DESCRIPTION;
108
109
110 /* PCI bus definitions */
111
112 #define PCI_TYPE0_ADDRESSES 6
113 #define PCI_TYPE1_ADDRESSES 2
114 #define PCI_TYPE2_ADDRESSES 5
115
116 typedef struct _PCI_COMMON_CONFIG
117 {
118 USHORT VendorID; /* read-only */
119 USHORT DeviceID; /* read-only */
120 USHORT Command;
121 USHORT Status;
122 UCHAR RevisionID; /* read-only */
123 UCHAR ProgIf; /* read-only */
124 UCHAR SubClass; /* read-only */
125 UCHAR BaseClass; /* read-only */
126 UCHAR CacheLineSize; /* read-only */
127 UCHAR LatencyTimer; /* read-only */
128 UCHAR HeaderType; /* read-only */
129 UCHAR BIST;
130 union
131 {
132 struct _PCI_HEADER_TYPE_0
133 {
134 ULONG BaseAddresses[PCI_TYPE0_ADDRESSES];
135 ULONG CIS;
136 USHORT SubVendorID;
137 USHORT SubSystemID;
138 ULONG ROMBaseAddress;
139 ULONG Reserved2[2];
140
141 UCHAR InterruptLine;
142 UCHAR InterruptPin; /* read-only */
143 UCHAR MinimumGrant; /* read-only */
144 UCHAR MaximumLatency; /* read-only */
145 } type0;
146
147 /* PCI to PCI Bridge */
148 struct _PCI_HEADER_TYPE_1
149 {
150 ULONG BaseAddresses[PCI_TYPE1_ADDRESSES];
151 UCHAR PrimaryBus;
152 UCHAR SecondaryBus;
153 UCHAR SubordinateBus;
154 UCHAR SecondaryLatency;
155 UCHAR IOBase;
156 UCHAR IOLimit;
157 USHORT SecondaryStatus;
158 USHORT MemoryBase;
159 USHORT MemoryLimit;
160 USHORT PrefetchBase;
161 USHORT PrefetchLimit;
162 ULONG PrefetchBaseUpper32;
163 ULONG PrefetchLimitUpper32;
164 USHORT IOBaseUpper16;
165 USHORT IOLimitUpper16;
166 UCHAR CapabilitiesPtr;
167 UCHAR Reserved1[3];
168 ULONG ROMBaseAddress;
169 UCHAR InterruptLine;
170 UCHAR InterruptPin;
171 USHORT BridgeControl;
172 } type1;
173
174 /* PCI to CARDBUS Bridge */
175 struct _PCI_HEADER_TYPE_2
176 {
177 ULONG SocketRegistersBaseAddress;
178 UCHAR CapabilitiesPtr;
179 UCHAR Reserved;
180 USHORT SecondaryStatus;
181 UCHAR PrimaryBus;
182 UCHAR SecondaryBus;
183 UCHAR SubordinateBus;
184 UCHAR SecondaryLatency;
185 struct
186 {
187 ULONG Base;
188 ULONG Limit;
189 } Range[PCI_TYPE2_ADDRESSES-1];
190 UCHAR InterruptLine;
191 UCHAR InterruptPin;
192 USHORT BridgeControl;
193 } type2;
194 } u;
195 UCHAR DeviceSpecific[192];
196 } PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
197
198 #define PCI_COMMON_HDR_LENGTH (FIELD_OFFSET (PCI_COMMON_CONFIG, DeviceSpecific))
199
200 #define PCI_MAX_DEVICES 32
201 #define PCI_MAX_FUNCTION 8
202 #define PCI_MAX_BRIDGE_NUMBER 0xFF
203
204 #define PCI_INVALID_VENDORID 0xFFFF
205
206 /* Bit encodings for PCI_COMMON_CONFIG.HeaderType */
207
208 #define PCI_MULTIFUNCTION 0x80
209 #define PCI_DEVICE_TYPE 0x00
210 #define PCI_BRIDGE_TYPE 0x01
211 #define PCI_CARDBUS_BRIDGE_TYPE 0x02
212
213 #define PCI_CONFIGURATION_TYPE(PciData) \
214 (((PPCI_COMMON_CONFIG)(PciData))->HeaderType & ~PCI_MULTIFUNCTION)
215
216 #define PCI_MULTIFUNCTION_DEVICE(PciData) \
217 ((((PPCI_COMMON_CONFIG)(PciData))->HeaderType & PCI_MULTIFUNCTION) != 0)
218
219
220 /* Bit encodings for PCI_COMMON_CONFIG.Command */
221
222 #define PCI_ENABLE_IO_SPACE 0x0001
223 #define PCI_ENABLE_MEMORY_SPACE 0x0002
224 #define PCI_ENABLE_BUS_MASTER 0x0004
225 #define PCI_ENABLE_SPECIAL_CYCLES 0x0008
226 #define PCI_ENABLE_WRITE_AND_INVALIDATE 0x0010
227 #define PCI_ENABLE_VGA_COMPATIBLE_PALETTE 0x0020
228 #define PCI_ENABLE_PARITY 0x0040
229 #define PCI_ENABLE_WAIT_CYCLE 0x0080
230 #define PCI_ENABLE_SERR 0x0100
231 #define PCI_ENABLE_FAST_BACK_TO_BACK 0x0200
232
233
234 /* Bit encodings for PCI_COMMON_CONFIG.Status */
235
236 #define PCI_STATUS_FAST_BACK_TO_BACK 0x0080
237 #define PCI_STATUS_DATA_PARITY_DETECTED 0x0100
238 #define PCI_STATUS_DEVSEL 0x0600 /* 2 bits wide */
239 #define PCI_STATUS_SIGNALED_TARGET_ABORT 0x0800
240 #define PCI_STATUS_RECEIVED_TARGET_ABORT 0x1000
241 #define PCI_STATUS_RECEIVED_MASTER_ABORT 0x2000
242 #define PCI_STATUS_SIGNALED_SYSTEM_ERROR 0x4000
243 #define PCI_STATUS_DETECTED_PARITY_ERROR 0x8000
244
245
246 /* PCI device classes */
247
248 #define PCI_CLASS_PRE_20 0x00
249 #define PCI_CLASS_MASS_STORAGE_CTLR 0x01
250 #define PCI_CLASS_NETWORK_CTLR 0x02
251 #define PCI_CLASS_DISPLAY_CTLR 0x03
252 #define PCI_CLASS_MULTIMEDIA_DEV 0x04
253 #define PCI_CLASS_MEMORY_CTLR 0x05
254 #define PCI_CLASS_BRIDGE_DEV 0x06
255 #define PCI_CLASS_SIMPLE_COMMS_CTLR 0x07
256 #define PCI_CLASS_BASE_SYSTEM_DEV 0x08
257 #define PCI_CLASS_INPUT_DEV 0x09
258 #define PCI_CLASS_DOCKING_STATION 0x0a
259 #define PCI_CLASS_PROCESSOR 0x0b
260 #define PCI_CLASS_SERIAL_BUS_CTLR 0x0c
261
262
263 /* PCI device subclasses for class 0 */
264
265 #define PCI_SUBCLASS_PRE_20_NON_VGA 0x00
266 #define PCI_SUBCLASS_PRE_20_VGA 0x01
267
268
269 /* PCI device subclasses for class 1 (mass storage controllers)*/
270
271 #define PCI_SUBCLASS_MSC_SCSI_BUS_CTLR 0x00
272 #define PCI_SUBCLASS_MSC_IDE_CTLR 0x01
273 #define PCI_SUBCLASS_MSC_FLOPPY_CTLR 0x02
274 #define PCI_SUBCLASS_MSC_IPI_CTLR 0x03
275 #define PCI_SUBCLASS_MSC_RAID_CTLR 0x04
276 #define PCI_SUBCLASS_MSC_OTHER 0x80
277
278
279 /* PCI device subclasses for class 2 (network controllers)*/
280
281 #define PCI_SUBCLASS_NET_ETHERNET_CTLR 0x00
282 #define PCI_SUBCLASS_NET_TOKEN_RING_CTLR 0x01
283 #define PCI_SUBCLASS_NET_FDDI_CTLR 0x02
284 #define PCI_SUBCLASS_NET_ATM_CTLR 0x03
285 #define PCI_SUBCLASS_NET_OTHER 0x80
286
287
288 /* PCI device subclasses for class 3 (display controllers)*/
289
290 #define PCI_SUBCLASS_VID_VGA_CTLR 0x00
291 #define PCI_SUBCLASS_VID_XGA_CTLR 0x01
292 #define PCI_SUBLCASS_VID_3D_CTLR 0x02
293 #define PCI_SUBCLASS_VID_OTHER 0x80
294
295
296 /* PCI device subclasses for class 4 (multimedia device)*/
297
298 #define PCI_SUBCLASS_MM_VIDEO_DEV 0x00
299 #define PCI_SUBCLASS_MM_AUDIO_DEV 0x01
300 #define PCI_SUBCLASS_MM_TELEPHONY_DEV 0x02
301 #define PCI_SUBCLASS_MM_OTHER 0x80
302
303
304 /* PCI device subclasses for class 5 (memory controller)*/
305
306 #define PCI_SUBCLASS_MEM_RAM 0x00
307 #define PCI_SUBCLASS_MEM_FLASH 0x01
308 #define PCI_SUBCLASS_MEM_OTHER 0x80
309
310
311 /* PCI device subclasses for class 6 (bridge device)*/
312
313 #define PCI_SUBCLASS_BR_HOST 0x00
314 #define PCI_SUBCLASS_BR_ISA 0x01
315 #define PCI_SUBCLASS_BR_EISA 0x02
316 #define PCI_SUBCLASS_BR_MCA 0x03
317 #define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04
318 #define PCI_SUBCLASS_BR_PCMCIA 0x05
319 #define PCI_SUBCLASS_BR_NUBUS 0x06
320 #define PCI_SUBCLASS_BR_CARDBUS 0x07
321 #define PCI_SUBCLASS_BR_OTHER 0x80
322
323
324 /* PCI device subclasses for class C (serial bus controller)*/
325
326 #define PCI_SUBCLASS_SB_IEEE1394 0x00
327 #define PCI_SUBCLASS_SB_ACCESS 0x01
328 #define PCI_SUBCLASS_SB_SSA 0x02
329 #define PCI_SUBCLASS_SB_USB 0x03
330 #define PCI_SUBCLASS_SB_FIBRE_CHANNEL 0x04
331
332
333 /* Bit encodes for PCI_COMMON_CONFIG.u.type0.BaseAddresses */
334
335 #define PCI_ADDRESS_IO_SPACE 0x00000001
336 #define PCI_ADDRESS_MEMORY_TYPE_MASK 0x00000006
337 #define PCI_ADDRESS_MEMORY_PREFETCHABLE 0x00000008
338
339 #define PCI_ADDRESS_IO_ADDRESS_MASK 0xfffffffc
340 #define PCI_ADDRESS_MEMORY_ADDRESS_MASK 0xfffffff0
341 #define PCI_ADDRESS_ROM_ADDRESS_MASK 0xfffff800
342
343 #define PCI_TYPE_32BIT 0
344 #define PCI_TYPE_20BIT 2
345 #define PCI_TYPE_64BIT 4
346
347
348 /* Bit encodes for PCI_COMMON_CONFIG.u.type0.ROMBaseAddresses */
349
350 #define PCI_ROMADDRESS_ENABLED 0x00000001
351
352
353
354 typedef struct _PCI_SLOT_NUMBER
355 {
356 union
357 {
358 struct
359 {
360 ULONG DeviceNumber:5;
361 ULONG FunctionNumber:3;
362 ULONG Reserved:24;
363 } bits;
364 ULONG AsULONG;
365 } u;
366 } PCI_SLOT_NUMBER, *PPCI_SLOT_NUMBER;
367
368 typedef enum _RESOURCE_TRANSLATION_DIRECTION {
369 TranslateChildToParent,
370 TranslateParentToChild
371 } RESOURCE_TRANSLATION_DIRECTION;
372
373 typedef NTSTATUS STDCALL_FUNC
374 (*PTRANSLATE_RESOURCE_HANDLER)(IN PVOID Context,
375 IN PCM_PARTIAL_RESOURCE_DESCRIPTOR Source,
376 IN RESOURCE_TRANSLATION_DIRECTION Direction,
377 IN ULONG AlternativesCount, OPTIONAL
378 IN IO_RESOURCE_DESCRIPTOR Alternatives[], OPTIONAL
379 IN PDEVICE_OBJECT PhysicalDeviceObject,
380 OUT PCM_PARTIAL_RESOURCE_DESCRIPTOR Target
381 );
382
383 typedef NTSTATUS STDCALL_FUNC
384 (*PTRANSLATE_RESOURCE_REQUIREMENTS_HANDLER)(IN PVOID Context,
385 IN PIO_RESOURCE_DESCRIPTOR Source,
386 IN PDEVICE_OBJECT PhysicalDeviceObject,
387 OUT PULONG TargetCount,
388 OUT PIO_RESOURCE_DESCRIPTOR *Target);
389
390 typedef struct _TRANSLATOR_INTERFACE {
391 USHORT Size;
392 USHORT Version;
393 PVOID Context;
394 PINTERFACE_REFERENCE InterfaceReference;
395 PINTERFACE_DEREFERENCE InterfaceDereference;
396 PTRANSLATE_RESOURCE_HANDLER TranslateResources;
397 PTRANSLATE_RESOURCE_REQUIREMENTS_HANDLER TranslateResourceRequirements;
398 } TRANSLATOR_INTERFACE, *PTRANSLATOR_INTERFACE;
399
400
401 /* Hal dispatch table */
402
403 typedef enum _HAL_QUERY_INFORMATION_CLASS
404 {
405 HalInstalledBusInformation,
406 HalProfileSourceInformation,
407 HalSystemDockInformation,
408 HalPowerInformation,
409 HalProcessorSpeedInformation,
410 HalCallbackInformation,
411 HalMapRegisterInformation,
412 HalMcaLogInformation,
413 HalFrameBufferCachingInformation,
414 HalDisplayBiosInformation
415 /* information levels >= 0x8000000 reserved for OEM use */
416 } HAL_QUERY_INFORMATION_CLASS, *PHAL_QUERY_INFORMATION_CLASS;
417
418
419 typedef enum _HAL_SET_INFORMATION_CLASS
420 {
421 HalProfileSourceInterval,
422 HalProfileSourceInterruptHandler,
423 HalMcaRegisterDriver
424 } HAL_SET_INFORMATION_CLASS, *PHAL_SET_INFORMATION_CLASS;
425
426
427 typedef struct _BUS_HANDLER *PBUS_HANDLER;
428 typedef struct _DEVICE_HANDLER_OBJECT *PDEVICE_HANDLER_OBJECT;
429
430
431 typedef BOOLEAN STDCALL_FUNC
432 (*PHAL_RESET_DISPLAY_PARAMETERS)(ULONG Columns, ULONG Rows);
433
434 #endif /* __USE_W32API */
435 /* Control codes of HalDeviceControl function */
436 #define BCTL_EJECT 0x0001
437 #define BCTL_QUERY_DEVICE_ID 0x0002
438 #define BCTL_QUERY_DEVICE_UNIQUE_ID 0x0003
439 #define BCTL_QUERY_DEVICE_CAPABILITIES 0x0004
440 #define BCTL_QUERY_DEVICE_RESOURCES 0x0005
441 #define BCTL_QUERY_DEVICE_RESOURCE_REQUIREMENTS 0x0006
442 #define BCTL_QUERY_EJECT 0x0007
443 #define BCTL_SET_LOCK 0x0008
444 #define BCTL_SET_POWER 0x0009
445 #define BCTL_SET_RESUME 0x000A
446 #define BCTL_SET_DEVICE_RESOURCES 0x000B
447
448 /* Defines for BCTL structures */
449 typedef struct
450 {
451 BOOLEAN PowerSupported;
452 BOOLEAN ResumeSupported;
453 BOOLEAN LockSupported;
454 BOOLEAN EjectSupported;
455 BOOLEAN Removable;
456 } BCTL_DEVICE_CAPABILITIES, *PBCTL_DEVICE_CAPABILITIES;
457
458 #ifndef __USE_W32API
459 typedef struct _DEVICE_CONTROL_CONTEXT
460 {
461 NTSTATUS Status;
462 PDEVICE_HANDLER_OBJECT DeviceHandler;
463 PDEVICE_OBJECT DeviceObject;
464 ULONG ControlCode;
465 PVOID Buffer;
466 PULONG BufferLength;
467 PVOID Context;
468 } DEVICE_CONTROL_CONTEXT, *PDEVICE_CONTROL_CONTEXT;
469
470 typedef struct _PM_DISPATCH_TABLE {
471 ULONG Signature;
472 ULONG Version;
473 PVOID Function[1];
474 } PM_DISPATCH_TABLE, *PPM_DISPATCH_TABLE;
475
476 typedef VOID STDCALL_FUNC
477 (*PDEVICE_CONTROL_COMPLETION)(IN PDEVICE_CONTROL_CONTEXT ControlContext);
478
479 typedef NTSTATUS STDCALL_FUNC
480 (*pHalDeviceControl)(IN PDEVICE_HANDLER_OBJECT DeviceHandler,
481 IN PDEVICE_OBJECT DeviceObject,
482 IN ULONG ControlCode,
483 IN OUT PVOID Buffer OPTIONAL,
484 IN OUT PULONG BufferLength OPTIONAL,
485 IN PVOID Context,
486 IN PDEVICE_CONTROL_COMPLETION CompletionRoutine);
487
488 typedef VOID FASTCALL_FUNC
489 (*pHalExamineMBR)(IN PDEVICE_OBJECT DeviceObject,
490 IN ULONG SectorSize,
491 IN ULONG MBRTypeIdentifier,
492 OUT PVOID *Buffer);
493
494 typedef VOID FASTCALL_FUNC
495 (*pHalIoAssignDriveLetters)(IN struct _LOADER_PARAMETER_BLOCK *LoaderBlock,
496 IN PSTRING NtDeviceName,
497 OUT PUCHAR NtSystemPath,
498 OUT PSTRING NtSystemPathString);
499
500 typedef NTSTATUS FASTCALL_FUNC
501 (*pHalIoReadPartitionTable)(IN PDEVICE_OBJECT DeviceObject,
502 IN ULONG SectorSize,
503 IN BOOLEAN ReturnRecognizedPartitions,
504 OUT PDRIVE_LAYOUT_INFORMATION *PartitionBuffer);
505
506 typedef NTSTATUS FASTCALL_FUNC
507 (*pHalIoSetPartitionInformation)(IN PDEVICE_OBJECT DeviceObject,
508 IN ULONG SectorSize,
509 IN ULONG PartitionNumber,
510 IN ULONG PartitionType);
511
512 typedef NTSTATUS FASTCALL_FUNC
513 (*pHalIoWritePartitionTable)(IN PDEVICE_OBJECT DeviceObject,
514 IN ULONG SectorSize,
515 IN ULONG SectorsPerTrack,
516 IN ULONG NumberOfHeads,
517 IN PDRIVE_LAYOUT_INFORMATION PartitionBuffer);
518
519 typedef PBUS_HANDLER FASTCALL_FUNC
520 (*pHalHandlerForBus)(IN INTERFACE_TYPE InterfaceType,
521 IN ULONG BusNumber);
522
523 typedef VOID FASTCALL_FUNC
524 (*pHalReferenceBusHandler)(IN PBUS_HANDLER BusHandler);
525
526 typedef NTSTATUS STDCALL_FUNC
527 (*pHalQuerySystemInformation)(IN HAL_QUERY_INFORMATION_CLASS InformationClass,
528 IN ULONG BufferSize,
529 IN OUT PVOID Buffer,
530 OUT PULONG ReturnedLength);
531
532
533 typedef NTSTATUS STDCALL_FUNC
534 (*pHalSetSystemInformation)(IN HAL_SET_INFORMATION_CLASS InformationClass,
535 IN ULONG BufferSize,
536 IN PVOID Buffer);
537
538
539 typedef NTSTATUS STDCALL_FUNC
540 (*pHalQueryBusSlots)(IN PBUS_HANDLER BusHandler,
541 IN ULONG BufferSize,
542 OUT PULONG SlotNumbers,
543 OUT PULONG ReturnedLength);
544
545 typedef NTSTATUS STDCALL_FUNC
546 (*pHalInitPnpDriver)(VOID);
547
548 typedef NTSTATUS STDCALL_FUNC
549 (*pHalInitPowerManagement)(IN PPM_DISPATCH_TABLE PmDriverDispatchTable,
550 OUT PPM_DISPATCH_TABLE *PmHalDispatchTable);
551
552 typedef struct _DMA_ADAPTER * STDCALL_FUNC
553 (*pHalGetDmaAdapter)(IN PVOID Context,
554 IN struct _DEVICE_DESCRIPTION *DeviceDescriptor,
555 OUT PULONG NumberOfMapRegisters);
556
557 typedef NTSTATUS STDCALL_FUNC
558 (*pHalGetInterruptTranslator)(IN INTERFACE_TYPE ParentInterfaceType,
559 IN ULONG ParentBusNumber,
560 IN INTERFACE_TYPE BridgeInterfaceType,
561 IN USHORT Size,
562 IN USHORT Version,
563 OUT PTRANSLATOR_INTERFACE Translator,
564 OUT PULONG BridgeBusNumber);
565
566 typedef NTSTATUS STDCALL_FUNC
567 (*pHalStartMirroring)(VOID);
568
569 typedef NTSTATUS STDCALL_FUNC
570 (*pHalEndMirroring)(IN ULONG PassNumber);
571
572 typedef NTSTATUS STDCALL_FUNC
573 (*pHalMirrorPhysicalMemory)(IN PHYSICAL_ADDRESS PhysicalAddress,
574 IN LARGE_INTEGER NumberOfBytes);
575
576 typedef NTSTATUS STDCALL_FUNC
577 (*pHalMirrorVerify)(IN PHYSICAL_ADDRESS PhysicalAddress,
578 IN LARGE_INTEGER NumberOfBytes);
579
580 typedef VOID STDCALL_FUNC
581 (*pHalEndOfBoot)(VOID);
582
583
584 typedef struct {
585 ULONG Version;
586 pHalQuerySystemInformation HalQuerySystemInformation;
587 pHalSetSystemInformation HalSetSystemInformation;
588 pHalQueryBusSlots HalQueryBusSlots;
589 ULONG Spare1;
590 pHalExamineMBR HalExamineMBR;
591 pHalIoAssignDriveLetters HalIoAssignDriveLetters;
592 pHalIoReadPartitionTable HalIoReadPartitionTable;
593 pHalIoSetPartitionInformation HalIoSetPartitionInformation;
594 pHalIoWritePartitionTable HalIoWritePartitionTable;
595
596 pHalHandlerForBus HalReferenceHandlerForBus;
597 pHalReferenceBusHandler HalReferenceBusHandler;
598 pHalReferenceBusHandler HalDereferenceBusHandler;
599
600 pHalInitPnpDriver HalInitPnpDriver;
601 pHalInitPowerManagement HalInitPowerManagement;
602
603 pHalGetDmaAdapter HalGetDmaAdapter;
604 pHalGetInterruptTranslator HalGetInterruptTranslator;
605
606 pHalStartMirroring HalStartMirroring;
607 pHalEndMirroring HalEndMirroring;
608 pHalMirrorPhysicalMemory HalMirrorPhysicalMemory;
609 pHalEndOfBoot HalEndOfBoot;
610 pHalMirrorVerify HalMirrorVerify;
611
612 } HAL_DISPATCH, *PHAL_DISPATCH;
613
614 #ifdef __NTOSKRNL__
615 extern HAL_DISPATCH EXPORTED HalDispatchTable;
616 #else
617 extern PHAL_DISPATCH IMPORTED HalDispatchTable;
618 #endif
619
620 #endif /* !__USE_W32API */
621
622 #ifndef __USE_W32API
623 #ifdef __NTOSKRNL__
624 #define HALDISPATCH (&HalDispatchTable)
625 #else
626 #define HALDISPATCH ((PHAL_DISPATCH)&HalDispatchTable)
627 #endif
628
629
630 #define HAL_DISPATCH_VERSION 3
631 #define HalDispatchTableVersion HALDISPATCH->Version
632 #define HalQuerySystemInformation HALDISPATCH->HalQuerySystemInformation
633 #define HalSetSystemInformation HALDISPATCH->HalSetSystemInformation
634 #define HalQueryBusSlots HALDISPATCH->HalQueryBusSlots
635 #define HalDeviceControl HALDISPATCH->HalDeviceControl
636 #define HalExamineMBR HALDISPATCH->HalExamineMBR
637 #define HalIoAssignDriveLetters HALDISPATCH->HalIoAssignDriveLetters
638 #define HalIoReadPartitionTable HALDISPATCH->HalIoReadPartitionTable
639 #define HalIoSetPartitionInformation HALDISPATCH->HalIoSetPartitionInformation
640 #define HalIoWritePartitionTable HALDISPATCH->HalIoWritePartitionTable
641 #define HalReferenceHandlerForBus HALDISPATCH->HalReferenceHandlerForBus
642 #define HalReferenceBusHandler HALDISPATCH->HalReferenceBusHandler
643 #define HalDereferenceBusHandler HALDISPATCH->HalDereferenceBusHandler
644
645
646 #endif /* !__USE_W32API */
647
648 /* Hal private dispatch table */
649
650 typedef struct _HAL_PRIVATE_DISPATCH
651 {
652 ULONG Version;
653 } HAL_PRIVATE_DISPATCH, *PHAL_PRIVATE_DISPATCH;
654
655 #ifdef __NTOSKRNL__
656 extern HAL_PRIVATE_DISPATCH EXPORTED HalPrivateDispatchTable;
657 #else
658 extern PHAL_PRIVATE_DISPATCH IMPORTED HalPrivateDispatchTable;
659 #endif
660
661 #define HAL_PRIVATE_DISPATCH_VERSION 1
662
663
664
665 /*
666 * Kernel debugger section
667 */
668
669 typedef struct _KD_PORT_INFORMATION
670 {
671 ULONG ComPort;
672 ULONG BaudRate;
673 ULONG BaseAddress;
674 } KD_PORT_INFORMATION, *PKD_PORT_INFORMATION;
675
676
677 #ifdef __NTHAL__
678 extern ULONG EXPORTED KdComPortInUse;
679 #else
680 extern ULONG IMPORTED KdComPortInUse;
681 #endif
682
683 #endif /* __INCLUDE_DDK_HALTYPES_H */
684
685 /* EOF */