reactos/include/reactos/drivers/serial/ns16550.h

   1 /*
   2  * PROJECT:         ReactOS ComPort Library
   3  * LICENSE:         BSD - See COPYING.ARM in the top level directory
   4  * FILE:            include/reactos/drivers/serial/ns16550.h
   5  * PURPOSE:         Header for National Semiconductor 16550 UART
   6  * PROGRAMMERS:     ReactOS Portable Systems Group
   7  */
   8
   9 /* INCLUDES *******************************************************************/
  10
  11 #pragma once
  12
  13 /* Note: These definitions are the internal definitions used by Microsoft serial
  14    driver (see src/kernel/serial/serial.h in WDK source code). Linux uses its own,
  15    as do most other OS.
  16 */
  17
  18 #if !defined(SERIAL_REGISTER_STRIDE)
  19 #define SERIAL_REGISTER_STRIDE 1
  20 #endif
  21
  22 #define RECEIVE_BUFFER_REGISTER    ((ULONG)((0x00)*SERIAL_REGISTER_STRIDE))
  23 #define TRANSMIT_HOLDING_REGISTER  ((ULONG)((0x00)*SERIAL_REGISTER_STRIDE))
  24 #define INTERRUPT_ENABLE_REGISTER  ((ULONG)((0x01)*SERIAL_REGISTER_STRIDE))
  25 #define INTERRUPT_IDENT_REGISTER   ((ULONG)((0x02)*SERIAL_REGISTER_STRIDE))
  26 #define FIFO_CONTROL_REGISTER      ((ULONG)((0x02)*SERIAL_REGISTER_STRIDE))
  27 #define LINE_CONTROL_REGISTER      ((ULONG)((0x03)*SERIAL_REGISTER_STRIDE))
  28 #define MODEM_CONTROL_REGISTER     ((ULONG)((0x04)*SERIAL_REGISTER_STRIDE))
  29 #define LINE_STATUS_REGISTER       ((ULONG)((0x05)*SERIAL_REGISTER_STRIDE))
  30 #define MODEM_STATUS_REGISTER      ((ULONG)((0x06)*SERIAL_REGISTER_STRIDE))
  31 #define DIVISOR_LATCH_LSB          ((ULONG)((0x00)*SERIAL_REGISTER_STRIDE))
  32 #define DIVISOR_LATCH_MSB          ((ULONG)((0x01)*SERIAL_REGISTER_STRIDE))
  33 #define SERIAL_REGISTER_SPAN       ((ULONG)(7*SERIAL_REGISTER_STRIDE))
  34 #define SERIAL_STATUS_LENGTH       ((ULONG)(1*SERIAL_REGISTER_STRIDE))
  35
  36 #define SERIAL_DATA_LENGTH_5 0x00
  37 #define SERIAL_DATA_LENGTH_6 0x01
  38 #define SERIAL_DATA_LENGTH_7 0x02
  39 #define SERIAL_DATA_LENGTH_8 0x03
  40
  41 #define SERIAL_IER_RDA   0x01
  42 #define SERIAL_IER_THR   0x02
  43 #define SERIAL_IER_RLS   0x04
  44 #define SERIAL_IER_MS    0x08
  45
  46 #define SERIAL_IIR_RLS      0x06
  47 #define SERIAL_IIR_RDA      0x04
  48 #define SERIAL_IIR_CTI      0x0c
  49 #define SERIAL_IIR_THR      0x02
  50 #define SERIAL_IIR_MS       0x00
  51 #define SERIAL_IIR_FIFOS_ENABLED 0xc0
  52 #define SERIAL_IIR_NO_INTERRUPT_PENDING 0x01
  53 #define SERIAL_IIR_MUST_BE_ZERO 0x30
  54
  55 #define SERIAL_FCR_ENABLE     ((UCHAR)0x01)
  56 #define SERIAL_FCR_RCVR_RESET ((UCHAR)0x02)
  57 #define SERIAL_FCR_TXMT_RESET ((UCHAR)0x04)
  58
  59 #define SERIAL_1_BYTE_HIGH_WATER   ((UCHAR)0x00)
  60 #define SERIAL_4_BYTE_HIGH_WATER   ((UCHAR)0x40)
  61 #define SERIAL_8_BYTE_HIGH_WATER   ((UCHAR)0x80)
  62 #define SERIAL_14_BYTE_HIGH_WATER  ((UCHAR)0xc0)
  63
  64 #define SERIAL_LCR_DLAB     0x80
  65 #define SERIAL_LCR_BREAK    0x40
  66
  67 #define SERIAL_5_DATA       ((UCHAR)0x00)
  68 #define SERIAL_6_DATA       ((UCHAR)0x01)
  69 #define SERIAL_7_DATA       ((UCHAR)0x02)
  70 #define SERIAL_8_DATA       ((UCHAR)0x03)
  71 #define SERIAL_DATA_MASK    ((UCHAR)0x03)
  72
  73 #define SERIAL_1_STOP       ((UCHAR)0x00)
  74 #define SERIAL_1_5_STOP     ((UCHAR)0x04) // Only valid for 5 data bits
  75 #define SERIAL_2_STOP       ((UCHAR)0x04) // Not valid for 5 data bits
  76 #define SERIAL_STOP_MASK    ((UCHAR)0x04)
  77
  78 #define SERIAL_NONE_PARITY  ((UCHAR)0x00)
  79 #define SERIAL_ODD_PARITY   ((UCHAR)0x08)
  80 #define SERIAL_EVEN_PARITY  ((UCHAR)0x18)
  81 #define SERIAL_MARK_PARITY  ((UCHAR)0x28)
  82 #define SERIAL_SPACE_PARITY ((UCHAR)0x38)
  83 #define SERIAL_PARITY_MASK  ((UCHAR)0x38)
  84
  85 #define SERIAL_MCR_DTR            0x01
  86 #define SERIAL_MCR_RTS            0x02
  87 #define SERIAL_MCR_OUT1           0x04
  88 #define SERIAL_MCR_OUT2           0x08
  89 #define SERIAL_MCR_LOOP           0x10
  90 #define SERIAL_MCR_TL16C550CAFE   0x20
  91
  92 #define SERIAL_LSR_DR       0x01
  93 #define SERIAL_LSR_OE       0x02
  94 #define SERIAL_LSR_PE       0x04
  95 #define SERIAL_LSR_FE       0x08
  96 #define SERIAL_LSR_BI       0x10
  97 #define SERIAL_LSR_THRE     0x20
  98 #define SERIAL_LSR_TEMT     0x40
  99 #define SERIAL_LSR_FIFOERR  0x80
 100
 101 #define SERIAL_MSR_DCTS     0x01
 102 #define SERIAL_MSR_DDSR     0x02
 103 #define SERIAL_MSR_TERI     0x04
 104 #define SERIAL_MSR_DDCD     0x08
 105 #define SERIAL_MSR_CTS      0x10
 106 #define SERIAL_MSR_DSR      0x20
 107 #define SERIAL_MSR_RI       0x40
 108 #define SERIAL_MSR_DCD      0x80