reactos/lib/fast486/common.c

   1 /*
   2  * Fast486 386/486 CPU Emulation Library
   3  * common.c
   4  *
   5  * Copyright (C) 2015 Aleksandar Andrejevic <theflash AT sdf DOT lonestar DOT org>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  20  */
  21
  22 /* INCLUDES *******************************************************************/
  23
  24 #include <windef.h>
  25
  26 // #define NDEBUG
  27 #include <debug.h>
  28
  29 #include <fast486.h>
  30 #include "common.h"
  31
  32 /* PUBLIC FUNCTIONS ***********************************************************/
  33
  34 BOOLEAN
  35 Fast486ReadMemory(PFAST486_STATE State,
  36                   FAST486_SEG_REGS SegmentReg,
  37                   ULONG Offset,
  38                   BOOLEAN InstFetch,
  39                   PVOID Buffer,
  40                   ULONG Size)
  41 {
  42     ULONG LinearAddress;
  43     PFAST486_SEG_REG CachedDescriptor;
  44
  45     ASSERT(SegmentReg < FAST486_NUM_SEG_REGS);
  46
  47     /* Get the cached descriptor */
  48     CachedDescriptor = &State->SegmentRegs[SegmentReg];
  49
  50     if (InstFetch || !CachedDescriptor->DirConf)
  51     {
  52         if ((Offset + Size - 1) > CachedDescriptor->Limit)
  53         {
  54             /* Read beyond limit */
  55             Fast486Exception(State, FAST486_EXCEPTION_GP);
  56             return FALSE;
  57         }
  58     }
  59     else
  60     {
  61         if (Offset < CachedDescriptor->Limit)
  62         {
  63             /* Read beyond limit */
  64             Fast486Exception(State, FAST486_EXCEPTION_GP);
  65             return FALSE;
  66         }
  67     }
  68
  69     /* Check for protected mode */
  70     if (State->ControlRegisters[FAST486_REG_CR0] & FAST486_CR0_PE)
  71     {
  72         /* Privilege checks */
  73
  74         if (!CachedDescriptor->Present)
  75         {
  76             Fast486Exception(State, FAST486_EXCEPTION_NP);
  77             return FALSE;
  78         }
  79
  80         if ((!InstFetch && (CachedDescriptor->Rpl > CachedDescriptor->Dpl))
  81             || (Fast486GetCurrentPrivLevel(State) > CachedDescriptor->Dpl))
  82         {
  83             Fast486Exception(State, FAST486_EXCEPTION_GP);
  84             return FALSE;
  85         }
  86
  87         if (InstFetch)
  88         {
  89             if (!CachedDescriptor->Executable)
  90             {
  91                 /* Data segment not executable */
  92                 Fast486Exception(State, FAST486_EXCEPTION_GP);
  93                 return FALSE;
  94             }
  95         }
  96         else
  97         {
  98             if (CachedDescriptor->Executable && (!CachedDescriptor->ReadWrite))
  99             {
 100                 /* Code segment not readable */
 101                 Fast486Exception(State, FAST486_EXCEPTION_GP);
 102                 return FALSE;
 103             }
 104         }
 105     }
 106
 107     /* Find the linear address */
 108     LinearAddress = CachedDescriptor->Base + Offset;
 109
 110 #ifndef FAST486_NO_PREFETCH
 111     if (InstFetch && ((Offset + FAST486_CACHE_SIZE - 1) <= CachedDescriptor->Limit))
 112     {
 113         State->PrefetchAddress = LinearAddress;
 114
 115         if ((State->ControlRegisters[FAST486_REG_CR0] & FAST486_CR0_PG)
 116             && (PAGE_OFFSET(State->PrefetchAddress) > (FAST486_PAGE_SIZE - FAST486_CACHE_SIZE)))
 117         {
 118             /* We mustn't prefetch across a page boundary */
 119             State->PrefetchAddress = PAGE_ALIGN(State->PrefetchAddress)
 120                                      | (FAST486_PAGE_SIZE - FAST486_CACHE_SIZE);
 121
 122             if ((LinearAddress - State->PrefetchAddress + Size) >= FAST486_CACHE_SIZE)
 123             {
 124                 /* We can't prefetch without possibly violating page permissions */
 125                 State->PrefetchValid = FALSE;
 126                 return Fast486ReadLinearMemory(State, LinearAddress, Buffer, Size);
 127             }
 128         }
 129
 130         /* Prefetch */
 131         if (Fast486ReadLinearMemory(State,
 132                                     State->PrefetchAddress,
 133                                     State->PrefetchCache,
 134                                     FAST486_CACHE_SIZE))
 135         {
 136             State->PrefetchValid = TRUE;
 137
 138             RtlMoveMemory(Buffer,
 139                           &State->PrefetchCache[LinearAddress - State->PrefetchAddress],
 140                           Size);
 141             return TRUE;
 142         }
 143         else
 144         {
 145             State->PrefetchValid = FALSE;
 146             return FALSE;
 147         }
 148     }
 149     else
 150 #endif
 151     {
 152         /* Read from the linear address */
 153         return Fast486ReadLinearMemory(State, LinearAddress, Buffer, Size);
 154     }
 155 }
 156
 157 BOOLEAN
 158 Fast486WriteMemory(PFAST486_STATE State,
 159                    FAST486_SEG_REGS SegmentReg,
 160                    ULONG Offset,
 161                    PVOID Buffer,
 162                    ULONG Size)
 163 {
 164     ULONG LinearAddress;
 165     PFAST486_SEG_REG CachedDescriptor;
 166
 167     ASSERT(SegmentReg < FAST486_NUM_SEG_REGS);
 168
 169     /* Get the cached descriptor */
 170     CachedDescriptor = &State->SegmentRegs[SegmentReg];
 171
 172     if (!CachedDescriptor->DirConf)
 173     {
 174         if ((Offset + Size - 1) > CachedDescriptor->Limit)
 175         {
 176             /* Write beyond limit */
 177             Fast486Exception(State, FAST486_EXCEPTION_GP);
 178             return FALSE;
 179         }
 180     }
 181     else
 182     {
 183         if (Offset < CachedDescriptor->Limit)
 184         {
 185             /* Read beyond limit */
 186             Fast486Exception(State, FAST486_EXCEPTION_GP);
 187             return FALSE;
 188         }
 189     }
 190
 191     /* Check for protected mode */
 192     if (State->ControlRegisters[FAST486_REG_CR0] & FAST486_CR0_PE)
 193     {
 194         /* Privilege checks */
 195
 196         if (!CachedDescriptor->Present)
 197         {
 198             Fast486Exception(State, FAST486_EXCEPTION_NP);
 199             return FALSE;
 200         }
 201
 202         if ((CachedDescriptor->Rpl > CachedDescriptor->Dpl)
 203             || (Fast486GetCurrentPrivLevel(State) > CachedDescriptor->Dpl))
 204         {
 205             Fast486Exception(State, FAST486_EXCEPTION_GP);
 206             return FALSE;
 207         }
 208
 209         if (CachedDescriptor->Executable)
 210         {
 211             /* Code segment not writable */
 212             Fast486Exception(State, FAST486_EXCEPTION_GP);
 213             return FALSE;
 214         }
 215         else if (!CachedDescriptor->ReadWrite)
 216         {
 217             /* Data segment not writeable */
 218             Fast486Exception(State, FAST486_EXCEPTION_GP);
 219             return FALSE;
 220         }
 221     }
 222
 223     /* Find the linear address */
 224     LinearAddress = CachedDescriptor->Base + Offset;
 225
 226 #ifndef FAST486_NO_PREFETCH
 227     if (State->PrefetchValid
 228         && (LinearAddress >= State->PrefetchAddress)
 229         && ((LinearAddress + Size) <= (State->PrefetchAddress + FAST486_CACHE_SIZE)))
 230     {
 231         /* Update the prefetch */
 232         RtlMoveMemory(&State->PrefetchCache[LinearAddress - State->PrefetchAddress],
 233                       Buffer,
 234                       min(Size, FAST486_CACHE_SIZE + State->PrefetchAddress - LinearAddress));
 235     }
 236 #endif
 237
 238     /* Write to the linear address */
 239     return Fast486WriteLinearMemory(State, LinearAddress, Buffer, Size);
 240 }
 241
 242 static inline BOOLEAN
 243 FASTCALL
 244 Fast486GetIntVector(PFAST486_STATE State,
 245                     UCHAR Number,
 246                     PFAST486_IDT_ENTRY IdtEntry)
 247 {
 248     /* Check for protected mode */
 249     if (State->ControlRegisters[FAST486_REG_CR0] & FAST486_CR0_PE)
 250     {
 251         /* Read from the IDT */
 252         if (!Fast486ReadLinearMemory(State,
 253                                      State->Idtr.Address
 254                                      + Number * sizeof(*IdtEntry),
 255                                      IdtEntry,
 256                                      sizeof(*IdtEntry)))
 257         {
 258             /* Exception occurred */
 259             return FALSE;
 260         }
 261     }
 262     else
 263     {
 264         /* Read from the real-mode IVT */
 265         ULONG FarPointer;
 266
 267         /* Paging is always disabled in real mode */
 268         State->MemReadCallback(State,
 269                                State->Idtr.Address
 270                                + Number * sizeof(FarPointer),
 271                                &FarPointer,
 272                                sizeof(FarPointer));
 273
 274         /* Fill a fake IDT entry */
 275         IdtEntry->Offset = LOWORD(FarPointer);
 276         IdtEntry->Selector = HIWORD(FarPointer);
 277         IdtEntry->Zero = 0;
 278         IdtEntry->Type = FAST486_IDT_INT_GATE;
 279         IdtEntry->Storage = FALSE;
 280         IdtEntry->Dpl = 0;
 281         IdtEntry->Present = TRUE;
 282         IdtEntry->OffsetHigh = 0;
 283     }
 284
 285     return TRUE;
 286 }
 287
 288 static inline BOOLEAN
 289 FASTCALL
 290 Fast486InterruptInternal(PFAST486_STATE State,
 291                          PFAST486_IDT_ENTRY IdtEntry,
 292                          BOOLEAN PushErrorCode,
 293                          ULONG ErrorCode)
 294 {
 295     BOOLEAN GateSize = (IdtEntry->Type == FAST486_IDT_INT_GATE_32) ||
 296                        (IdtEntry->Type == FAST486_IDT_TRAP_GATE_32);
 297     USHORT OldCs = State->SegmentRegs[FAST486_REG_CS].Selector;
 298     ULONG OldEip = State->InstPtr.Long;
 299     ULONG OldFlags = State->Flags.Long;
 300     UCHAR OldCpl = State->Cpl;
 301
 302     /* Check for protected mode */
 303     if (State->ControlRegisters[FAST486_REG_CR0] & FAST486_CR0_PE)
 304     {
 305         USHORT OldSs = State->SegmentRegs[FAST486_REG_SS].Selector;
 306         ULONG OldEsp = State->GeneralRegs[FAST486_REG_ESP].Long;
 307
 308         if (IdtEntry->Type == FAST486_TASK_GATE_SIGNATURE)
 309         {
 310             /* Task call */
 311             return Fast486TaskSwitch(State, FAST486_TASK_CALL, IdtEntry->Selector);
 312         }
 313
 314         /* Check if the interrupt handler is more privileged or if we're in V86 mode */
 315         if ((OldCpl > GET_SEGMENT_RPL(IdtEntry->Selector)) || State->Flags.Vm)
 316         {
 317             FAST486_TSS Tss;
 318
 319             /* Read the TSS */
 320             if (!Fast486ReadLinearMemory(State,
 321                                          State->TaskReg.Base,
 322                                          &Tss,
 323                                          sizeof(Tss)))
 324             {
 325                 /* Exception occurred */
 326                 return FALSE;
 327             }
 328
 329             /* Switch to the new privilege level */
 330             State->Cpl = GET_SEGMENT_RPL(IdtEntry->Selector);
 331
 332             /* Check the new (higher) privilege level */
 333             switch (State->Cpl)
 334             {
 335                 case 0:
 336                 {
 337                     if (!Fast486LoadSegment(State, FAST486_REG_SS, Tss.Ss0))
 338                     {
 339                         /* Exception occurred */
 340                         return FALSE;
 341                     }
 342                     State->GeneralRegs[FAST486_REG_ESP].Long = Tss.Esp0;
 343
 344                     break;
 345                 }
 346
 347                 case 1:
 348                 {
 349                     if (!Fast486LoadSegment(State, FAST486_REG_SS, Tss.Ss1))
 350                     {
 351                         /* Exception occurred */
 352                         return FALSE;
 353                     }
 354                     State->GeneralRegs[FAST486_REG_ESP].Long = Tss.Esp1;
 355
 356                     break;
 357                 }
 358
 359                 case 2:
 360                 {
 361                     if (!Fast486LoadSegment(State, FAST486_REG_SS, Tss.Ss2))
 362                     {
 363                         /* Exception occurred */
 364                         return FALSE;
 365                     }
 366                     State->GeneralRegs[FAST486_REG_ESP].Long = Tss.Esp2;
 367
 368                     break;
 369                 }
 370
 371                 default:
 372                 {
 373                     /* Should never reach here! */
 374                     ASSERT(FALSE);
 375                 }
 376             }
 377         }
 378
 379         /* Load new CS */
 380         if (!Fast486LoadSegment(State, FAST486_REG_CS, IdtEntry->Selector))
 381         {
 382             /* An exception occurred during the jump */
 383             return FALSE;
 384         }
 385
 386         if (GateSize)
 387         {
 388             /* 32-bit code segment, use EIP */
 389             State->InstPtr.Long = MAKELONG(IdtEntry->Offset, IdtEntry->OffsetHigh);
 390         }
 391         else
 392         {
 393             /* 16-bit code segment, use IP */
 394             State->InstPtr.LowWord = IdtEntry->Offset;
 395         }
 396
 397         /* Check if the interrupt handler is more privileged or we're in VM86 mode (again) */
 398         if ((OldCpl > GET_SEGMENT_RPL(IdtEntry->Selector)) || State->Flags.Vm)
 399         {
 400             if (State->Flags.Vm)
 401             {
 402                 /* Clear the VM flag */
 403                 State->Flags.Vm = FALSE;
 404
 405                 /* Push GS, FS, DS and ES */
 406                 if (!Fast486StackPush(State, State->SegmentRegs[FAST486_REG_GS].Selector)) return FALSE;
 407                 if (!Fast486StackPush(State, State->SegmentRegs[FAST486_REG_FS].Selector)) return FALSE;
 408                 if (!Fast486StackPush(State, State->SegmentRegs[FAST486_REG_DS].Selector)) return FALSE;
 409                 if (!Fast486StackPush(State, State->SegmentRegs[FAST486_REG_ES].Selector)) return FALSE;
 410
 411                 /* Now load them with NULL selectors, since they are useless in protected mode */
 412                 if (!Fast486LoadSegment(State, FAST486_REG_GS, 0)) return FALSE;
 413                 if (!Fast486LoadSegment(State, FAST486_REG_FS, 0)) return FALSE;
 414                 if (!Fast486LoadSegment(State, FAST486_REG_DS, 0)) return FALSE;
 415                 if (!Fast486LoadSegment(State, FAST486_REG_ES, 0)) return FALSE;
 416             }
 417
 418             /* Push SS selector */
 419             if (!Fast486StackPushInternal(State, GateSize, OldSs)) return FALSE;
 420
 421             /* Push the stack pointer */
 422             if (!Fast486StackPushInternal(State, GateSize, OldEsp)) return FALSE;
 423         }
 424     }
 425     else
 426     {
 427         /* Load new CS */
 428         if (!Fast486LoadSegment(State, FAST486_REG_CS, IdtEntry->Selector))
 429         {
 430             /* An exception occurred during the jump */
 431             return FALSE;
 432         }
 433
 434         /* Set the new IP */
 435         State->InstPtr.LowWord = IdtEntry->Offset;
 436     }
 437
 438     /* Push EFLAGS */
 439     if (!Fast486StackPushInternal(State, GateSize, OldFlags)) return FALSE;
 440
 441     /* Push CS selector */
 442     if (!Fast486StackPushInternal(State, GateSize, OldCs)) return FALSE;
 443
 444     /* Push the instruction pointer */
 445     if (!Fast486StackPushInternal(State, GateSize, OldEip)) return FALSE;
 446
 447     if (PushErrorCode)
 448     {
 449         /* Push the error code */
 450         if (!Fast486StackPushInternal(State, GateSize, ErrorCode)) return FALSE;
 451     }
 452
 453     if ((IdtEntry->Type == FAST486_IDT_INT_GATE)
 454         || (IdtEntry->Type == FAST486_IDT_INT_GATE_32))
 455     {
 456         /* Disable interrupts after a jump to an interrupt gate handler */
 457         State->Flags.If = FALSE;
 458     }
 459
 460     return TRUE;
 461 }
 462
 463 BOOLEAN
 464 FASTCALL
 465 Fast486PerformInterrupt(PFAST486_STATE State,
 466                         UCHAR Number)
 467 {
 468     FAST486_IDT_ENTRY IdtEntry;
 469
 470     /* Get the interrupt vector */
 471     if (!Fast486GetIntVector(State, Number, &IdtEntry))
 472     {
 473         /* Exception occurred */
 474         return FALSE;
 475     }
 476
 477     /* Perform the interrupt */
 478     if (!Fast486InterruptInternal(State, &IdtEntry, FALSE, 0))
 479     {
 480         /* Exception occurred */
 481         return FALSE;
 482     }
 483
 484     return TRUE;
 485 }
 486
 487 VOID
 488 FASTCALL
 489 Fast486ExceptionWithErrorCode(PFAST486_STATE State,
 490                               FAST486_EXCEPTIONS ExceptionCode,
 491                               ULONG ErrorCode)
 492 {
 493     FAST486_IDT_ENTRY IdtEntry;
 494
 495     /* Increment the exception count */
 496     State->ExceptionCount++;
 497
 498     /* Check if the exception occurred more than once */
 499     if (State->ExceptionCount > 1)
 500     {
 501         /* Then this is a double fault */
 502         ExceptionCode = FAST486_EXCEPTION_DF;
 503     }
 504
 505     /* Check if this is a triple fault */
 506     if (State->ExceptionCount == 3)
 507     {
 508         DPRINT("Fast486ExceptionWithErrorCode(%04X:%08X) -- Triple fault\n",
 509                State->SegmentRegs[FAST486_REG_CS].Selector,
 510                State->InstPtr.Long);
 511
 512         /* Reset the CPU */
 513         Fast486Reset(State);
 514         return;
 515     }
 516
 517     /* Clear the prefix flags */
 518     State->PrefixFlags = 0;
 519
 520     /* Restore the IP to the saved IP */
 521     State->InstPtr = State->SavedInstPtr;
 522
 523     /* Get the interrupt vector */
 524     if (!Fast486GetIntVector(State, ExceptionCode, &IdtEntry))
 525     {
 526         /*
 527          * If this function failed, that means Fast486Exception
 528          * was called again, so just return in this case.
 529          */
 530         return;
 531     }
 532
 533     /* Perform the interrupt */
 534     if (!Fast486InterruptInternal(State,
 535                                   &IdtEntry,
 536                                   EXCEPTION_HAS_ERROR_CODE(ExceptionCode)
 537                                   && (State->ControlRegisters[FAST486_REG_CR0] & FAST486_CR0_PE),
 538                                   ErrorCode))
 539     {
 540         /*
 541          * If this function failed, that means Fast486Exception
 542          * was called again, so just return in this case.
 543          */
 544         return;
 545     }
 546
 547     /* Reset the exception count */
 548     State->ExceptionCount = 0;
 549 }
 550
 551 BOOLEAN
 552 FASTCALL
 553 Fast486TaskSwitch(PFAST486_STATE State, FAST486_TASK_SWITCH_TYPE Type, USHORT Selector)
 554 {
 555     ULONG NewTssAddress;
 556     ULONG NewTssLimit;
 557     FAST486_TSS OldTss;
 558     FAST486_TSS NewTss;
 559     FAST486_SYSTEM_DESCRIPTOR NewTssDescriptor;
 560
 561     /* Read the old TSS */
 562     if (!Fast486ReadLinearMemory(State,
 563                                  State->TaskReg.Base,
 564                                  &OldTss,
 565                                  sizeof(OldTss)))
 566     {
 567         /* Exception occurred */
 568         return FALSE;
 569     }
 570
 571     /* If this is a task return, use the linked previous selector */
 572     if (Type == FAST486_TASK_RETURN) Selector = LOWORD(OldTss.Link);
 573
 574     /* Make sure the entry exists in the GDT (not LDT!) */
 575     if ((GET_SEGMENT_INDEX(Selector) == 0)
 576         || (Selector & SEGMENT_TABLE_INDICATOR)
 577         || GET_SEGMENT_INDEX(Selector) >= (State->Gdtr.Size + 1u))
 578     {
 579         Fast486ExceptionWithErrorCode(State, FAST486_EXCEPTION_TS, Selector);
 580         return FALSE;
 581     }
 582
 583     /* Get the TSS descriptor from the GDT */
 584     if (!Fast486ReadLinearMemory(State,
 585                                  State->Gdtr.Address + GET_SEGMENT_INDEX(Selector),
 586                                  &NewTssDescriptor,
 587                                  sizeof(NewTssDescriptor)))
 588     {
 589         /* Exception occurred */
 590         return FALSE;
 591     }
 592
 593     if (!NewTssDescriptor.Present)
 594     {
 595         /* Incoming task TSS not present */
 596         Fast486ExceptionWithErrorCode(State, FAST486_EXCEPTION_NP, Selector);
 597         return FALSE;
 598     }
 599
 600     /* Calculate the linear address of the new TSS */
 601     NewTssAddress = NewTssDescriptor.Base;
 602     NewTssAddress |= NewTssDescriptor.BaseMid << 16;
 603     NewTssAddress |= NewTssDescriptor.BaseHigh << 24;
 604
 605     /* Calculate the limit of the new TSS */
 606     NewTssLimit = NewTssDescriptor.Limit | (NewTssDescriptor.LimitHigh << 16);
 607
 608     if (NewTssDescriptor.Granularity)
 609     {
 610         NewTssLimit <<= 12;
 611         NewTssLimit |= 0x00000FFF;
 612     }
 613
 614     if (NewTssLimit < sizeof(FAST486_TSS))
 615     {
 616         /* TSS limit too small */
 617         Fast486ExceptionWithErrorCode(State, FAST486_EXCEPTION_TS, Selector);
 618         return FALSE;
 619     }
 620
 621     /*
 622      * The incoming task shouldn't be busy if we're executing it as a
 623      * new task, and it should be busy if we're returning to it.
 624      */
 625     if (((NewTssDescriptor.Signature != FAST486_TSS_SIGNATURE)
 626         || (Type == FAST486_TASK_RETURN))
 627         && ((NewTssDescriptor.Signature != FAST486_BUSY_TSS_SIGNATURE)
 628         || (Type != FAST486_TASK_RETURN)))
 629     {
 630         Fast486ExceptionWithErrorCode(State, FAST486_EXCEPTION_GP, Selector);
 631         return FALSE;
 632     }
 633
 634     /* Read the new TSS */
 635     if (!Fast486ReadLinearMemory(State,
 636                                  NewTssAddress,
 637                                  &NewTss,
 638                                  sizeof(NewTss)))
 639     {
 640         /* Exception occurred */
 641         return FALSE;
 642     }
 643
 644     if (Type != FAST486_TASK_CALL)
 645     {
 646         /* Clear the busy bit of the outgoing task */
 647         FAST486_SYSTEM_DESCRIPTOR OldTssDescriptor;
 648
 649         if (!Fast486ReadLinearMemory(State,
 650                                      State->Gdtr.Address
 651                                      + GET_SEGMENT_INDEX(State->TaskReg.Selector),
 652                                      &OldTssDescriptor,
 653                                      sizeof(OldTssDescriptor)))
 654         {
 655             /* Exception occurred */
 656             return FALSE;
 657         }
 658
 659         OldTssDescriptor.Signature = FAST486_TSS_SIGNATURE;
 660
 661         if (!Fast486WriteLinearMemory(State,
 662                                       State->Gdtr.Address
 663                                       + GET_SEGMENT_INDEX(State->TaskReg.Selector),
 664                                       &OldTssDescriptor,
 665                                       sizeof(OldTssDescriptor)))
 666         {
 667             /* Exception occurred */
 668             return FALSE;
 669         }
 670     }
 671     else
 672     {
 673         /* Store the link */
 674         NewTss.Link = State->TaskReg.Selector;
 675     }
 676
 677     /* Save the current task into the TSS */
 678     OldTss.Cr3 = State->ControlRegisters[FAST486_REG_CR3];
 679     OldTss.Eip = State->InstPtr.Long;
 680     OldTss.Eflags = State->Flags.Long;
 681     OldTss.Eax = State->GeneralRegs[FAST486_REG_EAX].Long;
 682     OldTss.Ecx = State->GeneralRegs[FAST486_REG_ECX].Long;
 683     OldTss.Edx = State->GeneralRegs[FAST486_REG_EDX].Long;
 684     OldTss.Ebx = State->GeneralRegs[FAST486_REG_EBX].Long;
 685     OldTss.Esp = State->GeneralRegs[FAST486_REG_ESP].Long;
 686     OldTss.Ebp = State->GeneralRegs[FAST486_REG_EBP].Long;
 687     OldTss.Esi = State->GeneralRegs[FAST486_REG_ESI].Long;
 688     OldTss.Edi = State->GeneralRegs[FAST486_REG_EDI].Long;
 689     OldTss.Es = State->SegmentRegs[FAST486_REG_ES].Selector;
 690     OldTss.Cs = State->SegmentRegs[FAST486_REG_CS].Selector;
 691     OldTss.Ss = State->SegmentRegs[FAST486_REG_SS].Selector;
 692     OldTss.Ds = State->SegmentRegs[FAST486_REG_DS].Selector;
 693     OldTss.Fs = State->SegmentRegs[FAST486_REG_FS].Selector;
 694     OldTss.Gs = State->SegmentRegs[FAST486_REG_GS].Selector;
 695     OldTss.Ldtr = State->Ldtr.Selector;
 696
 697     /* Write back the old TSS */
 698     if (!Fast486WriteLinearMemory(State,
 699                                   State->TaskReg.Base,
 700                                   &OldTss,
 701                                   sizeof(OldTss)))
 702     {
 703         /* Exception occurred */
 704         return FALSE;
 705     }
 706
 707     /* Mark the new task as busy */
 708     NewTssDescriptor.Signature = FAST486_BUSY_TSS_SIGNATURE;
 709
 710     /* Write back the new TSS descriptor */
 711     if (!Fast486WriteLinearMemory(State,
 712                                   State->Gdtr.Address + GET_SEGMENT_INDEX(Selector),
 713                                   &NewTssDescriptor,
 714                                   sizeof(NewTssDescriptor)))
 715     {
 716         /* Exception occurred */
 717         return FALSE;
 718     }
 719
 720     /* Set the task switch bit */
 721     State->ControlRegisters[FAST486_REG_CR0] |= FAST486_CR0_TS;
 722
 723     /* Load the task register with the new values */
 724     State->TaskReg.Selector = Selector;
 725     State->TaskReg.Base = NewTssAddress;
 726     State->TaskReg.Limit = NewTssLimit;
 727
 728     /* Change the page directory */
 729     State->ControlRegisters[FAST486_REG_CR3] = NewTss.Cr3;
 730
 731     /* Flush the TLB */
 732     if (State->Tlb) RtlZeroMemory(State->Tlb, NUM_TLB_ENTRIES * sizeof(ULONG));
 733
 734     /* Update the CPL */
 735     State->Cpl = GET_SEGMENT_RPL(NewTss.Cs);
 736
 737 #ifndef FAST486_NO_PREFETCH
 738     /* Context switching invalidates the prefetch */
 739     State->PrefetchValid = FALSE;
 740 #endif
 741
 742     /* Update the CPL */
 743     State->Cpl = GET_SEGMENT_RPL(NewTss.Cs);
 744
 745     /* Load the registers */
 746     State->InstPtr.Long = State->SavedInstPtr.Long = NewTss.Eip;
 747     State->Flags.Long = NewTss.Eflags;
 748     State->GeneralRegs[FAST486_REG_EAX].Long = NewTss.Eax;
 749     State->GeneralRegs[FAST486_REG_ECX].Long = NewTss.Ecx;
 750     State->GeneralRegs[FAST486_REG_EDX].Long = NewTss.Edx;
 751     State->GeneralRegs[FAST486_REG_EBX].Long = NewTss.Ebx;
 752     State->GeneralRegs[FAST486_REG_ESP].Long = NewTss.Esp;
 753     State->GeneralRegs[FAST486_REG_EBP].Long = NewTss.Ebp;
 754     State->GeneralRegs[FAST486_REG_ESI].Long = NewTss.Esi;
 755     State->GeneralRegs[FAST486_REG_EDI].Long = NewTss.Edi;
 756
 757     /* Set the NT flag if nesting */
 758     if (Type == FAST486_TASK_CALL) State->Flags.Nt = TRUE;
 759
 760     if (GET_SEGMENT_INDEX(NewTss.Ldtr) != 0)
 761     {
 762         BOOLEAN Valid;
 763         FAST486_SYSTEM_DESCRIPTOR GdtEntry;
 764
 765         if (NewTss.Ldtr & SEGMENT_TABLE_INDICATOR)
 766         {
 767             /* This selector doesn't point to the GDT */
 768             Fast486ExceptionWithErrorCode(State, FAST486_EXCEPTION_TS, NewTss.Ldtr);
 769             return FALSE;
 770         }
 771
 772         if (!Fast486ReadDescriptorEntry(State,
 773                                         NewTss.Ldtr,
 774                                         &Valid,
 775                                         (PFAST486_GDT_ENTRY)&GdtEntry))
 776         {
 777             /* Exception occurred */
 778             return FALSE;
 779         }
 780
 781         if (!Valid)
 782         {
 783             /* Invalid selector */
 784             Fast486ExceptionWithErrorCode(State, FAST486_EXCEPTION_TS, NewTss.Ldtr);
 785             return FALSE;
 786         }
 787
 788         if (GdtEntry.Signature != FAST486_LDT_SIGNATURE)
 789         {
 790             /* This is not an LDT descriptor */
 791             Fast486ExceptionWithErrorCode(State, FAST486_EXCEPTION_TS, NewTss.Ldtr);
 792             return FALSE;
 793         }
 794
 795         if (!GdtEntry.Present)
 796         {
 797             Fast486ExceptionWithErrorCode(State, FAST486_EXCEPTION_TS, NewTss.Ldtr);
 798             return FALSE;
 799         }
 800
 801         /* Update the LDTR */
 802         State->Ldtr.Selector = NewTss.Ldtr;
 803         State->Ldtr.Base = GdtEntry.Base | (GdtEntry.BaseMid << 16) | (GdtEntry.BaseHigh << 24);
 804         State->Ldtr.Limit = GdtEntry.Limit | (GdtEntry.LimitHigh << 16);
 805
 806         if (GdtEntry.Granularity)
 807         {
 808             State->Ldtr.Limit <<= 12;
 809             State->Ldtr.Limit |= 0x00000FFF;
 810         }
 811     }
 812     else
 813     {
 814         /* The LDT of this task is empty */
 815         RtlZeroMemory(&State->Ldtr, sizeof(State->Ldtr));
 816     }
 817
 818     /* Load the new segments */
 819     if (!Fast486LoadSegmentInternal(State,
 820                                     FAST486_REG_CS,
 821                                     NewTss.Cs,
 822                                     FAST486_EXCEPTION_TS))
 823     {
 824         return FALSE;
 825     }
 826
 827     if (!Fast486LoadSegmentInternal(State,
 828                                     FAST486_REG_SS,
 829                                     NewTss.Ss,
 830                                     FAST486_EXCEPTION_TS))
 831     {
 832         return FALSE;
 833     }
 834
 835     if (!Fast486LoadSegmentInternal(State,
 836                                     FAST486_REG_ES,
 837                                     NewTss.Es,
 838                                     FAST486_EXCEPTION_TS))
 839     {
 840         return FALSE;
 841     }
 842
 843     if (!Fast486LoadSegmentInternal(State,
 844                                     FAST486_REG_DS,
 845                                     NewTss.Ds,
 846                                     FAST486_EXCEPTION_TS))
 847     {
 848         return FALSE;
 849     }
 850
 851     if (!Fast486LoadSegmentInternal(State,
 852                                     FAST486_REG_FS,
 853                                     NewTss.Fs,
 854                                     FAST486_EXCEPTION_TS))
 855     {
 856         return FALSE;
 857     }
 858
 859     if (!Fast486LoadSegmentInternal(State,
 860                                     FAST486_REG_GS,
 861                                     NewTss.Gs,
 862                                     FAST486_EXCEPTION_TS))
 863     {
 864         return FALSE;
 865     }
 866
 867     return TRUE;
 868 }
 869
 870 BOOLEAN
 871 FASTCALL
 872 Fast486CallGate(PFAST486_STATE State,
 873                 PFAST486_CALL_GATE Gate,
 874                 BOOLEAN Call)
 875 {
 876     BOOLEAN Valid;
 877     FAST486_GDT_ENTRY NewCodeSegment;
 878     BOOLEAN GateSize = (Gate->Type == FAST486_CALL_GATE_SIGNATURE);
 879     FAST486_TSS Tss;
 880     USHORT OldCs = State->SegmentRegs[FAST486_REG_CS].Selector;
 881     ULONG OldEip = State->InstPtr.Long;
 882     USHORT OldCpl = State->Cpl;
 883     USHORT OldSs = State->SegmentRegs[FAST486_REG_SS].Selector;
 884     ULONG OldEsp = State->GeneralRegs[FAST486_REG_ESP].Long;
 885     ULONG ParamBuffer[32]; /* Maximum possible size - 32 DWORDs */
 886     PULONG LongParams = (PULONG)ParamBuffer;
 887     PUSHORT ShortParams = (PUSHORT)ParamBuffer;
 888
 889     if (!Gate->Selector)
 890     {
 891         /* The code segment is NULL */
 892         Fast486Exception(State, FAST486_EXCEPTION_GP);
 893         return FALSE;
 894     }
 895
 896     if (!Fast486ReadDescriptorEntry(State, Gate->Selector, &Valid, &NewCodeSegment))
 897     {
 898         /* Exception occurred */
 899         return FALSE;
 900     }
 901
 902     if (!Valid || (NewCodeSegment.Dpl > Fast486GetCurrentPrivLevel(State)))
 903     {
 904         /* Code segment invalid */
 905         Fast486ExceptionWithErrorCode(State, FAST486_EXCEPTION_GP, Gate->Selector);
 906         return FALSE;
 907     }
 908
 909     if (Call && Gate->ParamCount)
 910     {
 911         /* Read the parameters */
 912         if (!Fast486ReadMemory(State,
 913                                FAST486_REG_SS,
 914                                OldEsp,
 915                                FALSE,
 916                                ParamBuffer,
 917                                Gate->ParamCount * sizeof(ULONG)))
 918         {
 919             /* Exception occurred */
 920             return FALSE;
 921         }
 922     }
 923
 924     /* Check if the new code segment is more privileged */
 925     if (NewCodeSegment.Dpl < OldCpl)
 926     {
 927         if (Call)
 928         {
 929             /* Read the TSS */
 930             if (!Fast486ReadLinearMemory(State,
 931                                          State->TaskReg.Base,
 932                                          &Tss,
 933                                          sizeof(Tss)))
 934             {
 935                 /* Exception occurred */
 936                 return FALSE;
 937             }
 938
 939             /* Switch to the new privilege level */
 940             State->Cpl = NewCodeSegment.Dpl;
 941
 942             /* Check the new (higher) privilege level */
 943             switch (State->Cpl)
 944             {
 945                 case 0:
 946                 {
 947                     if (!Fast486LoadSegment(State, FAST486_REG_SS, Tss.Ss0))
 948                     {
 949                         /* Exception occurred */
 950                         return FALSE;
 951                     }
 952                     State->GeneralRegs[FAST486_REG_ESP].Long = Tss.Esp0;
 953
 954                     break;
 955                 }
 956
 957                 case 1:
 958                 {
 959                     if (!Fast486LoadSegment(State, FAST486_REG_SS, Tss.Ss1))
 960                     {
 961                         /* Exception occurred */
 962                         return FALSE;
 963                     }
 964                     State->GeneralRegs[FAST486_REG_ESP].Long = Tss.Esp1;
 965
 966                     break;
 967                 }
 968
 969                 case 2:
 970                 {
 971                     if (!Fast486LoadSegment(State, FAST486_REG_SS, Tss.Ss2))
 972                     {
 973                         /* Exception occurred */
 974                         return FALSE;
 975                     }
 976                     State->GeneralRegs[FAST486_REG_ESP].Long = Tss.Esp2;
 977
 978                     break;
 979                 }
 980
 981                 default:
 982                 {
 983                     /* Should never reach here! */
 984                     ASSERT(FALSE);
 985                 }
 986             }
 987         }
 988         else if (!NewCodeSegment.DirConf)
 989         {
 990             /* This is not allowed for jumps */
 991             Fast486ExceptionWithErrorCode(State, FAST486_EXCEPTION_GP, Gate->Selector);
 992             return FALSE;
 993         }
 994     }
 995
 996     /* Load new CS */
 997     if (!Fast486LoadSegment(State, FAST486_REG_CS, Gate->Selector))
 998     {
 999         /* An exception occurred during the jump */
1000         return FALSE;
1001     }
1002
1003     /* Set the instruction pointer */
1004     if (GateSize) State->InstPtr.Long = MAKELONG(Gate->Offset, Gate->OffsetHigh);
1005     else State->InstPtr.Long = Gate->Offset;
1006
1007     if (Call)
1008     {
1009         INT i;
1010
1011         /* Check if the new code segment is more privileged (again) */
1012         if (NewCodeSegment.Dpl < OldCpl)
1013         {
1014             /* Push SS selector */
1015             if (!Fast486StackPushInternal(State, GateSize, OldSs)) return FALSE;
1016
1017             /* Push stack pointer */
1018             if (!Fast486StackPushInternal(State, GateSize, OldEsp)) return FALSE;
1019         }
1020
1021         /* Push the parameters in reverse order */
1022         for (i = Gate->ParamCount - 1; i >= 0; i--)
1023         {
1024             if (!Fast486StackPushInternal(State,
1025                                           GateSize,
1026                                           GateSize ? LongParams[i] : ShortParams[i]))
1027             {
1028                 /* Exception occurred */
1029                 return FALSE;
1030             }
1031         }
1032
1033         /* Push the parameter count */
1034         if (!Fast486StackPushInternal(State, GateSize, Gate->ParamCount)) return FALSE;
1035
1036         /* Push CS selector */
1037         if (!Fast486StackPushInternal(State, GateSize, OldCs)) return FALSE;
1038
1039         /* Push the instruction pointer */
1040         if (!Fast486StackPushInternal(State, GateSize, OldEip)) return FALSE;
1041     }
1042
1043     return TRUE;
1044 }
1045
1046 /* EOF */