reactos/ntoskrnl/include/internal/amd64/mm.h

   1 /*
   2  * Lowlevel memory managment definitions
   3  */
   4
   5 #pragma once
   6
   7 /* Helper macros */
   8 #define PAGE_MASK(x)            ((x)&(~0xfff))
   9 #define PAE_PAGE_MASK(x)        ((x)&(~0xfffLL))
  10
  11 /* Memory layout base addresses */
  12 #define HYPER_SPACE                            0xFFFFF70000000000ULL
  13 #define HYPER_SPACE_END                        0xFFFFF77FFFFFFFFFULL
  14 #define MI_SESSION_SPACE_MINIMUM        (PVOID)0xFFFFF90000000000ULL
  15 #define MI_SESSION_VIEW_END             (PVOID)0xFFFFF97FFF000000ULL
  16 #define MI_SESSION_SPACE_END            (PVOID)0xFFFFF98000000000ULL
  17 #define MI_SYSTEM_PTE_START             (PVOID)0xFFFFFAA000000000ULL
  18 #define MI_PAGED_POOL_START             (PVOID)0xFFFFFA8000000000ULL
  19 #define MI_NON_PAGED_SYSTEM_START_MIN          0xFFFFFAA000000000ULL
  20 #define MI_PFN_DATABASE                 (PVOID)0xFFFFFAC000000000ULL
  21 #define MI_NONPAGED_POOL_END            (PVOID)0xFFFFFAE000000000ULL
  22 #define MI_DEBUG_MAPPING                (PVOID)0xFFFFFFFF80000000ULL // FIXME
  23 #define MI_HIGHEST_SYSTEM_ADDRESS       (PVOID)0xFFFFFFFFFFFFFFFFULL
  24 #define MI_SYSTEM_CACHE_WS_START        (PVOID)0xFFFFF78000001000ULL // CHECKME
  25
  26 #define MI_LOWEST_VAD_ADDRESS           (PVOID)0x000000007FF00000ULL
  27
  28 /* Memory sizes */
  29 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT)
  30 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING         ((19*1024*1024) >> PAGE_SHIFT)
  31 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST          ((32*1024*1024) >> PAGE_SHIFT)
  32 #define MI_MAX_INIT_NONPAGED_POOL_SIZE         (128ULL * 1024 * 1024 * 1024)
  33 #define MI_MAX_NONPAGED_POOL_SIZE              (128ULL * 1024 * 1024 * 1024)
  34 #define MI_MAX_FREE_PAGE_LISTS                 4
  35 #define MI_MIN_INIT_PAGED_POOLSIZE             (32 * 1024 * 1024)
  36 #define MI_SESSION_VIEW_SIZE                   (20 * 1024 * 1024)
  37 #define MI_SESSION_POOL_SIZE                   (16 * 1024 * 1024)
  38 #define MI_SESSION_IMAGE_SIZE                  (8 * 1024 * 1024)
  39 #define MI_SESSION_WORKING_SET_SIZE            (4 * 1024 * 1024)
  40 #define MI_SESSION_SIZE                        (MI_SESSION_VIEW_SIZE + \
  41                                                 MI_SESSION_POOL_SIZE + \
  42                                                 MI_SESSION_IMAGE_SIZE + \
  43                                                 MI_SESSION_WORKING_SET_SIZE)
  44 #define MI_SYSTEM_VIEW_SIZE                    (16 * 1024 * 1024)
  45 #define MI_NUMBER_SYSTEM_PTES 22000
  46
  47 #define MI_MIN_SECONDARY_COLORS                 8
  48 #define MI_SECONDARY_COLORS                     64
  49 #define MI_MAX_SECONDARY_COLORS                 1024
  50
  51 #define MM_HIGHEST_VAD_ADDRESS \
  52     (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
  53
  54 PULONG64
  55 FORCEINLINE
  56 MmGetPageDirectory(VOID)
  57 {
  58     return (PULONG64)__readcr3();
  59 }
  60
  61 PMMPTE
  62 FORCEINLINE
  63 MiAddressToPxe(PVOID Address)
  64 {
  65     ULONG64 Offset = (ULONG64)Address >> (PXI_SHIFT - 3);
  66     Offset &= PXI_MASK << 3;
  67     return (PMMPTE)(PXE_BASE + Offset);
  68 }
  69
  70 PMMPTE
  71 FORCEINLINE
  72 MiAddressToPpe(PVOID Address)
  73 {
  74     ULONG64 Offset = (ULONG64)Address >> (PPI_SHIFT - 3);
  75     Offset &= 0x3FFFF << 3;
  76     return (PMMPTE)(PPE_BASE + Offset);
  77 }
  78
  79 PMMPTE
  80 FORCEINLINE
  81 _MiAddressToPde(PVOID Address)
  82 {
  83     ULONG64 Offset = (ULONG64)Address >> (PDI_SHIFT - 3);
  84     Offset &= 0x7FFFFFF << 3;
  85     return (PMMPTE)(PDE_BASE + Offset);
  86 }
  87 #define MiAddressToPde(x) _MiAddressToPde((PVOID)(x))
  88
  89 PMMPTE
  90 FORCEINLINE
  91 _MiAddressToPte(PVOID Address)
  92 {
  93     ULONG64 Offset = (ULONG64)Address >> (PTI_SHIFT - 3);
  94     Offset &= 0xFFFFFFFFFULL << 3;
  95     return (PMMPTE)(PTE_BASE + Offset);
  96 }
  97 #define MiAddressToPte(x) _MiAddressToPte((PVOID)(x))
  98
  99 /* Convert a PTE into a corresponding address */
 100 PVOID
 101 FORCEINLINE
 102 MiPteToAddress(PMMPTE Pte)
 103 {
 104     /* Use signed math */
 105     LONG64 Temp = (LONG64)Pte;
 106     Temp <<= 25;
 107     Temp >>= 16;
 108     return (PVOID)Temp;
 109 }
 110
 111 BOOLEAN
 112 FORCEINLINE
 113 MiIsPdeForAddressValid(PVOID Address)
 114 {
 115     return ((MiAddressToPxe(Address)->u.Hard.Valid) &&
 116             (MiAddressToPpe(Address)->u.Hard.Valid) &&
 117             (MiAddressToPde(Address)->u.Hard.Valid));
 118 }
 119
 120 #define ADDR_TO_PAGE_TABLE(v) (((ULONG_PTR)(v)) / (512 * PAGE_SIZE))
 121 #define ADDR_TO_PDE_OFFSET(v) ((((ULONG_PTR)(v)) / (512 * PAGE_SIZE)))
 122 #define ADDR_TO_PTE_OFFSET(v)  ((((ULONG_PTR)(v)) % (512 * PAGE_SIZE)) / PAGE_SIZE)
 123
 124 #define MiGetPdeOffset ADDR_TO_PDE_OFFSET
 125
 126 #define VAtoPXI(va) ((((ULONG64)va) >> PXI_SHIFT) & 0x1FF)
 127 #define VAtoPPI(va) ((((ULONG64)va) >> PPI_SHIFT) & 0x1FF)
 128 #define VAtoPDI(va) ((((ULONG64)va) >> PDI_SHIFT) & 0x1FF)
 129 #define VAtoPTI(va) ((((ULONG64)va) >> PTI_SHIFT) & 0x1FF)
 130
 131 /* We don't use these hacks */
 132 VOID
 133 FORCEINLINE
 134 MmUpdatePageDir(PEPROCESS Process, PVOID Address, ULONG Size)
 135 {
 136     /* Nothing to do */
 137 }
 138
 139 VOID
 140 FORCEINLINE
 141 MmInitGlobalKernelPageDirectory(VOID)
 142 {
 143     /* Nothing to do */
 144 }
 145
 146 #define IS_ALIGNED(addr, align) (((ULONG64)(addr) & (align - 1)) == 0)
 147 #define IS_PAGE_ALIGNED(addr) IS_ALIGNED(addr, PAGE_SIZE)
 148
 149 /* Easy accessing PFN in PTE */
 150 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
 151
 152 // FIXME, only copied from x86
 153 #define MI_MAKE_LOCAL_PAGE(x)      ((x)->u.Hard.Global = 0)
 154 #define MI_MAKE_DIRTY_PAGE(x)      ((x)->u.Hard.Dirty = 1)
 155 #define MI_PAGE_DISABLE_CACHE(x)   ((x)->u.Hard.CacheDisable = 1)
 156 #define MI_PAGE_WRITE_THROUGH(x)   ((x)->u.Hard.WriteThrough = 1)
 157 #define MI_PAGE_WRITE_COMBINED(x)  ((x)->u.Hard.WriteThrough = 0)
 158 #if !defined(CONFIG_SMP)
 159 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.Write == 1)
 160 #else
 161 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.Writable == 1)
 162 #endif
 163 #define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
 164 #define MI_IS_PAGE_DIRTY(x)        ((x)->u.Hard.Dirty == 1)
 165 #define MI_MAKE_OWNER_PAGE(x)      ((x)->u.Hard.Owner = 1)
 166 #if !defined(CONFIG_SMP)
 167 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.Write = 1)
 168 #else
 169 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.Writable = 1)
 170 #endif
 171
 172 // FIXME!!!
 173 #define PAGE_TO_SECTION_PAGE_DIRECTORY_OFFSET(x) \
 174     ((x) / (4*1024*1024))
 175
 176 #define PAGE_TO_SECTION_PAGE_TABLE_OFFSET(x) \
 177     ((((x)) % (4*1024*1024)) / (4*1024))
 178
 179 #define NR_SECTION_PAGE_TABLES              1024
 180 #define NR_SECTION_PAGE_ENTRIES             1024
 181
 182 //#define TEB_BASE                            0x7FFDE000
 183
 184 #define MI_HYPERSPACE_PTES                  (256 - 1)
 185 #define MI_ZERO_PTES                        (32)
 186 #define MI_MAPPING_RANGE_START              (ULONG)HYPER_SPACE
 187 #define MI_MAPPING_RANGE_END                (MI_MAPPING_RANGE_START + \
 188                                              MI_HYPERSPACE_PTES * PAGE_SIZE)
 189 #define MI_ZERO_PTE                         (PMMPTE)(MI_MAPPING_RANGE_END + \
 190                                              PAGE_SIZE)
 191
 192 /* On x86, these two are the same */
 193 #define MMPDE MMPTE
 194 #define PMMPDE PMMPTE
 195
 196 /*
 197 * FIXME - different architectures have different cache line sizes...
 198 */
 199 #define MM_CACHE_LINE_SIZE                  32
 200