reactos/ntoskrnl/include/internal/amd64/mm.h

   1 /*
   2  * kernel internal memory management definitions for amd64
   3  */
   4 #pragma once
   5
   6 #define _MI_PAGING_LEVELS                   4
   7
   8 /* Memory layout base addresses */
   9 #define MI_LOWEST_VAD_ADDRESS           (PVOID)0x0000000000010000ULL
  10 #define MI_USER_PROBE_ADDRESS           (PVOID)0x000007FFFFFF0000ULL
  11 #define MI_DEFAULT_SYSTEM_RANGE_START   (PVOID)0xFFFF080000000000ULL
  12 #define MI_REAL_SYSTEM_RANGE_START             0xFFFF800000000000ULL
  13 #define HYPER_SPACE                            0xFFFFF70000000000ULL
  14 #define HYPER_SPACE_END                        0xFFFFF77FFFFFFFFFULL
  15 #define MI_SYSTEM_CACHE_WS_START               0xFFFFF78000001000ULL
  16 #define MI_PAGED_POOL_START             (PVOID)0xFFFFF8A000000000ULL
  17 //#define MI_PAGED_POOL_END                      0xFFFFF8BFFFFFFFFFULL
  18 //#define MI_SESSION_SPACE_START                 0xFFFFF90000000000ULL
  19 #define MI_SESSION_VIEW_END                    0xFFFFF97FFF000000ULL
  20 #define MI_SESSION_SPACE_END                   0xFFFFF97FFFFFFFFFULL
  21 #define MM_SYSTEM_SPACE_START                  0xFFFFF98000000000ULL
  22 #define MI_PFN_DATABASE                        0xFFFFFA8000000000ULL
  23 #define MI_NONPAGED_POOL_END            (PVOID)0xFFFFFFFFFFBFFFFFULL
  24 #define MI_HIGHEST_SYSTEM_ADDRESS       (PVOID)0xFFFFFFFFFFFFFFFFULL
  25
  26 /* WOW64 address definitions */
  27 #define MM_HIGHEST_USER_ADDRESS_WOW64   0x7FFEFFFF
  28 #define MM_SYSTEM_RANGE_START_WOW64     0x80000000
  29
  30 #define MI_DEBUG_MAPPING                (PVOID)0xFFFFFFFF80000000ULL // FIXME
  31 #define MI_NON_PAGED_SYSTEM_START_MIN   MM_SYSTEM_SPACE_START // FIXME
  32 #define MI_SYSTEM_PTE_START             MM_SYSTEM_SPACE_START
  33 #define MI_SYSTEM_PTE_END               (MI_SYSTEM_PTE_START + MI_NUMBER_SYSTEM_PTES * PAGE_SIZE - 1)
  34 #define MI_SYSTEM_PTE_BASE              (PVOID)MiAddressToPte(KSEG0_BASE)
  35 #define MM_HIGHEST_VAD_ADDRESS          (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
  36 #define MI_MAPPING_RANGE_START          HYPER_SPACE
  37 #define MI_MAPPING_RANGE_END            (MI_MAPPING_RANGE_START + MI_HYPERSPACE_PTES * PAGE_SIZE)
  38 #define MI_DUMMY_PTE                        (MI_MAPPING_RANGE_END + PAGE_SIZE)
  39 #define MI_VAD_BITMAP                       (MI_DUMMY_PTE + PAGE_SIZE)
  40 #define MI_WORKING_SET_LIST                 (MI_VAD_BITMAP + PAGE_SIZE)
  41
  42 /* Memory sizes */
  43 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT)
  44 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING        ((19*1024*1024) >> PAGE_SHIFT)
  45 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST         ((32*1024*1024) >> PAGE_SHIFT)
  46 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST_BOOST   ((256*1024*1024) >> PAGE_SHIFT)
  47 #define MI_MIN_INIT_PAGED_POOLSIZE            (32 * 1024 * 1024)
  48 #define MI_MAX_INIT_NONPAGED_POOL_SIZE        (128ULL * 1024 * 1024 * 1024)
  49 #define MI_MAX_NONPAGED_POOL_SIZE             (128ULL * 1024 * 1024 * 1024)
  50 #define MI_SYSTEM_VIEW_SIZE                   (16 * 1024 * 1024)
  51 #define MI_MIN_SECONDARY_COLORS               8
  52 #define MI_SECONDARY_COLORS                   64
  53 #define MI_MAX_SECONDARY_COLORS               1024
  54 #define MI_MIN_ALLOCATION_FRAGMENT            (4 * _1KB)
  55 #define MI_ALLOCATION_FRAGMENT                (64 * _1KB)
  56 #define MI_MAX_ALLOCATION_FRAGMENT            (2  * _1MB)
  57 #define MI_SESSION_WORKING_SET_SIZE           (4 * 1024 * 1024)
  58 #define MI_SESSION_VIEW_SIZE                  (20 * 1024 * 1024)
  59 #define MI_SESSION_POOL_SIZE                  (16 * 1024 * 1024)
  60 #define MI_SESSION_IMAGE_SIZE                 (8 * 1024 * 1024)
  61 #define MI_SESSION_SIZE                       (MI_SESSION_VIEW_SIZE + \
  62                                                MI_SESSION_POOL_SIZE + \
  63                                                MI_SESSION_IMAGE_SIZE + \
  64                                                MI_SESSION_WORKING_SET_SIZE)
  65
  66 #define MmSystemRangeStart ((PVOID)MI_REAL_SYSTEM_RANGE_START)
  67
  68 /* Misc constants */
  69 #define MI_NUMBER_SYSTEM_PTES               22000
  70 #define MI_MAX_FREE_PAGE_LISTS              4
  71 #define MI_HYPERSPACE_PTES                  (256 - 1)
  72 #define MI_ZERO_PTES                        (32)
  73 /* FIXME - different architectures have different cache line sizes... */
  74 #define MI_MAX_ZERO_BITS                    53
  75
  76 /* Helper macros */
  77 #define IS_ALIGNED(addr, align) (((ULONG64)(addr) & (align - 1)) == 0)
  78 #define IS_PAGE_ALIGNED(addr) IS_ALIGNED(addr, PAGE_SIZE)
  79
  80 #define MiIsPteOnPdeBoundary(PointerPte) \
  81     ((((ULONG_PTR)PointerPte) & (PAGE_SIZE - 1)) == 0)
  82 #define MiIsPteOnPpeBoundary(PointerPte) \
  83     ((((ULONG_PTR)PointerPte) & (PDE_PER_PAGE * PAGE_SIZE - 1)) == 0)
  84 #define MiIsPteOnPxeBoundary(PointerPte) \
  85     ((((ULONG_PTR)PointerPte) & (PPE_PER_PAGE * PDE_PER_PAGE * PAGE_SIZE - 1)) == 0)
  86
  87 /* MMPTE related defines */
  88 #define MM_EMPTY_PTE_LIST  ((ULONG64)0xFFFFFFFF)
  89 #define MM_EMPTY_LIST  ((ULONG_PTR)-1)
  90
  91 #define ADDR_TO_PAGE_TABLE(v) ((ULONG)(((ULONG_PTR)(v)) / (512 * PAGE_SIZE)))
  92 #define ADDR_TO_PDE_OFFSET(v) ((ULONG)((((ULONG_PTR)(v)) / (512 * PAGE_SIZE))))
  93 #define ADDR_TO_PTE_OFFSET(v)  ((ULONG)((((ULONG_PTR)(v)) % (512 * PAGE_SIZE)) / PAGE_SIZE))
  94
  95 #define MiGetPdeOffset ADDR_TO_PDE_OFFSET
  96
  97 #define VAtoPXI(va) ((((ULONG64)va) >> PXI_SHIFT) & 0x1FF)
  98 #define VAtoPPI(va) ((((ULONG64)va) >> PPI_SHIFT) & 0x1FF)
  99 #define VAtoPDI(va) ((((ULONG64)va) >> PDI_SHIFT) & 0x1FF)
 100 #define VAtoPTI(va) ((((ULONG64)va) >> PTI_SHIFT) & 0x1FF)
 101
 102 /* Easy accessing PFN in PTE */
 103 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
 104 #define PFN_FROM_PDE(v) ((v)->u.Hard.PageFrameNumber)
 105 #define PFN_FROM_PPE(v) ((v)->u.Hard.PageFrameNumber)
 106 #define PFN_FROM_PXE(v) ((v)->u.Hard.PageFrameNumber)
 107
 108 // FIXME, only copied from x86
 109 #define MI_MAKE_LOCAL_PAGE(x)      ((x)->u.Hard.Global = 0)
 110 #define MI_MAKE_DIRTY_PAGE(x)      ((x)->u.Hard.Dirty = 1)
 111 #define MI_MAKE_ACCESSED_PAGE(x)   ((x)->u.Hard.Accessed = 1)
 112 #define MI_PAGE_DISABLE_CACHE(x)   ((x)->u.Hard.CacheDisable = 1)
 113 #define MI_PAGE_WRITE_THROUGH(x)   ((x)->u.Hard.WriteThrough = 1)
 114 #define MI_PAGE_WRITE_COMBINED(x)  ((x)->u.Hard.WriteThrough = 0)
 115 #define MI_IS_PAGE_LARGE(x)        ((x)->u.Hard.LargePage == 1)
 116 #if !defined(CONFIG_SMP)
 117 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.Write == 1)
 118 #else
 119 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.Writable == 1)
 120 #endif
 121 #define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
 122 #define MI_IS_PAGE_DIRTY(x)        ((x)->u.Hard.Dirty == 1)
 123 #define MI_MAKE_OWNER_PAGE(x)      ((x)->u.Hard.Owner = 1)
 124 #if !defined(CONFIG_SMP)
 125 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.Write = 1)
 126 #else
 127 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.Writable = 1)
 128 #endif
 129
 130 /* On x64, these are the same */
 131 #define MMPDE MMPTE
 132 #define PMMPDE PMMPTE
 133 #define MMPPE MMPTE
 134 #define PMMPPE PMMPTE
 135 #define MMPXE MMPTE
 136 #define PMMPXE PMMPTE
 137 #define MI_WRITE_VALID_PPE MI_WRITE_VALID_PTE
 138
 139 #define ValidKernelPpe ValidKernelPde
 140
 141 PMMPTE
 142 FORCEINLINE
 143 MiAddressToPxe(PVOID Address)
 144 {
 145     ULONG64 Offset = (ULONG64)Address >> (PXI_SHIFT - 3);
 146     Offset &= PXI_MASK << 3;
 147     return (PMMPTE)(PXE_BASE + Offset);
 148 }
 149
 150 PMMPTE
 151 FORCEINLINE
 152 MiAddressToPpe(PVOID Address)
 153 {
 154     ULONG64 Offset = (ULONG64)Address >> (PPI_SHIFT - 3);
 155     Offset &= 0x3FFFF << 3;
 156     return (PMMPTE)(PPE_BASE + Offset);
 157 }
 158
 159 PMMPTE
 160 FORCEINLINE
 161 _MiAddressToPde(PVOID Address)
 162 {
 163     ULONG64 Offset = (ULONG64)Address >> (PDI_SHIFT - 3);
 164     Offset &= 0x7FFFFFF << 3;
 165     return (PMMPTE)(PDE_BASE + Offset);
 166 }
 167 #define MiAddressToPde(x) _MiAddressToPde((PVOID)(x))
 168
 169 PMMPTE
 170 FORCEINLINE
 171 _MiAddressToPte(PVOID Address)
 172 {
 173     ULONG64 Offset = (ULONG64)Address >> (PTI_SHIFT - 3);
 174     Offset &= 0xFFFFFFFFFULL << 3;
 175     return (PMMPTE)(PTE_BASE + Offset);
 176 }
 177 #define MiAddressToPte(x) _MiAddressToPte((PVOID)(x))
 178
 179 ULONG
 180 FORCEINLINE
 181 MiAddressToPti(PVOID Address)
 182 {
 183     return ((((ULONG64)Address) >> PTI_SHIFT) & 0x1FF);
 184 }
 185 #define MiAddressToPteOffset(x) MiAddressToPti(x) // FIXME: bad name
 186
 187 ULONG
 188 FORCEINLINE
 189 MiAddressToPxi(PVOID Address)
 190 {
 191     return ((((ULONG64)Address) >> PXI_SHIFT) & 0x1FF);
 192 }
 193
 194
 195 /* Convert a PTE into a corresponding address */
 196 PVOID
 197 FORCEINLINE
 198 MiPteToAddress(PMMPTE PointerPte)
 199 {
 200     /* Use signed math */
 201     return (PVOID)(((LONG64)PointerPte << 25) >> 16);
 202 }
 203
 204 PVOID
 205 FORCEINLINE
 206 MiPdeToAddress(PMMPTE PointerPde)
 207 {
 208     /* Use signed math */
 209     return (PVOID)(((LONG64)PointerPde << 34) >> 16);
 210 }
 211
 212 PVOID
 213 FORCEINLINE
 214 MiPpeToAddress(PMMPTE PointerPpe)
 215 {
 216     /* Use signed math */
 217     return (PVOID)(((LONG64)PointerPpe << 43) >> 16);
 218 }
 219
 220 PVOID
 221 FORCEINLINE
 222 MiPxeToAddress(PMMPTE PointerPxe)
 223 {
 224     /* Use signed math */
 225     return (PVOID)(((LONG64)PointerPxe << 52) >> 16);
 226 }
 227
 228 BOOLEAN
 229 FORCEINLINE
 230 MiIsPdeForAddressValid(PVOID Address)
 231 {
 232     return ((MiAddressToPxe(Address)->u.Hard.Valid) &&
 233             (MiAddressToPpe(Address)->u.Hard.Valid) &&
 234             (MiAddressToPde(Address)->u.Hard.Valid));
 235 }
 236
 237 #define MiPdeToPte(PDE) ((PMMPTE)MiPteToAddress(PDE))
 238 #define MiPteToPde(PTE) ((PMMPDE)MiAddressToPte(PTE))
 239 #define MiPdeToPpe(Pde) ((PMMPPE)MiAddressToPte(Pde))
 240
 241 /* Sign extend 48 bits */
 242 #define MiProtoPteToPte(x) (PMMPTE)(((LONG64)(x)->u.Long) >> 16)
 243
 244 //
 245 // Decodes a Prototype PTE into the underlying PTE
 246 //
 247 #define MiSubsectionPteToSubsection(x)                              \
 248         (PMMPTE)((x)->u.Subsect.SubsectionAddress >> 16)
 249
 250 FORCEINLINE
 251 VOID
 252 MI_MAKE_SUBSECTION_PTE(IN PMMPTE NewPte,
 253                        IN PVOID Segment)
 254 {
 255     ASSERT(FALSE);
 256 }
 257
 258 FORCEINLINE
 259 VOID
 260 MI_MAKE_PROTOTYPE_PTE(IN PMMPTE NewPte,
 261                       IN PMMPTE PointerPte)
 262 {
 263     /* Store the Address */
 264     NewPte->u.Long = (ULONG64)PointerPte << 16;
 265
 266     /* Mark this as a prototype PTE */
 267     NewPte->u.Proto.Prototype = 1;
 268
 269     ASSERT(MiProtoPteToPte(NewPte) == PointerPte);
 270 }
 271
 272 FORCEINLINE
 273 BOOLEAN
 274 MI_IS_MAPPED_PTE(PMMPTE PointerPte)
 275 {
 276     /// FIXME
 277     __debugbreak();
 278     return ((PointerPte->u.Long & 0xFFFFFC01) != 0);
 279 }
 280
 281 VOID
 282 FORCEINLINE
 283 MmInitGlobalKernelPageDirectory(VOID)
 284 {
 285     /* Nothing to do */
 286 }
 287