reactos/ntoskrnl/include/internal/amd64/mm.h

   1 /*
   2  * Lowlevel memory managment definitions
   3  */
   4
   5 #pragma once
   6
   7 /* Helper macros */
   8 #define PAGE_MASK(x)            ((x)&(~0xfff))
   9 #define PAE_PAGE_MASK(x)        ((x)&(~0xfffLL))
  10
  11 /* Memory layout base addresses */
  12 #define HYPER_SPACE                            0xFFFFF70000000000ULL
  13 #define HYPER_SPACE_END                        0xFFFFF77FFFFFFFFFULL
  14 #define MI_SESSION_SPACE_MINIMUM        (PVOID)0xFFFFF90000000000ULL
  15 #define MI_SESSION_VIEW_END             (PVOID)0xFFFFF97FFF000000ULL
  16 #define MI_SESSION_SPACE_END            (PVOID)0xFFFFF98000000000ULL
  17 #define MI_SYSTEM_PTE_START             (PVOID)0xFFFFFAA000000000ULL
  18 #define MI_PAGED_POOL_START             (PVOID)0xFFFFFA8000000000ULL
  19 #define MI_NON_PAGED_SYSTEM_START_MIN          0xFFFFFAA000000000ULL
  20 #define MI_PFN_DATABASE                 (PVOID)0xFFFFFAC000000000ULL
  21 #define MI_NONPAGED_POOL_END            (PVOID)0xFFFFFAE000000000ULL
  22 #define MI_DEBUG_MAPPING                (PVOID)0xFFFFFFFF80000000ULL // FIXME
  23 #define MI_HIGHEST_SYSTEM_ADDRESS       (PVOID)0xFFFFFFFFFFFFFFFFULL
  24 #define MI_SYSTEM_CACHE_WS_START        (PVOID)0xFFFFF78000001000ULL // CHECKME
  25
  26 /* Memory sizes */
  27 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT)
  28 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING         ((19*1024*1024) >> PAGE_SHIFT)
  29 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST          ((32*1024*1024) >> PAGE_SHIFT)
  30 #define MI_MAX_INIT_NONPAGED_POOL_SIZE         (128ULL * 1024 * 1024 * 1024)
  31 #define MI_MAX_NONPAGED_POOL_SIZE              (128ULL * 1024 * 1024 * 1024)
  32 #define MI_MAX_FREE_PAGE_LISTS                 4
  33 #define MI_MIN_INIT_PAGED_POOLSIZE             (32 * 1024 * 1024)
  34 #define MI_SESSION_VIEW_SIZE                   (20 * 1024 * 1024)
  35 #define MI_SESSION_POOL_SIZE                   (16 * 1024 * 1024)
  36 #define MI_SESSION_IMAGE_SIZE                  (8 * 1024 * 1024)
  37 #define MI_SESSION_WORKING_SET_SIZE            (4 * 1024 * 1024)
  38 #define MI_SESSION_SIZE                        (MI_SESSION_VIEW_SIZE + \
  39                                                 MI_SESSION_POOL_SIZE + \
  40                                                 MI_SESSION_IMAGE_SIZE + \
  41                                                 MI_SESSION_WORKING_SET_SIZE)
  42 #define MI_SYSTEM_VIEW_SIZE                    (16 * 1024 * 1024)
  43 #define MI_NUMBER_SYSTEM_PTES 22000
  44
  45 PULONG64
  46 FORCEINLINE
  47 MmGetPageDirectory(VOID)
  48 {
  49     return (PULONG64)__readcr3();
  50 }
  51
  52 PMMPTE
  53 FORCEINLINE
  54 MiAddressToPxe(PVOID Address)
  55 {
  56     ULONG64 Offset = (ULONG64)Address >> (PXI_SHIFT - 3);
  57     Offset &= PXI_MASK << 3;
  58     return (PMMPTE)(PXE_BASE + Offset);
  59 }
  60
  61 PMMPTE
  62 FORCEINLINE
  63 MiAddressToPpe(PVOID Address)
  64 {
  65     ULONG64 Offset = (ULONG64)Address >> (PPI_SHIFT - 3);
  66     Offset &= 0x3FFFF << 3;
  67     return (PMMPTE)(PPE_BASE + Offset);
  68 }
  69
  70 PMMPTE
  71 FORCEINLINE
  72 _MiAddressToPde(PVOID Address)
  73 {
  74     ULONG64 Offset = (ULONG64)Address >> (PDI_SHIFT - 3);
  75     Offset &= 0x7FFFFFF << 3;
  76     return (PMMPTE)(PDE_BASE + Offset);
  77 }
  78 #define MiAddressToPde(x) _MiAddressToPde((PVOID)(x))
  79
  80 PMMPTE
  81 FORCEINLINE
  82 _MiAddressToPte(PVOID Address)
  83 {
  84     ULONG64 Offset = (ULONG64)Address >> (PTI_SHIFT - 3);
  85     Offset &= 0xFFFFFFFFFULL << 3;
  86     return (PMMPTE)(PTE_BASE + Offset);
  87 }
  88 #define MiAddressToPte(x) _MiAddressToPte((PVOID)(x))
  89
  90 /* Convert a PTE into a corresponding address */
  91 PVOID
  92 FORCEINLINE
  93 MiPteToAddress(PMMPTE Pte)
  94 {
  95     /* Use signed math */
  96     LONG64 Temp = (LONG64)Pte;
  97     Temp <<= 25;
  98     Temp >>= 16;
  99     return (PVOID)Temp;
 100 }
 101
 102 BOOLEAN
 103 FORCEINLINE
 104 MiIsPdeForAddressValid(PVOID Address)
 105 {
 106     return ((MiAddressToPxe(Address)->u.Hard.Valid) &&
 107             (MiAddressToPpe(Address)->u.Hard.Valid) &&
 108             (MiAddressToPde(Address)->u.Hard.Valid));
 109 }
 110
 111 #define ADDR_TO_PAGE_TABLE(v) (((ULONG_PTR)(v)) / (512 * PAGE_SIZE))
 112 #define ADDR_TO_PDE_OFFSET(v) ((((ULONG_PTR)(v)) / (512 * PAGE_SIZE)))
 113 #define ADDR_TO_PTE_OFFSET(v)  ((((ULONG_PTR)(v)) % (512 * PAGE_SIZE)) / PAGE_SIZE)
 114
 115 #define VAtoPXI(va) ((((ULONG64)va) >> PXI_SHIFT) & 0x1FF)
 116 #define VAtoPPI(va) ((((ULONG64)va) >> PPI_SHIFT) & 0x1FF)
 117 #define VAtoPDI(va) ((((ULONG64)va) >> PDI_SHIFT) & 0x1FF)
 118 #define VAtoPTI(va) ((((ULONG64)va) >> PTI_SHIFT) & 0x1FF)
 119
 120 /* We don't use these hacks */
 121 VOID
 122 FORCEINLINE
 123 MmUpdatePageDir(PEPROCESS Process, PVOID Address, ULONG Size)
 124 {
 125     /* Nothing to do */
 126 }
 127
 128 VOID
 129 FORCEINLINE
 130 MmInitGlobalKernelPageDirectory(VOID)
 131 {
 132     /* Nothing to do */
 133 }
 134
 135 #define IS_ALIGNED(addr, align) (((ULONG64)(addr) & (align - 1)) == 0)
 136 #define IS_PAGE_ALIGNED(addr) IS_ALIGNED(addr, PAGE_SIZE)
 137
 138 /* Easy accessing PFN in PTE */
 139 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
 140
 141 // FIXME, only copied from x86
 142 #define MI_MAKE_LOCAL_PAGE(x)      ((x)->u.Hard.Global = 0)
 143 #define MI_MAKE_DIRTY_PAGE(x)      ((x)->u.Hard.Dirty = 1)
 144 #define MI_PAGE_DISABLE_CACHE(x)   ((x)->u.Hard.CacheDisable = 1)
 145 #define MI_PAGE_WRITE_THROUGH(x)   ((x)->u.Hard.WriteThrough = 1)
 146 #define MI_PAGE_WRITE_COMBINED(x)  ((x)->u.Hard.WriteThrough = 0)
 147 #if !defined(CONFIG_SMP)
 148 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.Write == 1)
 149 #else
 150 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.Writable == 1)
 151 #endif
 152 #define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
 153 #define MI_IS_PAGE_DIRTY(x)        ((x)->u.Hard.Dirty == 1)
 154 #define MI_MAKE_OWNER_PAGE(x)      ((x)->u.Hard.Owner = 1)
 155 #if !defined(CONFIG_SMP)
 156 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.Write = 1)
 157 #else
 158 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.Writable = 1)
 159 #endif
 160
 161 // FIXME!!!
 162 #define PAGE_TO_SECTION_PAGE_DIRECTORY_OFFSET(x) \
 163     ((x) / (4*1024*1024))
 164
 165 #define PAGE_TO_SECTION_PAGE_TABLE_OFFSET(x) \
 166     ((((x)) % (4*1024*1024)) / (4*1024))
 167
 168 #define NR_SECTION_PAGE_TABLES              1024
 169 #define NR_SECTION_PAGE_ENTRIES             1024
 170
 171 //#define TEB_BASE                            0x7FFDE000
 172
 173 #define MI_HYPERSPACE_PTES                  (256 - 1)
 174 #define MI_ZERO_PTES                        (32)
 175 #define MI_MAPPING_RANGE_START              (ULONG)HYPER_SPACE
 176 #define MI_MAPPING_RANGE_END                (MI_MAPPING_RANGE_START + \
 177                                              MI_HYPERSPACE_PTES * PAGE_SIZE)
 178 #define MI_ZERO_PTE                         (PMMPTE)(MI_MAPPING_RANGE_END + \
 179                                              PAGE_SIZE)
 180
 181 /* On x86, these two are the same */
 182 #define MMPDE MMPTE
 183 #define PMMPDE PMMPTE
 184
 185 /*
 186 * FIXME - different architectures have different cache line sizes...
 187 */
 188 #define MM_CACHE_LINE_SIZE                  32
 189